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TUSB2046B-Q1
SLLSE50A – SEPTEMBER 2010 – REVISED OCTOBER 2015
TUSB2046B-Q1 4-Port HUB for the Universal Serial BUS
With Optional Serial EEPROM Interface
1 Features
3 Description
•
•
The TUSB2046B-Q1 is a 3.3-V CMOS hub device
that provides one upstream port and four downstream
ports in compliance with the Universal Serial Bus
(USB) specification as a full-speed hub. Because this
device is implemented with a digital state machine
instead of a microcontroller, no firmware
programming is required. Fully-compliant USB
transceivers are integrated into the ASIC for all
upstream and downstream ports. The downstream
ports support both full-speed and low-speed devices
by automatically setting the slew rate according to the
speed of the device attached to the ports. The
configuration of the BUSPWR pin selects either the
bus-powered or the self-powered mode.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Fully Compliant With the USB Specification as a
Full-Speed Hub: TID #30220231
32-Pin VQFN Package With a 0.5-mm Pitch
3.3-V Low-Power ASIC Logic
Integrated USB Transceivers
State Machine Implementation Requires No
Firmware Programming
One Upstream Port and Four Downstream Ports
All Downstream Ports Support Full-Speed and
Low-Speed Operations
Two Power-Source Modes
– Self-Powered Mode
– Bus-Powered Mode
Power Switching and Overcurrent Reporting Is
Provided Ganged or Per Port
Supports Suspend and Resume Operations
Supports Programmable Vendor ID and Product
ID With External Serial EEPROM
3-State EEPROM Interface Allows EEPROM
Sharing
Push-Pull Outputs for PWRON Eliminate the Need
for External Pullup Resistors
Noise Filtering on OVRCUR Provides Immunity to
Voltage Spikes
Package Pinout Allows Two-Layer PCB
Low EMI Emission Achieved by a 6-MHz Crystal
Input
Migrated From Proven TUSB2040 Hub
Lower Cost Than the TUSB2040 Hub
Enhanced System ESD Performance
Supports 6-MHz Operation Through a Crystal
Input or a 48-MHz Input Clock
No Special Driver Requirements; Works
Seamlessly With Any System Having USB Stack
Support
Configuring the GANGED input determines the
power-switching and overcurrent-detection modes for
the downstream ports. External power-management
devices, such as the TPS2044, are required to
control the 5-V source to the downstream ports
according to the corresponding value of the PWRON
pin. On detecting any overcurrent conditions, the
power-management device sets the corresponding
OVRCUR pin of the TUSB2046B-Q1 to a logic low. If
GANGED is high, all PWRON outputs switch
together, and if any OVRCUR is activated, all ports
transition to the power-off state. If GANGED is low,
the PWRON outputs and OVRCUR inputs operate on
a per-port basis.
Device Information(1)
PART NUMBER
TUSB2046B-Q1
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Key Graphic
Sense
Op-Amp
VBAT
D+/D- (Host)
D+/D- (Client(s))
USB Charging
Controller
DGDC
Buck
USB
Controller
TUSB2046BI-Q1
4-Port Hub
USB Data Switch
ESD
Protection
VBUS
D+/D-
USB Data
Repeater
2 Applications
•
Automotive Infotainment
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB2046B-Q1
SLLSE50A – SEPTEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
7.6
6
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Differential Driver Switching Characteristics FullSpeed Mode...............................................................
7.7 Differential Driver Switching Characteristics Low
Speed Mode...............................................................
7.8 Typical Characteristics ..............................................
8
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
8.5 Programming........................................................... 12
9
Applications and Implementation ...................... 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 17
10 Power Supply Recommendations ..................... 22
10.1 TUSB2046BI-Q1 Power Supply ............................ 22
10.2 Downstream Port Power ....................................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
8
8
9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2013) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed part number here and throughout the text and illustrations of the data sheet from TUSB2046B to
TUSB2046BI-Q1..................................................................................................................................................................... 1
•
Deleted VF Package pinout drawing ..................................................................................................................................... 4
•
Revised pinout drawing .......................................................................................................................................................... 4
2
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SLLSE50A – SEPTEMBER 2010 – REVISED OCTOBER 2015
5 Description (Continued)
The TUSB2046B-Q1 provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the
TSTMODE pin controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL
circuitry is selected to drive the internal core of the device. When TSTMODE is high, the TSTPLL/48MCLK input
is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal
oscillator cell is also powered down while TSTMODE is high.
Low EMI emission is achieved because the TUSB2046B-Q1 is able to use a 6-MHz crystal input. Connect the
crystal as shown in Figure 8. An internal PLL then generates the 48-MHz clock used to sample data from the
upstream port and to synchronize the 12 MHz used for the USB clock. If low-power suspend and resume are
desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting
the output to the XTAL1 pin and leaving the XTAL2 pin open. The oscillator TTL output must not exceed 3.6 V.
For 48-MHz operation, the clock cannot be generated with a crystal using the XTAL2 output because the internal
oscillator cell supports only the fundamental frequency.
See Figure 7 and Figure 9 in the input clock configuration section for more-detailed information regarding the
input clock configuration.
The EXTMEM pin enables or disables the optional EEPROM interface. When the EXTMEM pin is high, the
product ID (PID) displayed during enumeration is the general-purpose USB hub. For this default, pin 5 is disabled
and pin 6 functions as the GANGED input pin. If custom PID and vendor ID (VID) descriptors are desired, the
EXTMEM pin must be low (EXTMEM = 0). For this configuration, pin 5 and pin 6 function as the EEPROM
interface with pin 5 and pin 6 functioning as EECLK and EEDATA, respectively. See Table 1 for a description of
the EEPROM memory map.
Other useful features of the TUSB2046B-Q1 include a package with a 0.8-mm pin pitch for easy PCB routing and
assembly, push-pull outputs for the PWRON pins to eliminate the need for pullup resistors required by traditional
open-collector I/Os, and OVRCUR pins having noise filtering for increased immunity to voltage spikes.
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TUSB2046B-Q1
SLLSE50A – SEPTEMBER 2010 – REVISED OCTOBER 2015
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6 Pin Configuration and Functions
TSTPLL/48MCLK
EXTMEM
30
29
28
27
26
VCC
GND
31
XTAL1
32
XTAL2
SUSPND
TSTMODE
RHB Package
32-Pin VQFN With Exposed Thermal Pad
Top View
DP0
1
25
24
DP4
DM0
2
23
DM4
VCC
3
22
OVRCUR4
RESET
4
21
PWRON4
EECLK
5
20
DP3
EEDATA/GANGED
6
19
DM3
GND
7
18
OVRCUR3
BUSPWR
8
9
10
11
12
13
14
15
17
16
PWRON
OVRCUR1
DM1
DP1
PWRON2
OVRCUR2
DM2
DP2
Thermal Pad
PWRON3
Pin Functions
PIN
NAME
NO.
BUSPWR
I/O
DESCRIPTION
Power source indicator. BUSPWR is an active-high input that indicates whether the downstream
ports source their power from the USB cable or a local power supply. For the bus-power mode,
this pin must be pulled to 3.3 V, and for the self-powered mode, this pin must be pulled low. Input
must not change dynamically during operation.
8
I
DM0
2
I/O
Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1
11
DM2
15
DM3
19
I/O
USB differential data minus. DM1–DM4 paired with DP1–DP4 support up to four downstream USB
ports.
DM4
23
DP0
1
I/O
Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
DP1
12
DP2
16
DP3
20
I/O
USB differential data plus. DP1–DP4 paired with DM1–DM4 support up to four downstream USB
ports.
DP4
24
EECLK
5
O
EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK pin
is disabled and must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3state serial clock output to the EEPROM with a 100-μA internal pulldown.
EEDATA/
GANGED
6
I/O
EEPROM serial data- and power-management mode indicator. When EXTMEM is high,
EEDATA/GANGED selects between ganged or per-port power overcurrent detection for the
downstream ports. When EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the
EEPROM and is internally pulled down with a 100-μA pulldown. This standard TTL input must not
change dynamically during operation.
EXTMEM
26
I
When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is
low, pins 5 and 6 are configured as the clock and data pins of the serial EEPROM interface,
respectively.
GND
4
7, 28
GND pins must be tied to ground for proper operation.
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Pin Functions (continued)
PIN
NAME
NO.
OVRCUR1
10
OVRCUR2
14
OVRCUR3
18
OVRCUR4
22
PWRON1
9
PWRON2
13
PWRON3
17
PWRON4
21
I/O
DESCRIPTION
I
Overcurrent input. OVRCUR1–OVRCUR4 are active-low. For per-port overcurrent detection, one
overcurrent input is available for each of the four downstream ports. In the ganged mode, any
OVRCUR input may be used and all OVRCUR pins must be tied together. OVRCUR pins are
active-low inputs with noise-filtering logic.
O
Power-on and -off control signals. PWRON1–PWRON4 are active-low, push-pull outputs. Pushpull outputs eliminate the pullup resistors which open-drain outputs require. However, the external
power switches that connect to these pins must be able to operate with 3.3-V inputs because
these outputs cannot drive 5-V signals.
RESET
4
I
RESET is an active-low TTL input with hysteresis and must be asserted at power up. When
RESET is asserted, all logic is initialized. Generally, a reset with a pulse duration between 100 μs
and 1 ms is recommended after 3.3-V VCC reaches 90% of its full value. The clock signal must be
active during the last 60 μs of the reset window.
SUSPND
32
O
Suspend status. SUSPND is an active-high output available for external logic power-down
operations. During the suspend mode, SUSPND is high. SUSPND is low for normal operation.
TSTMODE
31
I
Test or mode pin. TSTMODE is used as a test pin during production testing. This pin must be tied
to ground or 3.3-V VCC for normal 6-MHz or 48-MHz operation, respectively.
TSTPLL/
48MCLK
27
I/O
Test or 48-MHz clock input. TSTPLL/48MCLK is used as a test pin during production testing. This
pin must be tied to ground for normal 6-MHz operation. If 48-MHz input clock is desired, a 48-MHz
clock source (no crystal) can be connected to this input pin.
VCC
3, 25
3.3-V supply voltage
XTAL1
30
I
Crystal 1. XTAL1 is a 6-MHz crystal input with 50% duty cycle. An internal PLL generates the 48MHz and 12-MHz clocks used internally by the ASIC logic.
XTAL2
29
O
Crystal 2. XTAL2 is a 6-MHz crystal output. This pin must be left open when using an oscillator.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage (2)
–0.5
3.6
V
VI
Input voltage
–0.5
VCC + 0.5
V
VO
Output voltage
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0 V or VI < VCC
±20
mA
IOK
Output clamp current
VO < 0 V or VO < VCC
±20
mA
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage levels are with respect to GND.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002
(1)
±3000
Charged device model (CDM), per AEC Q100-011
±2000
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
VCC
Supply voltage
VI
VO
NOM
MAX
UNIT
3.3
3.6
V
Input voltage, TTL or LVCMOS
0
VCC
V
Output voltage, TTL or LVCMOS
0
VCC
V
VIH(REC)
High-level input voltage, signal-ended receiver
2
VCC
V
VIL(REC)
Low-level input voltage, signal-ended receiver
0.8
V
VIH(TTL)
High-level input voltage, TTL or LVCMOS
2
VCC
V
VIL(TTL)
Low-level input voltage, TTL or LVCMOS
0
0.8
V
R(DRV)
External series differential-driver resistor
22 (–5%)
22 (5%)
Ω
f(OPRH)
Operating (dc differential driver) high-speed mode
12
Mb/s
f(OPRL)
Operating (dc differential driver) low-speed mode
1.5
Mb/s
VICR
Common-mode input-range differential receiver
2.5
V
tt
Input transition times, TTL or LVCMOS
0
25
ns
TJ
Junction temperature range
–40
115
°C
TA
Operating free-air temperature
–40
85
°C
6
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7.4 Thermal Information
TUSB2046B-Q1
THERMAL METRIC (1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
35.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.4
°C/W
RθJB
Junction-to-board thermal resistance
9.9
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
9.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TTL or
LVCMOS
VOH
High-level output voltage
IOH = –4 mA
R(DRV) = 15 kΩ to GND
USB data
lines
IOH = –12 mA (without R(DRV))
TTL or
LVCMOS
VOL
Low-level output voltage
VIT+
Positive input threshold
USB data
lines
Negative-input threshold
Input hysteresis (1)
(VT+ – VT–)
High-impedance output
current
IOZ
MAX
VCC – 0.5
IOL = 4 mA
0.5
R(DRV) = 1.5 kΩ to 3.6 V
0.3
IOL = 12 mA (without R(DRV))
0.5
0.8 V ≤ VICR ≤ 2.5 V
TTL or
LVCMOS
TTL or
LVCMOS
V
V
1.8
0.8
0.8 V ≤ VICR ≤ 2.5 V
UNIT
V
2.8
1.8
Single-ended
Vhys
TYP
VCC – 0.5
TTL or
LVCMOS
Single-ended
VIT–
MIN
V
1
0.3
0.7
300
500
Single-ended
0.8 V ≤ VICR ≤ 2.5 V
TTL or
LVCMOS
V = VCC or GND (2)
±10
USB data
lines
0 V ≤ VO ≤ VCC
±10
mV
μA
IIL
Low-level input current
TTL or
LVCMOS
VI = GND
–1
μA
IIH
High-level input current
TTL or
LVCMOS
VI = VCC
1
μA
z0(DRV)
Driver output impedance (3)
USB data
lines
Static VOH or VOL
7.1
19.9
Ω
VID
Differential input voltage
USB data
lines
0.8 V ≤ VICR ≤ 2.5 V
0.2
ICC
Input supply current
(1)
(2)
(3)
Normal operation
Suspend mode
V
40
mA
1
μA
Applies for input buffers with hysteresis.
Applies for open-drain buffers.
Characterization only. Limits are approved by design and are not production tested.
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7.6 Differential Driver Switching Characteristics Full-Speed Mode
over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Transition rise time for DP or DM
See Figure 1 and Figure 2
4
20
ns
tf
Transition fall time for DP or DM
See Figure 1 and Figure 2
4
20
ns
t(RFM)
Rise and fall time matching (1)
(tr / tf) × 100
90%
110%
VO(CRS)
Signal crossover output voltage (1)
1.3
2
(1)
V
Characterization only. Limits are approved by design and are not production tested.
7.7 Differential Driver Switching Characteristics Low Speed Mode
over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tr
Transition rise time for DP or DM (1)
CL = 200 pF to 600 pF, see Figure 1 and Figure 2
75
300
ns
tf
Transition fall time for DP or DM (1)
CL = 200 pF to 600 pF, see Figure 1 and Figure 2
75
300
ns
80%
120%
1.3
2
(1)
t(RFM)
Rise and fall time matching
VO(CRS)
Signal crossover output voltage (1)
(1)
(tr / tf) × 100
CL = 200 pF to 600 pF
V
Characterization only. Limits are approved by design and are not production tested.
22 Ω
1.5 kΩ
15 kΩ
22 Ω
15 kΩ
Figure 1. Differential Driver Switching Load
Figure 2. Differential Driver Timing Waveforms
Vhys
Logic high
VCC
VIH
VIT+
VIT-
VIL
Logic low
0V
Figure 3. Single-Ended Receiver Input-Signal Parameter Definitions
8
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V ID - Diff erential Receiver Input Sensitivity - V
7.8 Typical Characteristics
1.5
1.3
1
0.5
0.2
0
0
3
1
2
3.6
0.8
2.5
VICR - Common Mode Input Rang e - V
4
Figure 4. Differential Receiver Input Sensitivity Versus Common-Mode Input Range
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8 Detailed Description
8.1 Overview
The TUSB2046BI-Q1 is a USB 2.0-compliant hub at full-speed as assigned by USB-IF TID #30220231. The
device will enumerate high–speed devices, but limit the throughput to full–speed bit rates. The single upstream
port and four downstream ports are equipped to support full-speed or low-speed connections. In the event of an
overcurrent condition or failure, all or individual power pins can be configured to fail-safe open. A variety of
clocking options allow the internal core of the device to be driven internally or externally with a crystal or
resonator to achieve low EMI emission. The device contains an EEPROM controller for connection to an external
EEPROM, which allows for automatic loading of static configuration data upon power-on reset, pin reset, or
software reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and the
MAC address.
8.2 Functional Block Diagram
DP0
DM0
1
2
USB
Transceiver
32
27
SUSPND
TSTPLL/48MCLK
30 XTAL1
29
Suspend/Resume
Logic and
Frame Timer
HUB Repeater
OSC/PLL
XTAL2
SIE
4
26
6
SIE Interface
Logic
Serial
EEPROM
Interface
5
RESET
EXTMEM
EEDATA/GANGED
EECLK
Port 1
Logic
Port 2
Logic
Hub/Device
Command
Decoder
Port 3
Logic
8
BUSPWR
Port 4
Logic
USB
Transceiver
24
DP4
10
23
DM4
USB
Transceiver
20
DP3
19
DM3
USB
Transceiver
16
DP2
15
DM2
USB
Transceiver
12
DP1
Hub
Power
Logic
10, 14, 18, 22
OVRCUR1 – OVRCUR4
11
DM1
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9, 13, 17, 21
PWRON1 – PWRON4
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8.3 Feature Description
8.3.1 USB Power Management
The TUSB2046BI-Q1 supports both bus-powered and self-powered modes. External power-management
devices, such as the TPS2044, are required to control the 5-V power source switching (ON/OFF) to the
downstream ports and to detect an overcurrent condition from the downstream ports individually or ganged.
Outputs from external power devices provide overcurrent inputs to the TUSB2046BI-Q1 OVRCUR pins in case of
an overcurrent condition, the corresponding PWRON pins are disabled by the TUSB2046BI-Q1. In the ganged
mode, all PWRON signals transition simultaneously, and any OVRCUR input can be used. In the nonganged
mode, the PWRON outputs and OVRCUR inputs operate on a per-port basis.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types
of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port
basis). Individual-port management requires power-management devices for each individual downstream port,
but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only
powers down the port that has the condition. The ganged configuration uses fewer power management devices
and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all
the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2046BI-Q1 supports four modes
of power management: bus-powered hub with either individual-port power management or ganged-port power
management, and the self-powered hub with either individual-port power management or ganged-port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2046BI-Q1
along with the power-management devices needed to implement a fully USB compliant system.
8.3.2 Clock Generation
The TUSB2046BI-Q1 provides the flexibility of using either a 6-MHz or a 48-MHz clock. The logic level of the
MODE pin controls the selection of the clock source. When MODE is low, the output of the internal APLL circuitry
is selected to drive the internal core of the chip. When MODE is high, the XTAL1 input is selected as the input
clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered
down while MODE is high. For 6-MHz operation, TUSB2046BI-Q1 requires a 6-MHz clock signal on XTAL1 pin
(with XTAL2 for a crystal) from which its internal APLL circuitry generates a 48-MHz internal clock to sample the
data from the upstream port. For 48-MHz operation, the clock cannot be generated with a crystal, using the
XTAL2 output, since the internal oscillator cell only supports the fundamental frequency. If low-power suspend
and resume are desired, a passive crystal or resonator must be used, although the hub supports the flexibility of
using any device that generates a 6-MHz clock. Because most oscillators cannot be stopped while power is on,
their use prohibits low-power suspend, which depends on disabling the clock. When the oscillator is used, by
connecting its output to the XTAL1 pin and leaving the XTAL2 pin open, its TTL output level cannot exceed 3.6
V. If a 6-MHz oscillator is used, it must be stopped at logic low whenever SUSPND is high. For crystal or
resonator implementations, the XTAL1 pin is the input and the XTAL2 pin is used as the feedback path. A
sample crystal tuning circuit is shown in Figure 8.
A sample crystal turning circuit is show in Figure 8.
8.4 Device Functional Modes
8.4.1 Vendor ID and Product ID With External Serial EEPROM
The EXTMEM enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor and
product IDs (VID and PID) use defaults, such that the message displayed during enumeration is General
Purpose USB Hub. For this configuration, pin 6 functions as the GANGED input pin and the EECLK is unused. If
custom VID and PID descriptors are desired, the EXTMEM must be tied low (EXTMEM = 0) and a SGS
Thompson M93C46 EEPROM, or equivalent, stores the programmable VID, PID, and GANGED values. For this
configuration, pins 5 and 6 function as the EEPROM interface signals with pin 5 as EECLK and pin 6 as
EEDATA, respectively.
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8.5 Programming
8.5.1 Programming the EEPROM
An SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID and PID. When the
EEPROM interface is enabled (EXTMEM = 0), the EECLK and EEDATA are internally pulled down (100 μA)
inside the TUSB2046B-Q1. The internal pulldowns are disabled when the EEPROM interface is disabled
(EXTMEM = 1).
The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting pin 6 of the
EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16-bit words.
Table 1. EEPROM Memory Map
ADDRESS
00000
00001
00010
D15
0
D14
GANGED
D13
00000
VID high-byte
PID high-byte
XXXXXXXX
D12–D8
00000
D7–D0
00000000
VID low-byte
PID low-byte
The D and Q signals of the EEPROM must be tied together using a 1-kΩ resistor with the common I/O
operations forming a single-wire bus. After system power-on reset, the TUSB2046B-Q1 performs a one-time
access read operation from the EEPROM if the EXTMEM pin is pulled low and the chip select(s) of the EEPROM
is connected to the system power-on reset. Initially, the EEDATA pin is driven by the TUSB2046B-Q1 to send a
start bit (1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read
instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data to
the output shift register. At this point, the hub stops driving the EEDATA pin and the EEPROM starts driving. A
dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most significant
bit (MSB) first.
The output data changes are triggered by the rising edge of the clock provided by the TUSB2046B-Q1 on the
EECLK pin. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next memory
location by automatically incrementing the address internally. Any EEPROM used must have the automatic
internal address advance function. After reading the three words of data from the EEPROM, the TUSB2046B-Q1
puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share
the EEPROM. The EEPROM read operation is summarized in Figure 5. For more details on EEPROM operation,
refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data sheet.
12
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D
C
S
Start
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A5
Hub Driving Data Line
Read OP Code(10)
Other
Address
Bits
A1
6 Bit Address (000000)
A0
Dummy
Bit
MSB of The
First Word
D15
Other
LSB of
Data Bits Third Word
D0
EEPROM Driving Data Line
D14
48 Data Bits
MSB of
Fourth Word
XX
Don’t Care
3-Stated
With Internal
Pulldown
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TUSB2046B-Q1
Figure 5. EEPROM Read Operation Timing Diagram
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that
provides both communication and power distribution. The power configurations are bus-powered and selfpowered modes. The maximum current that may be drawn from the USB 5-V line during power up is 100 mA.
For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable. A buspowered hub must always be connected downstream to a self-powered hub unless it is the only hub connected
to the PC and there are no high-powered functions connected downstream. In the self-powered mode, the hub is
connected to an external power supply and can supply up to 500 mA to each downstream port. High-powered
functions may draw a maximum of 500 mA from each downstream port and may only be connected downstream
to self-powered hubs. Per the USB specification, in the bus-powered mode, each downstream port can provide a
maximum of 100 mA of current, and in the self-powered mode, each downstream port can provide a maximum of
500 mA of current.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types
of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port
basis). Individual-port management requires power-management devices for each individual downstream port,
but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only
powers down the port that has the condition. The ganged configuration uses fewer power management devices
and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all
the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2046B-Q1 supports four modes
of power management: bus-powered hub with either individual-port power management or ganged-port power
management, and the self-powered hub with either individual-port power management or ganged-port power
management. Texas Instruments supplies the complete hub solution with the TUSB2036 (2/3-port), TUSB2046BQ1, and the TUSB2077 (7-port) hubs along with the power-management devices needed to implement a fully
USB specification-compliant system.
A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a
single personal computer (see Figure 6).
PC
With Root Hub
Monitor
With 4-Port Hub (Self-Powered)
Printer
With 4-Port Hub
(Self-Powered)
Scanner
Digital
Scanner
Figure 6. USB-Tiered Configuration Example
14
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Application Information (continued)
9.1.1 Input Clock Configuration
The input clock configuration logic of TUSB2046B-Q1 is enhanced to accept a 6-MHz crystal or 48-MHz on-theboard clock source with a simple tie-off change on TSTMODE (pin 31).
•
A 6-MHz input clock configuration is shown in Figure 7.
In this mode, both the TSTMODE and TSTPLL/48MCLK pins must be tied to ground. The hub is configured to
use the 6-MHz clock on pins 30 and 29, which are XTAL1 and XTAL2, respectively, on the TUSB2046B-Q1.
This is identical to the TUSB2046.
TUSB2046BI-Q1 USB HUB
3.3 V
30
XTAL1
29
Open
XTAL2
31
TSTMODE
48-MHz Oscillator
or on Board Clock Source 27
TSTPLL/48MCLK
Figure 7. 6-MHz Input Clock Configuration
Figure 8 is an example of how to generate the 6-MHz clock signal.
CL
XTAL1
XTAL2
C1
C2
NOTE: This figure assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd
are determined using a Fox Electronics part number HC49U-6.00MHz 30\50\0-70\20 crystal or equivalent, which
means ±30 ppm at 25°C and ±50 ppm from 0°C to 70°C. The characteristics for the crystal include a load capacitance
(CL) of 20 pF, maximum shunt capacitance (Co) of 7 pF, and the maximum ESR of 50 Ω. In order to ensure enough
negative resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain, and Rd = 1.5 kΩ is recommended.
Figure 8. Crystal Tuning Circuit
•
A 48-MHz input clock configuration is shown in Figure 9.
In this mode, both TSTMODE and XTAL1 pins must be tied to 3.3-V VCC. The hub accepts the 48-MHz clock
input on TSTPLL/48MCLK (pin 27). XTAL2 must be left floating (open) for this configuration. Only the
oscillator or the onboard clock source is accepted for this mode. A crystal can not be used for this mode,
since the chip’s internal oscillator cell only supports the fundamental frequency.
TUSB2046BI-Q1 USB HUB
3.3 V
30
XTAL1
29
Open
XTAL2
31
TSTMODE
48-MHz Oscillator
or on Board Clock Source 27
TSTPLL/48MCLK
Figure 9. 48-MHz Input Clock Configuration
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Application Information (continued)
Figure 10 is a block diagram example of how to connect the external EEPROM if a custom product ID and
vendor ID are desired. Figure 5 shows the EEPROM read operation timing diagram. Figure 13, Figure 14, and
Figure 11 illustrate how to connect the TUSB2046B-Q1 device for different power source and port powermanagement combinations.
TUSB2046BI-Q1 USB Hub
DP1–DP4
DM1–DM4
Ω
OVRCUR1–
OVRCUR4
PWRON1–
PWRON4
Figure 10. Typical Application of the TUSB2046B-Q1 USB Hub
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9.2 Typical Applications
9.2.1 Self-Powered Hub, Individual-Port Power Management
TUSB2046BI-Q1
D
1.5 kΩ
SN75240
Ω
Ω
A
SN75240
3.3 V LDO
A
C
100 µF
Ω
Ω
Ω
Ω
SN75240
B
A
100 µF
TPS2044
B
A
100 µF
100 µF
B
B
NOTES: A. TPS2044, TPS2042, and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044.
The OCn outputs of the TPS204n are open-drain. A 10-kΩ pullup is recommended.
B. 120 µF per hub is the minimum required per the USB specification. However, TI recommends a 100-µF, low-ESR,
tantalum capacitor per port for immunity to voltage droop.
C. LDO is a 5-V-to-3.3-V voltage regulator.
D. All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter
capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub
terminal and the series resistor, as per section 7.1.6 of the USB specification.
Figure 11. TUSB2046B-Q1 Self-Powered Hub, Individual-Port Power-Management Application
9.2.1.1 Design Requirements
For this example, follow the design parameters listed in Table 2.
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Typical Applications (continued)
Table 2. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
VCC Supply
3.3 V
Downstream Ports
4
Power Management
Individual-Port
Clock Source
6-MHz Crystal
External EEPROM
No
Power Source Mode
Self-Powered
9.2.1.2 Detailed Design Procedure
In a self-powered configuration, the TUSB2046-Q1 can be implemented for individual-port power management
when used with the TPS2044, because it can supply 500 mA of current to each downstream port, and can
provide current limiting on a per-port basis. When the hub detects a fault on a downstream port, power is
removed from the port with the fault; the remaining ports continue to operate normally. Self-powered hubs are
required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient
suppressors reduce inrush current and voltage spikes on the data lines.
9.2.1.3 Application Curve
Figure 12. Downstream Port 1
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9.2.2 Bus-Powered Hub, Ganged-Port Power Management
When used in bus-powered mode, the TUSB2046B-Q1 supports up to four downstream ports by controlling a
TPS2041 device which is capable of supplying 100 mA of current to each downstream port. Bus-powered hubs
must implement power switching to ensure current demand is held below 100 mA when the hub is hot-plugged
into the system. Utilizing the TPS2041 for ganged-port power management provides overcurrent protection for
the downstream ports. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data
lines. The OVRCUR signals must be tied together for a ganged operation.
TUSB2046BI-Q1
1.5 kΩ
3.3 V
Downstream
Ports
D
D+
SN75240
A
SN75240
3.3 V LDO
A
D−
Ferrite Beads
A C
B D
15 kΩ
15 kΩ
GND
A
5V
100 µF
15 kΩ
B
15 kΩ
D+
D−
Ferrite Beads
GND
A C
B D
15 kΩ
15 kΩ
SN75240
5V
A
100 µF
B
15 kΩ
15 kΩ
TPS2041
EN
D+
D−
A
Ferrite Beads
GND
IN
IN
5V
1 µF
100 µF
B
OUT
OUT
OUT
OC
D+
D−
Ferrite Beads
GND
5V
100 µF
B
NOTES: A. TPS2041 and SN75240 are Texas Instruments devices. The OCn outputs of the TPS204n are open-drain. A 10-kΩ pullup is
recommended.
B. 120 µF per hub is the minimum required per the USB specification. However, TI recommends a 100-µF, low-ESR,
tantalum capacitor per port for immunity to voltage droop.
C. LDO is a 5-V-to-3.3-V voltage regulator
D. All USB DP, DM signal pairs require series resistors of approximately 27 Ω to ensure proper termination. An optional filter
capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub
terminal and the series resistor, as per section 7.1.6 of the USB specification.
Figure 13. TUSB2046B-Q1 Bus-Powered Hub, Ganged-Port Power-Management Application
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9.2.2.1 Design Requirements
Table 3 lists the design parameters for this example.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VCC Supply
3.3 V
Downstream Ports
4
Power Management
Individual-Port
Clock Source
6-MHz Crystal
External EEPROM
No
Power Source Mod
Self-Powered
9.2.2.2 Detailed Design Procedures
In a self-powered configuration, the TUSB2046-Q1 can be implemented for individual-port power management
when used with the TPS2044 because it is capable of supplying 500 mA of current to each downstream port and
can provide current limiting on a per-port basis. When the hub detects a fault on a downstream port, power is
removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered
hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient
suppressors reduce inrush current and voltage spikes on the data lines.
9.2.3 Self-Powered Hub, Ganged-Port Power Management
The TUSB2046B-Q1 can also be implemented for ganged-port power management in a self-powered
configuration. The implementation is very similar to the bus-powered example with the exception that a selfpowered port supplies 500 mA of current to each downstream port. The overcurrent protection can be provided
by a TPS2044 quad device or a TPS2024 single power switch.
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TUSB2046BI-Q1
1.5 kΩ
D
SN75240
A
Ω
Ω
3.3 V LDO
C
SN75240
Ω
Ω
A
100 µF
B
Ω
Ω
SN75240
Ω
Ω
TPS2044
A
100 µF
B
A
100 µF
100 µF
B
B
NOTES: A. TPS2044, TPS2042, and SN75240 are Texas Instruments devices. The TPS2042 can be substituted for the TPS2044. The
OCn outputs of the TPS204n are open-drain. A 10-kΩ pullup is recommended.
B. 120 µF per hub is the minimum required per the USB specification. However, TI recommends a 100-µF, low-ESR,
tantalum capacitor per port for immunity to voltage droop.
C. LDO is a 5-V-to-3.3-V voltage regulator.
D. All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter
capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub
terminal and the series resistor, as per section 7.1.6 of the USB specification.
Figure 14. TUSB2046B-Q1 Self-Powered Hub, Ganged-Port Power-Management Application
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10 Power Supply Recommendations
10.1 TUSB2046BI-Q1 Power Supply
VCC should be implemented as a single power plane.
• The VCC pins of the TUSB2046B-Q1 supply 3.3-V power rail to the I/O of the TUSB2046B-Q1. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
• All power rails require a 10-μF capacitor or 1-μF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as
close to the TUSB2046BI-Q1 power pins as possible with an optimal grouping of two of differing values per
pin.
10.2 Downstream Port Power
•
•
•
The downstream port power, VBUS, must be supplied by a source capable of supplying 5 V and up to 500
mA per port. Downstream port power switches can be controlled by the TUSB2046B-Q1 signals. It is also
possible to leave the downstream port power always enabled.
A large bulk low-ESR capacitor of 22 μF or larger is required on each downstream port’s VBUS to limit in-rush
current.
The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both
ESD and EMI reasons. A 0.1-μF capacitor on the USB connector side of the ferrite provides a low impedance
path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.
11 Layout
11.1 Layout Guidelines
11.1.1 Placement
1. A 0.1 μF should be placed as close as possible on VCC power pin.
2. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.
3. If a crystal is used, it must be placed as close as possible to the TUSB2046-Q1’s XTAL1 and XTAL2 pins.
4. Place voltage regulators as far away as possible from the TUSB2046-Q1, the crystal, and the differential
pairs.
5. In general, the large bulk capacitors associated with the power rail should be placed as close as possible to
the voltage regulators.
11.1.2 Differential Pairs
1. Must be designed with a differential impedance of 90 Ω ±10%.
2. Route all differential pairs on the same layer adjacent to a solid ground plane.
3. Do not route differential pairs over any plane split.
4. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
5. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore
minimize the impact bends have on EMI.
6. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for USB
2.0 differential pair signals is eight inches. Longer trace lengths require very careful routing to assure proper
signal integrity.
7. Match the etch lengths of the differential pair traces. The USB 2.0 differential pairs should not exceed 50 mils
relative trace length difference.
22
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Layout Guidelines (continued)
8. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB2046-Q1 device.
9. Do not place power fuses across the differential pair traces.
11.1.3 Ground
TI recommends using only one board ground plane in the design. This provides the best image plane for signal
traces running above the plane. The thermal pad of the TUSB2046-Q1 and any of the voltage regulators should
be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port
connectors on a different plane for EMI and ESD purposes.
Voltage
Regulator
System POR
VCC
EXTMEM
TSTPLL/48
GND
XTAL2
XTAL1
TSTMODE
SUSPND
11.2 Layout Example
DP0
DP4
DM0
DM4
VCC
OVERCUR4
RST
PWRON4
TUSB2046BI-Q1
DP2
PWRON3
DM2
BUSPWR
OVRCUR2
OVERCUR3
PWRON2
GND
DP1
DM3
DM1
EED/GANG
OVRCUR1
DP3
PWRON
EEPROM
EECLK
Figure 15. Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
TUSB2046BIRHBRQ1
OBSOLETE
Package Type Package Pins Package
Drawing
Qty
VQFN
RHB
32
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
TUSB
2046BQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
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lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2016
OTHER QUALIFIED VERSIONS OF TUSB2046B-Q1 :
• Catalog: TUSB2046B
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TUSB2046BIRHBRQ1
Package Package Pins
Type Drawing
VQFN
RHB
32
SPQ
0
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB2046BIRHBRQ1
VQFN
RHB
32
0
338.1
338.1
20.6
Pack Materials-Page 2
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