TUSB2140BN

TUSB2140B Data Manual 4-Port Hub With an Embedded Function for the Universal Serial Bus SLLS313A March 1999 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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Copyright  1999, Texas Instruments Incorporated Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Embedded Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Device-Numbering Convention and Ordering Information . . . . . . . . . . . . . . . . . . . 1.5 Related Documents Referenced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1–1 1–1 1–2 1–2 1–2 1–3 1–5 1–5 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Serial Interface Engine (SIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 SIE Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Hub Command Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Frame Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Suspend/Resume Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Hub Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Port Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 Embedded Function Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13 Embedded Function Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14 Embedded Function FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15 Embedded Function I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 2–1 2–1 2–1 2–2 2–2 2–2 2–2 2–2 2–2 2–2 2–2 2–3 2–3 2–3 2–3 3 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Register Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Function Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Endpoint 0 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Endpoint 0 Transmit Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Endpoint 0 Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 Endpoint 0 Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 Endpoint 0 Transmit FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.9 Endpoint 0 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.10 Endpoint 0 Receive Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 3–2 3–4 3–4 3–5 3–5 3–6 3–6 3–7 3–8 3–9 3–9 3–9 iii 3.2.11 Endpoint 0 Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.12 Endpoint 0 Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.13 Endpoint 0 Receive FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.14 Endpoint 1 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.15 Endpoint 1 Transmit Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.16 Endpoint 1 Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.17 Endpoint 1 Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.18 Endpoint 1 Transmit FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.19 PID Low-Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.20 PID High-Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.21 VID Low-Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.22 VID High-Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 3–11 3–12 3–12 3–12 3–13 3–14 3–15 3–15 3–16 3–16 3–16 4 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Embedded Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Function Reset and USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Interrupt Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 Suspend and Remote Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Over-Current Detection and Power Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Clock Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 4–1 4–1 4–1 4–1 4–1 4–2 4–2 4–2 4–3 4–3 4–5 4–5 4–6 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings Over Operating Free-air Temperature Range . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Ranges of Operating Free-air Temperature and Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Timing Characteristics for USB Transceivers . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Timing Characteristics for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Timing Characteristics for Remote Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 5–1 5–1 5–2 5–3 5–3 5–5 5–7 USB Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Bus-Powered Hub, Ganged Port Power Management . . . . . . . . . . . . . . . . . . . . . . 6.3 Self-Powered Hub, Ganged Port Power Management . . . . . . . . . . . . . . . . . . . . . . 6.4 Self-Powered Hub, Individual Port Power Management . . . . . . . . . . . . . . . . . . . . . 6–1 6–2 6–4 6–5 6–6 6 Appendix A Firmware Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 Appendix B Firmware Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 Appendix C Flow Chart for the Firmware Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . C–1 Appendix D Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1 iv List of Illustrations Figure Title Page 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 Differential Driver Switching Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Data Signal Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Receiver Input Sensitivity vs Common Mode Input Range . . . . . . . . . . Single-Ended Receiver Input Signal Parameter Definitions . . . . . . . . . . . . . . . . . . . SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 5–4 5–4 5–5 5–5 5–5 5–6 5–6 5–6 5–7 5–7 5–7 6–1 6–2 6–3 6–4 6–5 6–6 6–7 USB Tiered Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical I2C Interface Connection to a Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . Resonator Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Tuning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TUSB2140B Bus-Powered Hub, Ganged Port Power Management Application . . TUSB2140B Self-Powered Hub, Ganged Port Power Management Application . . TUSB2140B Self-Powered Hub, Individual-Port Power Management Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 6–2 6–2 6–3 6–4 6–5 Flow Chart for TUSB2140B Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 0 Transmit Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 0 Receive Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 1 Transmit Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 A–3 A–5 A–6 A–1 A–2 A–3 A–4 6–6 C–1 Flow Chart for TUSB2140B Firmware (Sample Code) . . . . . . . . . . . . . . . . . . . . . . . . C–1 C–2 Endpoint 0 Receive Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2 C–3 Endpoint 0 Transmit Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3 v vi 1 Introduction The TUSB2140B is a compound USB device that provides an external 4-port hub and an embedded function that is virtually connected to an internal fifth hub port. The TUSB2140B is fully compatible with the USB, version 1.0, specification and the embedded function is fully compatible with the USB display-device class specification. The USB hub has a control endpoint and an interrupt endpoint. The embedded function also includes a control endpoint and an interrupt endpoint to support USB data transfers. The FIFOs and control registers associated with the endpoints are fully integrated within the device. An Inter IC(I2C), 2-wire serial bus provides an interface for any local micro-controller unit (MCU) to access the FIFOs and control registers. The TUSB2140B hub has the default power-on vendor ID (VID) of 0451H and a product ID (PID) of 2140H for the hub which will be displayed as General-Purpose USB Hub during enumeration. When custom vendor and product ID’s are desired for the external 4-port USB hub, the default VID/PID values can be replaced with custom values that are firmware based. When new VID/PID values are desired, they must be down-loaded through the I2C interface before the MCU connects the embedded function. The VID and PID for the embedded functions are always firmware based. The TUSB2140B hub supports power switching to the downstream ports for either individual or ganged power management modes. External power-management devices are required to switch power and to detect over-current conditions. See Application Information in Section 6. The TUSB2140B provides the required inputs and outputs needed for the power-management devices to control power switching and to monitor any over-current conditions. In the ganged mode, all PWRON signals switch simultaneously and all OVRCUR inputs should be tied together and driven by the same signal. The TUSB2140B requires a 48-MHz clock signal to sample data from the upstream port and to generate a synchronized 12-MHz USB clock signal. The hub supports the flexibility to use either a 48-MHz oscillator, a 48-MHz resonator, or a crystal tuned to 48-MHz. When an oscillator is used, the oscillator output must be connected to the XTAL1 terminal and the XTAL2 terminal should remain open. An oscillator with a TTL level output may be used if the output does not exceed 3.6-V maximum. When an oscillator is used, the TUSB2140B device will not be able to go into low-power suspend mode because the oscillator will always drive a 48-MHz clock signal into the TUSB2140B. A better implementation is to use a passive device such as a resonator or a crystal because when the TUSB2140B suspends, the resonator and crystal will also stop operation. For a resonator or crystal implementation, the XTAL1 terminal should be used as the input and the XTAL2 terminal should be used as the feedback path. See Figure 6–3 for resonator connection. Because the crystal is required to resonate at 48-MHz, a tuning circuit may be required such as shown in Figure 6–4. USB-compatible transceivers are provided for all upstream and downstream ports. All external downstream ports support both full-speed and low-speed connections by automatically setting the slew rate according to the speed of the device attached to the port. 1.1 Features The main features of the TUSB2140B hub and embedded function are listed in the following sections. 1.1.1 Hub • Universal Serial Bus (USB) Version 1.0 Compatible • Includes Serial Interface Engine (SIE) • All Four External Downstream Ports Support Full-Speed and Low-Speed Operations • Integrated USB Transceivers • Power Switching and Over-Current Conditions are Reported for Per Port or Ganged Modes • Supports default or custom Product ID (PID) and Vendor ID (VID) 1–1 1.1.2 Embedded Function • USB Display Class Compatible • Supports both Control and Interrupt Data Transfers • Integrated FIFOs and Control/Status Registers • Supports Interrupt Driven Operation to Minimize Local Micro-Controller Polling • Supports USB Remote Wake-Up • Supports Custom Product ID (PID) and Vendor ID (VID) 1.1.3 1.2 General Characteristics • Low-Power CMOS Technology • Generates a Clock Output With a Frequency of 12 MHz, 8 MHz, 6 MHz, or 4 MHz • Available in a 40-Pin Dip Package or a 44-Pin LQFP Package • Requires a 48-MHz Crystal, a 48–MHz Resonator, or 48-MHz Oscillator Input • Uses a 3.3 V and 5 V Power Supply Terminal Assignments N PACKAGE (TOP VIEW) WAKEUP CLKOUT GND CLKSEL0 CLKSEL1 OVRCUR5 OVRCUR2 PWRON1 OVRCUR1 DP0 DM0 GND DP1 DM1 BUSPWR GANGED DP2 DM2 VCC3V DP3 1–2 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 VCC5V SCL SDA IRQ PWRON5 FUNCSUSP PWRON2 VCC3V OVRCUR3 PWRON3 GND XTAL1 XTAL2 OSCOFF PWRON4 OVRCUR4 RESET DM4 DP4 DM3 NC CLKSEL1 CLKSEL0 GND CLKOUT WAKEUP VCC5V SCL SDA IRQ PWRON5 PGT PACKAGE (TOP VIEW) 44 43 42 41 40 39 38 37 36 35 34 OVRCUR5 OVRCUR2 PWRON1 OVRCUR1 DP0 DM0 GND DP1 DM1 BUSPWR NC 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 NC FUNCSUSP PWRON2 VCC3V OVRCUR3 PWRON3 GND XTAL1 XTAL2 OSCOFF PWRON4 NC GANGED DP2 DM2 VCC 3V DP3 DM3 DP4 DM4 RESET OVRCUR4 12 13 14 15 16 17 18 19 20 21 22 NC – No internal connection 1.3 Terminal Functions TERMINAL PGT NO. N NO. I/O DESCRIPTION BUSPWR 10 15 I Port power indicator. BUSPWR is an active low input that indicates whether the ports and the hub source power from the USB bus or are self-powered by the local power supply. When a microcontroller is connected to the TUSB2140B, the hub must be self-powered and it is mandatory for this pin to be connected to 3.3 V. This standard TTL input must not change dynamically during operation. CLKOUT 40 2 O Clock output. Depending on the configuration of CLKSEL0 and CLKSEL1, CLKOUT is a selected clock output of 12 MHz, 8 MHz, 6 MHz, or 4 MHz. DM1 – DM4 9, 14, 17, 19 14, 18, 21, 23 I/O Data minus USB differential data pairs. DM1 – DM4 support up to four negative-signal downstream USB ports. DP1 – DP4 8, 13, 16, 18 13, 17, 20, 22 I/O Data plus USB differential data pairs. DP1 – DP4 support up to four positive-signal downstream USB ports. DM0 6 11 I/O Data minus USB differential data. DM0 is used for the upstream USB port cable pair and negative signal. DP0 5 10 I/O Data plus USB differential data. DP0 is used for the upstream USB port cable pair and positive signal. NAME 1–3 1.3 Terminal Functions (continued) TERMINAL NAME PGT NO. N NO. I/O DESCRIPTION FUNCSUSP 32 35 O Function port suspend. FUNCSUSP is an active high output that indicates if the port that connects to the embedded function has been selectively suspended. See Suspend and Remote Wake-Up in section 4.3.6 for further information. GANGED 12 16 I Power switch/over-current detection mode select. GANGED selects between gang or per port switching for over-current detection of the downstream ports. This pin should be set dependent upon how the external power management devices are configured. This standard TTL input must not change dynamically during operation. GND 7, 27, 41 3, 12, 30 IRQ 35 37 O Interrupt. IRQ is an active low output to the micro-controller that indicates an interrupt condition has occurred. OSCOFF 24 27 I Oscillator off. OSCOFF disables the internal oscillator for quiescent current draw (ICCQ) testing. OSCOFF must be tied low for normal operation. OVRCUR1 – OVRCUR5 4, 2, 29, 21, 1 9, 7, 32, 25, 6 I Over-current indicators. OVRCUR1 – OVRCUR5 are active low, standard TTL inputs. One over-current indicator is available for each of the four downstream ports. These inputs are internally gated when port power switching is ganged. The unused terminals must be tied high. PWRON1 – PWRON5 3, 31, 28, 23, 34 8, 34, 31, 26, 36 O Power on/off control switches. PWRON1 – PWRON5 are active low, open-drain outputs. One power on/off control switch is used for each of the four downstream ports. All outputs are switched together when the port power switching is ganged. RESET 20 24 I Reset. RESET is a TTL input with hysteresis and must be asserted at power up for conformance to USB. RESET is an active low and must be asserted for at least 250 ns for all logic to be properly re-initialized. However, asserting the RESET for longer than 5 ms could cause the TUSB2140B to NAK too long and be ignored by the USB host. SCL 37 39 I Serial clock. SCL is the clock signal for the I2C serial interface and is 5-V tolerant. SDA 36 38 I/O Serial data. SDA is the bidirectional data signal for the I2C serial interface and is 5-V tolerant. SDA uses an open-drain output driver. VCC3V 15, 30 19, 33 VCC5V 38 40 WAKEUP 39 1 I Function port remote wake-up. WAKEUP is an active high input used by the micro-controller to initiate a remote wake-up from a suspended mode. WAKEUP is 5-V tolerant. See Suspend and Remote Wake-Up in section 4.3.6 for further information. XTAL1 26 29 I Crystal 1. XTAL1 is a 48-MHz clock input. Operation at 48-MHz is four times the USB full-speed bit rate of 12 Mbps. XTAL2 25 28 O Crystal 2. XTAL2 is a 48-MHz feedback output for crystals and resonators. Operation at 48-MHz is four times the USB full-speed bit rate of 12 Mbps. 42, 43 4, 5 I Clock select inputs. CLKSEL0 and CLKSEL1 determine the CLKOUT frequency (See Table 4–2). CLKSEL0, CLKSEL1 1–4 Ground. All terminals must be tied to ground for proper operation. 3.3-V supply voltage 5-V supply voltage 1.4 Device-Numbering Convention and Ordering Information T USB 2 1 40 B N Texas Instruments Universal Serial Bus Hub Device Hub Generation Type 1 = Embedded Function with I 2C 0 = Pure Hub Number of Downstream Ports 40 = 4 Downstream USB Ports Version Number Package Type PDIP 40 pins LQFP 44 pins 1.5 N PGT Related Documents Referenced • Universal Serial Bus Specification version 1.0 dated January 19, 1996. • Inter IC (I2C) Specification 1–5 1–6 2 Functional Description The functional block diagram for the TUSB2140B is shown in Section 2.1. The description for the function blocks follow Section 2.1. For additional information, including USB signaling specifications, packet protocol, and hub functionality, please refer to the Universal Serial Bus Specification version 1.0 dated January 19, 1996. 2.1 Functional Block Diagram DP0 10 DM0 11 USB Transceiver 27 29, 28 Hub Repeater State Machine and Signal Router 4, 5 2 Clock Generator Suspend / Resume Logic and Frame Timer SIE 24 OSCOFF XTAL1, XTAL2 CLKSEL0, CLKSEL1 CLKOUT RESET 1 35 SIE Interface Logic Port 1 Logic Hub / Device Command Decoder Port 4 Logic USB Transceiver 22 23 USB Transceiver 13 14 DP4 DM4 DP1 DM1 FIFOs I2C Slave Function Control Logic Control Status Registers 38 39 37 SDA SCL IRQ Embedded Function 16 Power Control Logic WAKEUP FUNCSUSP 15 9, 7, 32, 25, 6 8, 34, 31, 26, 36 GANGED BUSPWR OVRCUR1 – OVRCUR5 PWRON1 – PWRON5 NOTE A: Terminal numbers shown are for the N package 2.2 USB Transceiver The TUSB2140B provides integrated transceivers for all the USB ports. The transceivers include a differential output driver, a differential input receiver and two single ended inputs. The transceiver for each port connects to the appropriate DP and DM differential signal pair. 2.3 Clock Generator Utilizing the 48-MHz input signal, the clock generator logic generates the CLKOUT output signal in addition to the various internal clock signals. The TUSB2140B internal clocks consist of the 48-MHz clock, a 12-MHz clock, and a USB clock. The USB clock also has a frequency of 12-MHz. The USB clock is the same as the 12-MHz clock when the TUSB2140B is transmitting data and is derived from the data when the TUSB2140B is receiving data. 2–1 2.4 Serial Interface Engine (SIE) The serial interface engine logic manages the USB packet protocol requirements for the packets being received and transmitted by the TUSB2140B. For packets being received, the SIE decodes the packet identifier field (PID) to determine the type of packet being received and ensures the PID is valid. For token packets and data packets being received, the SIE calculates the packet CRC and compares the value to the CRC contained in the packet to verify that the packet was not corrupted during transmission. For token packets and data packets being transmitted, the SIE generates the CRC that is transmitted with the packet. For packets being transmitted, the SIE also generates the synchronization field (SYNC) which is the eight bit field at the beginning of each packet. In addition, the SIE generates the correct PID for all packets being transmitted. Another major function of the SIE is the overall serial-to-parallel conversion of the data packets being received and the parallel-to-serial conversion of the data packets being transmitted. 2.5 SIE Interface Logic The SIE interface logic provides the control logic that interfaces the SIE to the hub control logic and the embedded function control logic. One of the major functions of the SIE interface logic is to decode the function address from the SIE to determine if either the hub or embedded function is being addressed. In addition, the endpoint address field is decoded to determine which particular endpoint of the hub or embedded function is being addressed. The SIE interface logic also managers the multiplexing of the byte-wide transmit data signals and other control signals from the hub control logic and embedded function control logic. 2.6 Hub Command Decoder The hub command decoder logic manages the overall control of the hub including the decode and execution of host initiated control commands, as well as the status change endpoint. During USB interrupt transfers, the USB host uses the status change endpoint to acquire hub status and port status change information. 2.7 Frame Timer The frame timer logic generates the end of frame (EOF) signal which is used mainly to ensure that all downstream traffic is completed during each frame period. In addition, since the frame timer counts 1.0 ms periods, the EOF signal is used by other logic that needs to time events based on multiples of 1.0 ms periods. The hub frame timer logic is locked to the host frame timer logic by the host generated Start of Frame (SOF) packets. 2.8 Suspend/Resume Logic The suspend/resume logic is used to detect the suspend/resume states and to generate the signals used to control the overall device during the suspend/resume states. See Suspend and Remote Wake-Up in section 4.3.6 for further information. 2.9 Hub Repeater The hub repeater logic manages the connectivity of the root port and the downstream ports on a per-packet basis. The data flow of the USB packets through the TUSB2140B from the root port to the downstream ports and vice-a-versa is totally asynchronous. 2.10 Port Logic The port logic manages the overall state of a particular downstream port. Each downstream port has unique port logic which controls the connect/disconnect, enable/disable, suspend/resume and reset states of the port. 2.11 Power Control Logic The power control logic generates the PWRON1 thru PWRON5 output signals based on the GANGED, BUSPWR, and OVRCUR input signals. 2–2 2.12 Embedded Function Control Logic The Function control logic (FCL) manages communication between the local microcontroller Unit (MCU) and the Serial interface engine (SIE). The local MCU directs the operation of the FCL through the control and status registers. One of the major functions performed by the FCL is to move data to and from the internal FIFOs during the control and interrupt endpoint transfer operations. 2.13 Embedded Function Control/Status Registers The control and status registers allow the local MCU to control and monitor transfer operations done by the TUSB2140B. A separate set of registers is used to control the transmit and receive operations for the control endpoint which is endpoint 0. In addition, a separate set of registers is provided for the interrupt endpoint transmit operations, which is endpoint 1. Also, an interrupt and interrupt mask register is provided to control the conditions that generate the IRQ output signal. 2.14 Embedded Function FIFOs The TUSB2140B internal FIFOs provide a buffer between the SIE and the local MCU. There are three 8-byte by 8-bit FIFOs provided. There is a separate transmit and receive FIFO provided for the control endpoint, which is endpoint 0. In addition, there is a transmit FIFO provided for the interrupt endpoint, which is endpoint 1. 2.15 Embedded Function I2C Interface The I2C Interface logic provides a two-wire serial interface that is used by a local MCU or device needing serial access to the TUSB2140B control/status registers and FIFOs. The interface allows single byte read and writes to the registers and multiple byte read and writes to the FIFOs. Note that the transmit FIFOs are write only and the receive FIFOs are read only from the local MCU side. 2–3 2–4 3 Internal Registers The TUSB2140B provides a set of control and status registers to be used by the local microcontroller unit to control the overall operation of the embedded function. The control and status registers allow the local MCU to control and monitor USB transfers to both the control endpoint and the interrupt endpoint of the embedded function. There is a separate set of registers provided for the control endpoint transmit and receive operations. In addition, there is a separate set of registers provided for the transmit operations of the interrupt endpoint. Also, an interrupt and interrupt mask register is provided to control the conditions that generate the IRQ output signal. 3–1 3–2 3.1 Address Map ADDRESS MSB LSB 7 6 5 00h 01h 02h 4 3 2 1 NAME 0 FSUSP FRST EP1TX EP0RX EP0TX Interrupt Register FSUSP FRST EP1TX EP0RX EP0TX Interrupt Mask Register FEN FA6 FA5 FA4 FA3 FA2 FA1 FA0 Function Address Register D7 D6 D5 D4 D3 D2 D1 D0 EP0 TX FIFO BCNT3 BCNT2 BCNT1 BCNT0 EP0 TX Byte Count Register TXFEN TXEN EP0 TX Control Register 03h 04h 05h 06h TXCLR 07h TXSEQ TXSTL STSGE 08h 09h D7 D6 D5 D4 0Ah 0Bh RXCLR 0Ch RXSEQ STALL NACK ERROR ACK EP0 TX Status Register EMPT FULL UNDR OVRR EP0 TX FIFO Flags Register D3 D2 D1 D0 EP0 RX FIFO BCNT3 BCNT2 BCNT1 BCNT0 EP0 RX Byte Count Register RXFEN RXEN EP0 RX Control Register RXSTL SETUP RXFSW STSGE 0Dh STALL NACK ERROR ACK EP0 RX Status Register EMPT FULL UNDR OVRR EP0 RX FIFO Flags Register D3 D2 D1 D0 EP1 TX FIFO BCNT3 BCNT2 BCNT1 BCNT0 EP1 TX Byte Count Register TXFEN TXEN EP1 TX Control Register 0Eh 0Fh 10h D7 D6 12h TXCLR TXSOW 13h TXSEQ D5 D4 11h TXSTL 14h STALL NACK ERROR ACK EP1 TX Status Register EMPT FULL UNDR OVRR EP1 TX FIFO Flags Register 15h PID(7) PID(6) PID(5) PID(4) PID(3) PID(2) PID(1) PID(0) Hub Product ID, Low Byte Register 16h PID(15) PID(14) PID(13) PID(12) PID(11) PID(10) PID(9) PID(8) Hub Product ID, High Byte Register 17h VID(7) VID(6) VID(5) VID(4) VID(3) VID(2) VID(1) VID(0) Hub Vendor ID, Low Byte Register 18h VID(15) VID(14) VID(13) VID(12) VID(11) VID(10) VID(9) VID(8) Hub Vendor ID, High Byte Register 19h 3.1 Address Map (continued) ADDRESS 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh MSB 7 LSB 6 5 4 3 2 1 0 NAME 3–3 3.2 Register Functional Description The following sections contain the functional descriptions for each register and the individual register bits. Note that firmware should write a 0 to reserved bits and ignore any value read from reserved bits. 3.2.1 Interrupt Register The interrupt register bits are used to indicate when an interrupt condition is pending. If one or more of the interrupt bits are set, the TUSB2140B interrupt output signal (IRQ) will be asserted until the interrupt condition(s) is cleared. One or more of the interrupt bits can be masked by setting the corresponding bit in the interrupt mask register. If the interrupt mask bit is set, the corresponding interrupt bit will still be set when an interrupt condition occurs. However, the IRQ output signal will not be asserted. This feature is provided for systems that detect pending interrupt conditions with a polling scheme rather than by monitoring the IRQ output signal. 7 0 – – BIT MNEMONIC 7:5 – 3–4 – FSUSP FRST NAME EP1TX EP0RX EP0TX DESCRIPTION Reserved Reserved for future use. 4 FSUSP Function suspend The function suspend interrupt bit is set in response to the hub suspend logic detecting a global suspend condition or a selective suspend condition for the embedded function. To enable the TUSB2140B to enter a low–power suspend state which includes disabling the clocks, this bit must be cleared by the local MCU. This bit is cleared by writing a 1 to this register. This bit is read/write and is cleared by power-on reset. 3 FRST Function reset The function reset interrupt bit is set in response to the host initiating a port reset on the function port. To enable the function reset, this bit must be cleared by the local MCU. When a function reset occurs, all of the Function Interface logic within the TUSB2140B will be reset except the endpoint 0 receive enable bit (RXEN), the endpoint 0 transmit enable bit (TXEN), the function reset interrupt bit (FRST) and all of the interrupt mask bits. This bit is cleared by writing a 1 to this register. This bit is read/write and is cleared by power-on reset. 2 EP1TX Endpoint 1 transmit interrupt The endpoint 1 transmit interrupt bit is set in response to the endpoint 1 transmit acknowledge status bit (ACK), the endpoint 1 transmit FIFO over-run flag bit (OVRR), or the endpoint 1 transmit FIFO under-run flag bit (UNDR) being set. This bit is cleared by clearing the corresponding status or FIFO flag bit that caused the interrupt. This bit is read-only and is cleared by power-on reset. 1 EP0RX Endpoint 0 receive interrupt The endpoint 0 receive interrupt bit is set in response to the endpoint 0 receive acknowledge status bit (ACK), the endpoint 0 receive FIFO over-run flag bit (OVRR), or the endpoint 0 receive FIFO under-run flag bit (UNDR) being set. This bit is cleared by clearing the corresponding status or FIFO flag bit that caused the interrupt. This bit is read-only and is cleared by power-on reset. 0 EP0TX Endpoint 0 transmit interrupt The endpoint 0 transmit interrupt bit is set in response to the endpoint 0 transmit acknowledge status bit (ACK), the endpoint 0 transmit FIFO over-run flag bit (OVRR), or the endpoint 0 transmit FIFO under-run flag bit (UNDR) being set. This bit is cleared by clearing the corresponding status or FIFO flag bit that caused the interrupt. This bit is read-only and is cleared by power-on reset. 3.2.2 Interrupt Mask Register The interrupt mask register bits are used to mask the corresponding interrupt bits. 7 0 – – – BIT MNEMONIC 7:4 – 4 FSUSP FSUSP FRST NAME EP1TX EP0RX EP0TX DESCRIPTION Reserved Reserved for future use Function suspend The function suspend interrupt mask bit is set to enable the function suspend interrupt bit. This bit is read/write and is cleared by power–on reset. interrupt mask 3 FRST Function reset interrupt mask The function reset interrupt mask bit is set to enable the function reset interrupt bit. This bit is read/write and is cleared by power-on reset. 2 EP1TX Endpoint 1 transmit interrupt mask The endpoint 1 transmit interrupt mask bit is set to enable the endpoint 1 transmit interrupt bit. This bit is read/write and is cleared by power-on reset. 1 EP0RX Endpoint 0 receive interrupt mask The endpoint 0 receive interrupt mask bit is set to enable the endpoint 0 receive interrupt bit. This bit is read/write and is cleared by power-on reset. 0 EP0TX Endpoint 0 transmit interrupt mask The endpoint 0 transmit interrupt mask bit is set to enable the endpoint 0 transmit interrupt bit. This bit is read/write and is cleared by power-on reset. 3.2.3 Function Address Register The function address register contains the current setting of the USB device address assigned to the function. During enumeration of the function, the function address is loaded into this register automatically by the TUSB2140B Function Control Logic when a Set Address request is received from the USB host. This register is read only and is used only for diagnostic purposes. 7 0 FEN BIT 7 6:0 FA6 MNEMONIC FA5 FA4 NAME FA3 FA2 FA1 FA0 DESCRIPTION FEN Function enabled The function enabled bit is set when the embedded function port has been enabled by the host with a set port feature request. This bit is read-only and is cleared by power-on reset. FA(6:0) Function address The function address register value is set to the current device address assigned to the function. These bits are read/write-able and are cleared by power-on reset. The function address is updated when the MCU receives a set-address control transfer for the embedded function from the host. The MCU will then update the function address from the micro-controller firmware through the I2C interface. 3–5 3.2.4 Endpoint 0 Transmit FIFO 7 0 D6 D7 BIT MNEMONIC 7:0 D(7:0) 3.2.5 D5 D4 D3 D2 D1 NAME DESCRIPTION Transmit FIFO data Endpoint 0 transmit FIFO data is written to the transmit FIFO on a byte-to-byte basis. These bits are write-only. Endpoint 0 Transmit Byte Count Register 7 0 – – BIT MNEMONIC 7:4 – 3:0 3–6 D0 BCNT(3:0) – – NAME BCNT3 BCNT2 BCNT1 BCNT0 DESCRIPTION Reserved Reserved for future use. Transmit byte count The transmit byte count register should be loaded with the number of bytes to be transmitted. The byte count should be the number of bytes in the data packet that was loaded into the transmit FIFO. When the local MCU writes to the byte count register, the EP0 transmit FIFO enable bit (TXFEN) will automatically be set. Also, the byte count register does not decrement as data is transmitted. These bits are read/write and are cleared by power-on reset. 3.2.6 Endpoint 0 Transmit Control Register The transmit control register is used to store bits which control various functions and operating modes of the function interface logic within the TUSB2140B. 7 0 – TXCLR BIT MNEMONIC – – TXSTL – TXFEN TXEN NAME DESCRIPTION Transmit clear The transmit clear bit is set to reset the transmit FIFO pointers and flags. This bit should be set in response to a transmit FIFO over–run or under-run condition. After the FIFO pointers are reset, this bit will be automatically cleared. In addition, the FIFO empty flag will be set and the other FIFO flags will be cleared upon completion of the FIFO reset. This bit is read/write and is cleared by power-on reset. – Reserved Reserved for future use – Reserved Reserved for future use 4 – Reserved Reserved for future use 3 TXSTL Transmit stall The transmit stall bit is set to enable a STALL handshake to be returned in response to the next valid In Transaction. This bit is automatically cleared if a new Setup Stage Transaction is successfully received. This bit is read/write and is cleared by power-on reset. 7 TXCLR 6 5 2 – Reserved Reserved for future use 1 TXFEN Transmit FIFO enable The transmit FIFO enable bit is set to enable the transmission of data in the transmit FIFO when the next valid in transaction occurs. This bit is automatically set when the local MCU writes to the EP0 transmit byte count register and is automatically cleared when the EP0 transmit acknowledge status bit (ACK) is set. This bit is also automatically cleared if a new setup stage transaction is successfully received or the EP0 transmit clear bit (TXCLR) is set. If the transmit enable bit is not set, the device returns a NACK handshake. If the transmit stall control bit (TXSTL) is set, a STALL handshake is returned instead of a NACK handshake. This bit is read/write and is cleared by power-on reset. 0 TXEN Transmit enable The transmit enable bit is set to enable the transmit endpoint. For endpoint 0, the control endpoint, both a receive and transmit endpoint are required. Therefore, the transmit enable and receive enable bits must both be set before the device will be enumerated. If either of these bits is not set, the function port will remain in the disconnected state. This bit is read/write and is cleared by power-on reset. 3–7 3.2.7 Endpoint 0 Transmit Status Register The transmit status register is used to store bits which report status information about the operating conditions of the function control logic within the TUSB2140B. 7 0 – TXSEQ BIT 3–8 – MNEMONIC STSGE STALL NAME NACK ERROR ACK DESCRIPTION 7 TXSEQ Transmit sequence The transmit sequence bit value determines the data packet PID to be used for the next data packet to be transmitted for the next In data stage transaction. This bit is automatically set at the end of a successful setup stage transaction and is automatically toggled at the end of each successful in data stage transaction. If this bit is a 0, a DATA0 PID is sent in the data packet. If this bit is a 1, a DATA1 PID is sent in the data packet. This bit is read only and is cleared by power-on reset. 6 – Reserved Reserved for future use 5 – Reserved Reserved for future use 4 STSGE In status stage The in status stage bit is set when the function control logic detects the status stage transaction of a control transfer. This bit will be automatically cleared at the beginning of the next setup stage transaction. This bit is read-only and is cleared by power-on reset. 3 STALL Stall The stall status bit is set at the end of an in transaction if a STALL handshake packet is returned to the host instead of a data packet. The function control logic will automatically return a STALL handshake to the host if a valid in transaction is received and the transmit stall control bit is set. This stall status bit will be automatically updated at the end of the next valid in transaction. This bit is read-only and is cleared by power-on reset. 2 NACK No acknowledge The no acknowledge status bit is set at the end of an In Transaction if a NACK handshake packet is returned to the host instead of a data packet. The function control logic will automatically return a NACK handshake to the host if a valid In Transaction is received and there is not a data packet in the transmit FIFO ready to be transmitted. This bit will be automatically updated at the end of the next valid in transaction. This bit is read-only and is cleared by power-on reset. 1 ERROR Error The error status bit is set at the end of an in transaction if a timeout, bit-stuff, CRC, force transmit or other errors occur. This bit will be automatically updated at the end of the next valid in transaction. This bit is read-only and is cleared by power-on reset. 0 ACK Acknowledge The acknowledge status bit is set at the end of an in transaction if the data packet in the transmit FIFO was sent successfully and an acknowledge handshake was received from the host. When this bit is set, the endpoint 0 transmit interrupt bit is also set. The acknowledge status bit should be cleared by the local MCU in order to clear the interrupt condition. This bit will be automatically cleared at the beginning of the next setup stage transaction. This bit is read/write and is cleared by power-on reset. 3.2.8 Endpoint 0 Transmit FIFO Flags Register The transmit FIFO flags register is used to store bits which report status information about the transmit FIFO operating condition. 7 0 – – BIT MNEMONIC 7:4 – – – EMPT NAME FULL UNDR OVRR DESCRIPTION Reserved Reserved for future use 3 EMPT Transmit FIFO empty The transmit FIFO empty flag is set when the transmit FIFO is empty. This bit is cleared when the FIFO is no longer empty. This bit is read-only and is set by power-on reset. 2 FULL Transmit FIFO full The transmit FIFO full flag is set when the transmit FIFO is full. This bit is cleared when the FIFO is no longer full. This bit is read-only and is cleared by power-on reset. 1 UNDR Transmit FIFO under-run The transmit FIFO under-run flag is set when the transmit FIFO is empty and the function control logic attempts to read another byte from the FIFO. This will happen if the number of bytes actually written to the transmit FIFO is less than the value loaded into the transmit byte count register. When this bit is set, the endpoint 0 transmit interrupt bit is also set. To clear the FIFO under-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. 0 OVRR Transmit FIFO over-run The transmit FIFO over-run flag is set when the transmit FIFO is full and the local MCU attempts to write another byte to the FIFO. When this bit is set, the endpoint 0 transmit interrupt bit is also set. To clear the FIFO over-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. 3.2.9 Endpoint 0 Receive FIFO 7 0 D6 D7 BIT MNEMONIC 7:0 D(7:0) 3.2.10 D5 D4 D3 D2 D1 NAME DESCRIPTION Receive FIFO data Endpoint 0 receive FIFO data is read from the receive FIFO on a byte-to-byte basis. These bits are read-only. Endpoint 0 Receive Byte Count Register 7 0 – – BIT MNEMONIC 7:4 – 3:0 D0 BCNT(3:0) – – NAME BCNT3 BCNT2 BCNT1 BCNT0 DESCRIPTION Reserved Reserved for future use Receive byte count The receive byte count register is loaded with the number of bytes in the data packet received into the endpoint 0 receive FIFO for a valid setup stage transaction or OUT Transaction. The receive FIFO byte count register does not decrement as data is read from the FIFO. These bits are read-only and are cleared by power-on reset. 3–9 3.2.11 Endpoint 0 Receive Control Register The receive control register is used to store bits which control various functions and operating modes of the function interface logic within the TUSB2140B device. 7 0 – RXCLR BIT MNEMONIC – – RXSTL – RXFEN RXEN NAME DESCRIPTION Receive clear The receive clear bit is set to reset the receive FIFO pointers and flags. This bit should be set in response to a receive FIFO over–run or under-run condition. After the FIFO pointers are reset, this bit will be automatically cleared. In addition, the FIFO empty flag will be set and the other FIFO flags will be cleared upon completion of the FIFO reset. This bit is read/write and is cleared by power-on reset. – Reserved Reserved for future use – Reserved Reserved for future use 4 – Reserved Reserved for future use 3 RXSTL Receive stall The receive stall bit is set to enable a STALL handshake to be returned in response to the next valid out transaction. This bit does not effect a setup stage transaction. The setup stage transaction must always be accepted, unless there is a data packet error or a time out error, so that a clear feature endpoint Stall request can be received from the host. This bit is automatically cleared if a new setup stage transaction is successfully received. This bit is read/write and is cleared by power-on reset. 7 RXCLR 6 5 2 – Reserved Reserved for future use 1 RXFEN Receive FIFO enable The receive FIFO enable bit is set to enable the reception of data into the receive FIFO when the next valid out transaction occurs. This bit is automatically cleared when the local EP0 receive acknowledge status bit (ACK) is set. This bit is also automatically cleared if a new setup stage transaction is successfully received or the EP0 receive clear bit (RXCLR) is set. If the receive enable bit is not set, the device returns a NACK handshake. If the receive stall control bit (RXSTL) is set, a STALL handshake is returned instead of a NACK handshake. This bit does not effect a setup stage transaction. The setup stage transaction must always be accepted, unless there is a data packet error or a time-out error. This bit is read/write and is cleared by power-on reset. 0 RXEN Receive enable The receive enable bit is set to enable the receive endpoint. For endpoint 0, the control endpoint, both a receive and transmit endpoint are required. Therefore, the transmit enable and receive enable bits must both be set before the device will be enumerated. If either of these bits is not set, the function port will remain in the disconnected state. This bit is read/write and is cleared by power-on reset. 3–10 3.2.12 Endpoint 0 Receive Status Register The receive status register is used to store bits which report status information about the operating conditions of the function control logic within the TUSB2140B device. 7 0 RXSEQ BIT MNEMONIC SETUP RXFSW NAME STSGE STALL NACK ERROR ACK DESCRIPTION 7 RXSEQ Receive sequence The receive sequence bit is toggled by the function control logic at the end of an out data stage transaction if a valid data packet is received and the data packet PID matches the expected PID. The receive sequence bit is initialized to a 1 at the end of a successful setup stage transaction. This bit is read-only and is cleared by power-on reset. 6 SETUP Setup stage transaction The setup stage transaction bit is set at the end of a successful Setup Stage Transaction to indicate that the data packet in the receive FIFO is a setup stage transaction data packet. This bit is cleared by writing a 1 to this register. To read the receive FIFO, the local MCU must first clear the setup stage transaction bit (SETUP). This bit is read/write and is cleared by power-on reset. 5 RXFSW Receive FIFO setup stage transaction data packet write The receive FIFO setup stage transaction data packet write bit is set at the beginning of a setup stage transaction and is cleared at the end of setup stage transaction. This bit indicates that the receive FIFO is being over-written with data from the setup stage transaction data packet. This bit, in conjunction with the setup stage bit (SETUP), is used to indicate when a new setup stage transaction has occurred and data in the receive FIFO from a previous out data stage transaction may have been over-written. This bit is read-only and is cleared by power-on reset. 4 STSGE In status stage The in status stage bit is set when the function control logic detects the status stage transaction of a control transfer. This bit will be automatically cleared at the beginning of the next setup stage transaction. This bit is read-only and is cleared by power-on reset. 3 STALL Stall The stall status bit is set at the end of an out transaction if a STALL handshake packet is returned to the host. The function control logic will automatically return a STALL handshake to the host if a valid out transaction is received and the receive stall control bit is set. This stall status bit will automatically be updated at the end of the next valid out transaction. This bit is read-only and is cleared by power-on reset. 2 NACK No acknowledge The no acknowledge status bit is set at the end of an out transaction if a NACK handshake packet is returned to the host. The Function Control Logic will automatically return a NACK handshake to the host if a valid out transaction is received and the receive FIFO enable bit has not been set. This bit will be automatically updated at the end of the next valid out transaction. This bit is read-only and is cleared by power-on reset. 1 ERROR Error The error status bit is set at the end of an out transaction if a timeout, bit-stuff, CRC, force receive or other errors occur. This bit will be automatically updated at the end of the next valid out transaction. This bit is read-only and is cleared by power-on reset. 0 ACK Acknowledge The acknowledge status bit is set at the end of an out transaction if the data packet was received successfully and an acknowledge handshake was sent to the host. When this bit is set, the endpoint 0 receive interrupt bit is also set. The acknowledge status bit should be cleared by the local MCU in order to clear the interrupt condition. This bit will be automatically cleared at the beginning of the next setup stage transaction. This bit is read/write and is cleared by power-on reset. 3–11 3.2.13 Endpoint 0 Receive FIFO Flags Register The receive FIFO flags register is used to store bits which report status information about the receive FIFO operating condition. 7 0 – – BIT MNEMONIC 7:4 – – – EMPT NAME FULL UNDR OVRR DESCRIPTION Reserved Reserved for future use. 3 EMPT Receive FIFO empty The receive FIFO empty flag is set when the receive FIFO is empty. This bit is cleared when the FIFO is no longer empty. This bit is read-only and is set by power-on reset. 2 FULL Receive FIFO full The receive FIFO full flag is set when the receive FIFO is full. This bit is cleared when the FIFO is no longer full. This bit is read-only and is cleared by power-on reset. 1 UNDR Receive FIFO under-run The receive FIFO under-run flag is set when the receive FIFO is empty and when the local MCU attempts to read a byte from the FIFO. When this bit is set, the endpoint 0 receive interrupt bit is also set. To clear the FIFO under-run condition, the receive FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 receive interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. 0 OVRR Receive FIFO over-run The receive FIFO over-run flag is set when the receive FIFO is full and the function control Logic attempts to write another byte to the FIFO. When this bit is set, the endpoint 0 receive interrupt bit is also set. To clear the FIFO over-run condition, the receive FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 receive interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. 3.2.14 Endpoint 1 Transmit FIFO 7 0 D6 D7 BIT MNEMONIC 7:0 D(7:0) 3.2.15 D5 D4 D3 D2 D1 NAME DESCRIPTION Transmit FIFO data Endpoint 1 transmit FIFO data is written to the transmit FIFO on a byte-to-byte basis. These bits are write-only. Endpoint 1 Transmit Byte Count Register 7 0 – – BIT 7:4 3:0 3–12 D0 MNEMONIC – BCNT(3:0) – – BCNT3 NAME BCNT2 BCNT1 BCNT0 DESCRIPTION Reserved Reserved for future use. Transmit byte count The transmit byte count register should be loaded with the number of bytes to be transmitted. The byte count should be the number of bytes in the data packet that was loaded into the transmit FIFO. When the local MCU writes to the byte count register, the EP1 transmit FIFO enable bit (TXFEN) will automatically be set. Also, the byte count register does not decrement as data is transmitted. These bits are read/write and are cleared by power-on reset. 3.2.16 Endpoint 1 Transmit Control Register The transmit control register is used to store bits which control various functions and operating modes of the function interface logic within the TUSB2140B device. 7 0 TXSOW TXCLR BIT MNEMONIC – – TXSTL NAME – TXFEN TXEN DESCRIPTION 7 TXCLR Transmit clear The transmit clear bit is set to reset the transmit FIFO pointers and flags. This bit should be set in response to a transmit FIFO over–run or under-run condition. After the FIFO pointers are reset, this bit will be automatically cleared. In addition, the FIFO empty flag will be set and the other FIFO flags will be cleared upon completion of the FIFO reset. This bit is read/write and is cleared by power-on reset. 6 TXSOW Transmit sequence bit over-write The transmit sequence bit over-write bit is set to enable the local MCU to write to the transmit sequence bit (TXSEQ). See the EP1TX Transmit Status Register. This bit is read/write and is cleared by power-on reset. 5 – Reserved Reserved for future use 4 – Reserved Reserved for future use 3 TXSTL Transmit stall The transmit stall bit is set to enable a STALL handshake to be returned in response to the next valid in transaction. This bit is read/write and is cleared by power-on reset. 2 – Reserved Reserved for future use 1 TXFEN Transmit FIFO enable The transmit FIFO enable bit is set to enable the transmission of data in the transmit FIFO when the next valid in transaction occurs. This bit is automatically set when the local MCU writes to the EP1 transmit byte count register and is automatically cleared when the EP1 transmit acknowledge status bit (ACK) is set. This bit is also automatically cleared if the EP1 transmit clear bit (TXCLR) is set. If the transmit enable bit is not set, the device returns a NACK handshake. If the transmit stall control bit (TXSTL) is set, a STALL handshake is returned instead of a NACK handshake. This bit is read/write and is cleared by power-on reset. 0 TXEN Transmit enable The transmit enable bit is set to enable the transmit endpoint. This bit is read/write and is cleared by power-on reset. 3–13 3.2.17 Endpoint 1 Transmit Status Register The transmit status register is used to store bits which report status information about the operating conditions of the Function Control Logic within the TUSB2140B device. 7 0 – TXSEQ BIT – MNEMONIC 7 TXSEQ 6 – STALL NAME NACK ERROR ACK DESCRIPTION Transmit sequence The transmit sequence bit value determines the data packet PID to be used for the next data packet to be transmitted during the next in data stage transaction. This bit is automatically toggled at the end of a successful In Transaction. If this bit is a 0, a DATA0 PID is sent in the data packet. If this bit is a 1, a DATA1 PID is sent in the data packet. The local MCU can write to this bit if the transmit sequence bit over-write (TXSOW) is set. This bit is read/write and is cleared by power-on reset. – Reserved Reserved for future use 5 – Reserved Reserved for future use 4 – Reserved Reserved for future use 3 STALL Stall The stall status bit is set at the end of an in transaction if a STALL handshake packet is returned to the host instead of a data packet. The function control logic will automatically return a STALL handshake to the host if a valid in transaction is received and the transmit stall control bit is set. This stall status bit will be automatically updated at the end of the next valid in transaction. This bit is read-only and is cleared by power-on reset. 2 NACK No acknowledge The no acknowledge status bit is set at the end of an In Transaction if a NACK handshake packet is returned to the host instead of a data packet. The function control logic will automatically return a NACK handshake to the host if a valid In Transaction is received and there is not a data packet in the transmit FIFO ready to be transmitted. This bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. 1 ERROR Error The error status bit is set at the end of an in transaction if a timeout, bit-stuff, CRC, force transmit or other errors occur. This bit will be automatically updated at the end of the next valid in transaction. This bit is read-only and is cleared by power-on reset. 0 ACK Acknowledge The acknowledge status bit is set at the end of an in transaction if the data packet in the transmit FIFO was sent successfully and an acknowledge handshake was received from the host. When this bit is set, the endpoint 1 transmit interrupt bit is also set. The acknowledge status bit should be cleared by the local MCU in order to clear the interrupt condition. This bit is read/write and is cleared by power-on reset. 3–14 3.2.18 Endpoint 1 Transmit FIFO Flags Register The transmit FIFO flags register is used to store bits which report status information about the transmit FIFO operating condition. 7 0 – – BIT MNEMONIC 7:4 – – – EMPT NAME FULL UNDR OVRR DESCRIPTION Reserved Reserved for future use 3 EMPT Transmit FIFO empty The transmit FIFO empty flag is set when the transmit FIFO is empty. This bit is cleared when the FIFO is no longer empty. This bit is read-only and is set by power-on reset. 2 FULL Transmit FIFO full The transmit FIFO full flag is set when the transmit FIFO is full. This bit is cleared when the FIFO is no longer full. This bit is read-only and is cleared by power-on reset. 1 UNDR Transmit FIFO under-run The transmit FIFO under-run flag is set when the transmit FIFO is empty and the function control logic attempts to read another byte from the FIFO. This will happen if the number of bytes actually written to the transmit FIFO is less than the value loaded into the transmit byte count register. When this bit is set, the endpoint 1 transmit interrupt bit is also set. To clear the FIFO under-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 1 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. 0 OVRR Transmit FIFO over-run The transmit FIFO over-run flag is set when the transmit FIFO is full and the local MCU attempts to write another byte to the FIFO. When this bit is set, the endpoint 1 transmit interrupt bit is also set. To clear the FIFO over-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 1 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. 3.2.19 PID Low-Byte Register The PID low-byte register is used to store the lower eight bits of the PID information for the USB hub. This register has the power-up default value of 40h, but can be replaced by any custom value downloaded through the I2C interface from the firmware that resides on the local microcontroller. 7 0 PID(7) PID(6) PID(5) PID(4) PID(3) PID(2) PID(1) PID(0) 3–15 3.2.20 PID High-Byte Register The PID high-byte register is used to store the higher eight bits of the PID information for the USB hub. This register has the power-up default value of 21h, but can be replaced by any custom value downloaded through the I2C interface from the firmware that resides on the local microcontroller. 7 0 PID(15) 3.2.21 PID(14) PID(13) PID(12) PID(11) PID(10) PID(9) PID(8) VID Low-Byte Register The VID low-byte register is used to store the lower eight bits of the VID information for the USB hub. This register has the power-up default value of 51h, but can be replaced by any custom value downloaded through the I2C interface from the firmware that resides on the local microcontroller. 7 0 VID(7) 3.2.22 VID(6) VID(5) VID(4) VID(3) VID(2) VID(1) VID(0) VID High-Byte Register The VID high-byte register is used to store the higher eight bits of the VID information for the USB hub. This register has the power-up default value of 04h, but can be replaced by any custom value downloaded through the I2C interface from the firmware that resides on the local microcontroller. 7 0 VID(15) VID(14) VID(13) VID(12) VID(11) VID(10) VID(9) VID(8) NOTE: The default VID = 0451h and PID = 2140h will be displayed as General Purpose USB Hub during enumeration. Section 4.3 explains the order of operation for downloading the custom IDs in more detail. 3–16 4 Device Operation The operation of the TUSB2140B is explained in the following sections. For additional information on USB, please refer to the Universal Serial Bus Specification version 1.0 dated January 19, 1996. Chapter 11 of the specification contains very detailed information on the hub operations. 4.1 Device Initialization When a power-on reset is applied to the TUSB2140B, the device is automatically configured as a stand-alone hub with five downstream ports. In addition, all of the registers associated with the embedded function are initialized as defined in Section 3.2, Register Functional Descriptions. Both the hub and the embedded function power-up with a default function address of zero, and the embedded function is disconnected. To connect the embedded function to the downstream port 5 of the hub, the MCU must set the receive enable bit (RXEN) to 1 and the transmit enable bit (TXEN) to a 1. 4.2 Hub The hub within the TUSB2140B supports a maximum of 4 external downstream ports and the embedded function. The embedded function must be connected to downstream port 5 before the hub begins functioning. The hub is a separate logical device and contains a separate control endpoint and interrupt endpoint from the embedded function. The hub automatically handles all USB standard device commands addressed to the hub function address. Because the hub is a state machine approach instead of being based on a microcontroller, the only software required to support the hub function is the generic USB driver, on the host side, that supports the hub-class. 4.3 Embedded Function The embedded function within the TUSB2140B supports USB control and interrupt data transfers by providing FIFOs, control/status registers, and the USB bus interface to be used by a local MCU. The embedded function is a separate logical device, and therefore, the embedded function requires a unique function address. To enumerate the embedded function, the TUSB2140B hub must first be enumerated and configured. In addition, the embedded function must be connected to downstream port 5 of the hub, which is accomplished by setting the embedded function endpoint 0 receive enable bit (RXEN) and transmit enable bit (TXEN) to a 1. After power-on reset, the device will NAK and wait for the embedded function to be connected by the MCU. When new VIDs/PIDs are desired for the USB hub, they must be loaded through the I2C interface before the MCU is connected to the embedded function by enabling the TXEN bit and the RXEN bit. 4.3.1 Interrupt Handler The interrupt handler monitors the various conditions that can cause interrupts and asserts the appropriate interrupt bit when an interrupt condition is pending. If one or more of the interrupt bits is set, the TUSB2140B interrupt output signal (IRQ) will be asserted until the interrupt condition(s) is cleared. The interrupt bits are enabled by setting the corresponding bit in the interrupt mask register. If the interrupt mask bit is cleared, the corresponding interrupt bit will still be set when an interrupt condition occurs. However, the IRQ output signal will not be asserted. This feature is provided for systems that detect pending interrupt conditions with a polling scheme rather than monitoring the IRQ output signal. 4.3.2 Function Reset and USB Reset To reset the embedded function, the host initiates a port reset on the function port which sets the function reset interrupt bit. The function reset will not be enabled unless the MCU clears the function reset interrupt bit (FRST). When a function reset occurs, all of the function interface logic within the TUSB2140B will be reset except the endpoint 0 receive enable bit (RXEN), the endpoint 0 transmit enable bit (TXEN), the FRST, and all of the interrupt mask bits. In addition, the local MCU should respond by setting the default 4–1 configuration, and then should clear the FRST interrupt bit. The USB RESET will only reset the hub logic and not the embedded function logic. 4.3.3 Enumeration After enumeration of the hub and the connection of the embedded function, the host should enable, reset, and set the function address of the embedded function. To enable the port, the host should first power-on the port, which should result in the PWRON5 output signal being asserted. When the embedded function has been enabled, the function enabled bit (FEN), bit 7 of the function address register, will also be set. When the host initiates the port reset for the embedded function, the function reset bit (FRST), bit 3 of the interrupt register, will be set. If the corresponding mask bit is a 1, then the IRQ output signal will be asserted. The local MCU should respond to the FRST by setting the default configuration for the device and then clearing the FRST interrupt bit. To set the function address, the host should initiate the set address command. The embedded function will automatically decode the set address command and set the function address within the embedded function to the address requested by the host. 4.3.4 Control Transfers Control transfers to the embedded function require multiple transactions which use both the embedded function endpoint 0 receive and transmit endpoints. The three types of control transfers are control write, control write with no-data stage and control read. All USB commands, except the set address command, are passed by the embedded function logic to the local MCU which does the decoding. The set address command is handled completely by the embedded function. After the set address command is complete, the function address can be read by the local MCU from the function address register (see Firmware Development Flow Diagram in Appendix A). 4.3.4.1 Control Read Transfers A control read transfer is used by the host to read data from the embedded function. A control read transfer requires a setup stage transaction, at least one in data stage transaction, and an out status stage transaction. As a result, the setup stage transaction and the out status stage transaction use the endpoint 0 receive endpoint and the in data stage transactions use the endpoint 0 transmit endpoint. 4.3.4.2 Control Write Transfers A control write transfer is used by the host to write data to the embedded function. A control write transfer requires a setup stage transaction, at least one out data stage transaction, and an in status stage transaction. As a result, the setup stage transaction and the out data stage transactions use the endpoint 0 receive endpoint and the in status stage transaction uses the endpoint 0 transmit endpoint. 4.3.4.3 Control Write Transfers with No-Data Stages A control write transfer with no-data stages is used by the host to write data to the embedded function. A control write transfer with no-data stages requires a setup stage transaction, no data stage transactions, and an in status stage transaction. As a result, the setup stage transaction uses the endpoint 0 receive endpoint and the in status stage transaction uses the endpoint 0 transmit endpoint. The data written to the function by the host is contained in the setup stage transaction data packet and is limited to two bytes. 4.3.5 Interrupt Transfers The transfer of interrupt type data is accomplished by the TUSB2140B using the interrupt endpoint, which is transmit endpoint 1. In addition to the endpoint 1 transmit FIFO, the operation of transmit endpoint 1 requires the use of 4 registers, which are the endpoint 1 TX byte count register, TX control register, TX status register and TX FIFO flags register. The steps to be followed to transfer interrupt data are as follows: 1. 4–2 The local MCU loads the data packet to be transmitted into the endpoint 1 transmit FIFO. The endpoint 1 transmit FIFO is 8 bytes deep, and therefore, the maximum data packet size is 8 bytes. If a FIFO over-run occurs while loading the data packet, the MCU sets the FIFO clear bit (TXCLR) to clear the FIFO. After the over-run condition is cleared, the MCU loads the data packet into the FIFO again. The FIFO over-run condition results in the FIFO over-run bit (OVRR) being set and the endpoint 1 transmit interrupt bit (EP1TX) being set. The FIFO clear bit (TXCLR) is cleared automatically after the FIFO clear is complete. The MCU should poll the FIFO clear bit to determine when the FIFO clear is complete. After the FIFO clear is complete, the MCU should clear the FIFO over-run bit (OVRR), which automatically clears the endpoint 1 transmit interrupt bit (EP1TX). 2. Next, the local MCU loads the data packet byte count into the endpoint 1 transmit byte count register. Writing the byte count automatically sets the transmit FIFO enable bit (TXFEN) to enable the FCL to send the data packet when the next endpoint 1 In Transaction occurs. 3. At the end of the In Transaction, if the data packet was sent successfully and an acknowledge (ACK) handshake was received from the host, the acknowledge status bit (ACK) and the endpoint 1 transmit interrupt bit (EP1TX) are set. First the interrupt register is read to determine that an endpoint 1 transmit interrupt (EP1TX) has occurred. Then the status register is read to determine that the source of the interrupt was the acknowledge bit (ACK). Note that the transmit FIFO enable bit (TXFEN) is automatically cleared when the ACK bit is set. Finally, the MCU clears the acknowledge status bit (ACK), which automatically clears the interrupt bit (EP1TX). 4.3.6 Suspend and Remote Wake-Up The TUSB2140B embedded function supports both suspend and remote wake-up. The ability to support remote wake-up should be reported by the function to the host in the configuration descriptor for the embedded function. In addition, the host should be able to enable and disable the remote wake-up feature using the set feature device and clear feature device commands. The TUSB2140B will assert the function suspend interrupt bit (FSUSP) if either a global suspend of the entire bus or a selective suspend of the embedded function is detected by the hub. In order for the TUSB2140B to enter a low power suspend state, the local MCU must clear the FSUSP bit. In the low power suspend state, the power control logic within the TUSB2140B will assert the function suspend output signal, FUNCSUSP. In addition, to reduce power consumption to a minimum, the TUSB2140B will disable all clocks including the CLKOUT output signal. The hub logic will shut off the clock only when the MCU enables the logic by clearing the FUNCSUSP interrupt bit. The remote wake-up function allows the local MCU or other logic to initiate a wake-up telling the host to resume USB operations. To initiate the remote wake-up, the active high WAKEUP input signal to the TUSB2140B should be asserted as shown in Figure 5–12. The WAKEUP input to the device will be ignored unless the embedded function is enabled. 4.3.7 I2C Interface The TUSB2140B uses a bidirectional two-wire serial interface to access the internal registers and FIFOs used for the embedded function operations. This serial interface is compatible with the I2C (Inter IC) bus protocol and supports both 100 kbps and 400 kbps data transfer rates. The TUSB2140B is a slave only device on the bus with an assigned I2C device address as shown below in Table 4–1. Table 4–1. I2C Device Address 4.3.7.1 A6 A5 A4 A3 A2 A1 A0 0 1 0 1 1 1 0 R/W Data Transfers The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the TUSB2140B is a slave only device, and therefore, the SCL signal is an input only. The SDA signal is a bidirectional signal that uses an open-drain output to allow the TUSB2140B to be wire-ORed with other devices that use open-drain or open-collector outputs. 4–3 All read and write data transfers on the serial bus are initiated by a master device. The master device is also responsible for generating the clock signal used by the TUSB2140B for all data transfers. The data is transferred on the bus serially one bit at a time. However, the protocol requires that the address and data information be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 5–5. As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can only change states while the SCL signal is low. The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in Figure 5–6. As shown, the start condition is defined as a high-to-low transition of the SDA signal while the SCL signal is high. Also, as shown, the stop condition is defined as a low-to-high transition of the SDA signal while the SCL signal is high. When the TUSB2140B is the device receiving address or data information, the TUSB2140B will acknowledge each byte received by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL period, the master device must stop driving the SDA signal. If the TUSB2140B is unable to receive a byte, the SDA signal will not be driven low and should be pulled high external to the TUSB2140B device. A high during the SCL period indicates a not-acknowledge to the master device. After receiving a not-acknowledge from the TUSB2140B, the master device should generate a stop condition. The output acknowledge timing is shown in Figure 5–7. Read and write data transfers to the TUSB2140B internal registers are done using single byte data transfers. However, read and write data transfers to the TUSB2140B internal FIFOs can be done with either single or multiple byte data transfers. 4.3.7.2 Single Byte Write As shown in Figure 5–8, a single byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit (refer to Table 4–1). The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit should be a 0. After receiving the correct I2C device address and the read/write bit, the TUSB2140B should respond with an acknowledge bit. Next, the master device should transmit the address byte corresponding to the TUSB2140B internal register or FIFO being accessed (see Section 3.1). After receiving the address byte, the TUSB2140B should again respond with an acknowledge bit. Next, the master device should transmit the data byte to be written to the register or FIFO being addressed. After receiving the data byte, the TUSB2140B should again respond with an acknowledge bit. Finally, the master device should transmit a stop condition to complete the single byte data write transfer. 4.3.7.3 Multiple Byte Write A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to the TUSB2140B as shown in Figure 5–9. After receiving each data byte, the TUSB2140B should respond with an acknowledge bit. 4–4 4.3.7.4 Single Byte Read As shown in Figure 5–10, a single byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit (refer to Table 4–1). For the data read transfer, both a write and a read are actually done. Initially, a write is done to transfer the address byte of the internal register or FIFO to be read. As a result, the read/write bit should be a 0. After receiving the I2C device address and the read/write bit the TUSB2140B should respond with an acknowledge bit. Also, after sending the address byte, the master device should transmit another start condition followed by the I2C device address and the read/write bit again. This time the read/write bit should be a 1 indicating a read transfer. After receiving the I2C device address and the read/write bit the TUSB2140B should again respond with an acknowledge bit. Next, the TUSB2140B should transmit the data byte from the register or FIFO being addressed. After receiving the data byte, the master device should transmit a not-acknowledge followed by a stop condition to complete the single byte data read transfer. 4.3.7.5 Multiple Byte Read A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TUSB2140B to the master device as shown in Figure 5–11. Except for the last data byte, the master device should respond with an acknowledge bit after receiving each data byte. 4.4 Over-Current Detection and Power Switching The TUSB2140B provides an active low over-current input signal for each downstream port including the embedded function. External circuitry is required to detect an over-current condition for each port and to assert the appropriate over-current input. When an over-current input is asserted using individual port power management, the TUSB2140B will de-assert the power-on output signal corresponding to the over-current input. The external circuitry should remove power from the appropriate downstream port when the power-on output is de-asserted. In addition, the over-current condition will be reported to the host by the TUSB2140B hub controller. If the ganged port power management mode is used, the GANGED input to the TUSB2140B is set to a 1, then the power-on outputs are all de-asserted at the same time, when any of the over-current inputs are asserted. 4.5 Clock Output Generation The TUSB2140B generates a clock output signal, CLKOUT, that is synchronous to the 48 MHz crystal input. The CLKOUT signal frequency is selected using the two clock select inputs, CLKSEL0 and CLKSEL1. As shown in Table 4–2, the CLKOUT frequency can be selected to be 12 MHz, 8 MHz, 6 MHz or 4 MHz. Table 4–2. Clock Output Signal Frequency CLKSEL1 CLKSEL0 CLKOUT FREQUENCY 0 0 12 MHz 0 1 8 MHz 1 0 6 MHz 1 1 4 MHz The TUSB2140B will only shut off the clock only when the MCU enables it to do so by clearing the FUNCSUSP interrupt bit. See Suspend and Remote Wake-Up in section 4.3.6 for further information. 4–5 4.6 Power Supply Sequencing Turning power supplies on and off with a mixed 5-V/3.3-V system is an important consideration. To avoid possible damage to the TUSB2140B device, proper power sequencing is required. The basic turn on requirement is that the 5-V and 3.3-V power supplies should start ramping from 0 V and reach 95 percent of the final voltage values within 25 ms of each other. The turn-off requirement is that the 5-V and 3.3-V power supplies should start ramping from the steady-state voltage and reach 5 percent of these values with 25 ms of each other. In addition, the difference between the two voltages should never exceed 3.6 V while turning on or off. Normally, in a mixed voltage system, the 3.3-V supply is generated from a voltage regulator running from the 5-V supply. A voltage regulator, such as TI’s TPS7133, can be used to meet these power sequencing requirements. 4–6 5 Electrical Specifications 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)† Supply voltage range, VCC3V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.8 V Supply voltage range, VCC5V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Input voltage range, VI: (3.3 VCC3V) . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC3V + 0.5 V (5 VCC5V) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Output voltage range, VO (3.3 VCC3V) . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC3V + 0.5 V Input clamp current, IIK, (VI < 0 V or VI > VCC3V) . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK, (VO < 0 V or VO > VCC3V) . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage levels are with respect to GND. 5.2 Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage, VCC3V 3 3.3 3.6 V Supply voltage, VCC5V 4.75 5 5.25 V VCC3V VCC5V V V Input voltage, TTL/LVCMOS, VI 0 Input voltage, 5-V tolerant TTL, VI 0 Output voltage, TTL/LVCMOS, VO 0 High-level input voltage, signal-ended receiver, VIH(REC) 2 VCC3V VCC3V Low-level input voltage, signal-ended receiver, VIL(REC) 0 0.8 V High-level input voltage, TTL/LVCMOS, VIH(TTL) 2 V High-level input voltage, 5-V tolerant TTL, VIH(TTL) 2 VCC3V VCC5V Low-level input voltage, TTL/LVCMOS, VIL(TTL) 0 0.8 V Low-level input voltage, 5-V tolerant TTL, VIL(TTL) 0 0.8 V Operating junction temperature, TJ 0 115 °C Operating (dc differential driver) high speed mode, f(OPRH) 12 Mb/s Operating (dc differential driver) low speed mode, f(OPRL) 1.5 Mb/s External series, differential driver resistor, R(DRV) Common mode, input range, differential receiver, V(ICR) Input transition times, tt, TTL/LVCMOS V V V Ω 27 0.8 2.5 V 0 6 ns 5–1 5.3 Electrical Characteristics Over Recommended Ranges of Operating Free-Air Temperature and Supply Voltage (Unless Otherwise Noted) PARAMETER TEST CONDITIONS TTL/LVCMOS VOH High-level output voltage USB data lines TTL /LVCMOS VOL Low-level output voltage USB data lines IOH = – 4 mA R(DRV) = 15 kΩ to GND IOH = – 12 mA (without R(DRV)) MIN MAX UNIT VCC3V – 0.6 2.8 V VCC – 0.5 IOL = 4 mA R(DRV) = 1.5 k Ω to 3.6 V 0.5 0.3 V IOL = 12 mA (without R(DRV)) 0.5 2 V 0.8 V ≤ VICR ≤ 2.5 V 1.8 V Positive input threshold voltage TTL /LVCMOS VIT IT– Negative-input threshold g voltage TTL /LVCMOS Vh hys † Input hysteresis y (VT+ – VT–) TTL /LVCMOS Single-ended 0.8 V ≤ VICR ≤ 2.5 V IOZ High-impedance output g current TTL/LVCMOS V = VCC or GND‡ USB data lines 0 V ≤ VO ≤ VCC ± 10 µA IOZH 5–V tolerant, 3-state output, high-impedance state current VO = 5.5 V 85 µA –1 µA 1 µA 19.9 Ω 100 mA 1 µA VIT IT+ Single-ended Single-ended 0.8 0.8 V ≤ VICR ≤ 2.5 V 1 0.25 300 IIL IIH Low-level input current TTL/LVCMOS High-level input current TTL/LVCMOS VI = GND VI = VCC zo(DRV) Driver output impedance USB data lines Static VOH or VOL 7.1 VID Differential input voltage USB data lines 0.8 V ≤ VICR ≤ 2.5 V 0.2 ICC Input supply current † Applies for input buffers with hysteresis ‡ Applies for open drain buffers 5–2 Normal operation Suspend mode V V 0.7 V 500 mV ± 10 µA V 5.4 Timing Characteristics 5.4.1 Timing Characteristics for USB Transceivers Full Speed Mode MIN MAX tr tf Transition rise time for DP or DM PARAMETER See Figure 5–1 and Figure 5–2 TEST CONDITIONS 4 20 ns Transition fall time for DP or DM See Figure 5–1 and Figure 5–2 4 20 ns t(RFM) VO(CRS) Rise/fall time matching at crossing point (tr/tf) x 100 Signal crossover output voltage UNIT 90 110 % 1.3 2.0 V Low Speed Mode PARAMETER TEST CONDITIONS MIN MAX UNIT 75 300 ns 75 300 ns 80 120 % 1.3 2.0 V tr Transition rise time for DP or DM CL = 50 pF to 350 pF, See Figure 1 and Figure 2 tf Transition fall time for DP or DM CL = 50 pF to 350 pF, See Figure 1 and Figure 2 t(RFM) VO(CRS) Rise/fall time matching at crossing point Signal crossover output voltage (tr/tf) x 100 CL = 50 pF to 350 pF Characterization Measurement Point DP V(TERM) = 2.8 V 22 Ω Full 15 kΩ DM 1.5 kΩ CL 22 Ω Low 15 kΩ CL Figure 5–1. Differential Driver Switching Load 5–3 tr(DP) DM 90% 10% DP VOH 90% 10% VOL tf(DP) (a) DP Rise and Fall Time tr(DM) DM 10% DP VOH 90% 90% 10% VOL tf(DM) (b) DM Fall and Rise Time NOTE: Figures (a) and (b) represent the same waveform but have been separated for clarity. The tr/tf ratio is measured as tr(DP)/tf(DM) and tr(DM)/tf(DP) at each crossover point. Figure 5–2. USB Data Signal Rise and Fall Times V ID – Differential Receiver Input Sensitivity – V 1.5 1.3 1 0.5 0.2 0 0 3 1 2 3.6 0.8 2.5 VICR – Common Mode Input Range – V 4 Figure 5–3. Differential Receiver Input Sensitivity vs Common Mode Input Range 5–4 VCC Vhys Logic high VIH VIT+ VIT– VIL Logic low 0V Figure 5–4. Single-Ended Receiver Input Signal Parameter Definitions Timing Characteristics for I2C Interface 5.4.2 STANDARD MODE PARAMETER FAST MODE MIN MAX MIN MAX 0 100 0 400 UNITS fSCL tw(H) Clock frequency, SCL tw(L) tr Pulse duration, SCL low tf tsu1 Fall time, SCL and SDA th1 tbuf Hold time, SCL to SDA 0 0 ns Bus free time between stop and start condition 4.7 1.3 µs tsu2 th2 Setup time, SCL to start condition 4.7 0.6 µs Hold time, start condition to SCL 4 0.6 µs tsu3 Setup time, SCL to stop condition 4 0.6 µs Pulse duration, SCL high 4 0.6 4.7 1.3 Rise time, SCL and SDA 1000 300 Setup time, SDA to SCL 250 tw(H) tw(L) tr 100 kHz µs µs 300 ns 300 ns ns tf SCL tsu1 th1 SDA Figure 5–5. SCL and SDA Timing SCL tsu2 th2 tsu3 tbuf SDA Start Condition Stop Condition Figure 5–6. Start and Stop Conditions 5–5 5–6 SCL 1 2 8 9 SDA IN SDA OUT Figure 5–7. Output Acknowledge Start Condition Acknowledge A6 SDA A5 A4 A3 A2 A1 A0 R/W ACK * Acknowledge * I2C Device Address and Read/Write Bit * A4 A3 A2 A1 A0 ACK D7 Acknowledge D6 D5 FIFO or Register Address D4 D3 D2 D1 D0 ACK Stop Condition Data Byte * Don’t Care Bits Figure 5–8. Single Byte Write Transfer Start Condition SDA Acknowledge A6 A5 A1 A0 R/W ACK I2C Device Address and Read/Write Bit * Acknowledge * * A4 A3 A1 FIFO or Register Address A0 ACK D7 Acknowledge D6 D1 First Data Byte * Don’t Care Bits Figure 5–9. Multiple Byte Write Transfer D0 ACK Acknowledge D7 Other Data Bytes D6 D1 Last Data Byte D0 ACK Stop Condition Repeat Start Condition Start Condition Acknowledge A6 SDA A5 A1 A0 R/W ACK I2C Device Address and Read/Write Bit * Acknowledge * A4 * A0 Not Acknowledge Acknowledge ACK A6 A5 A1 A0 R/W ACK D7 D6 I2C Device Address and Read/Write Bit FIFO or Register Address D1 D0 ACK Stop Condition Data Byte * Don’t Care Bits Figure 5–10. Single Byte Read Transfer Repeat Start Condition Start Condition SDA Acknowledge A6 A0 R/W ACK * I2C Device Address and Read/Write Bit Acknowledge * * A4 A0 ACK Acknowledge A6 A0 R/W ACK D7 I2C Device Address and Read/Write Bit FIFO or Register Address Not Acknowledge Acknowledge D0 ACK First Data Byte D7 Other Data Bytes D6 D1 D0 ACK Stop Condition Last Data Byte * Don’t Care Bits Figure 5–11. Multiple Byte Read Transfer 5.4.3 Timing Characteristics for Remote Wake-Up PARAMETER tw(H) TEST CONDITIONS Pulse duration, WAKEUP high tw(H) WAKEUP 5–7 Figure 5–12. Remote Wake-Up MIN MAX 0.6 10 UNITS µs 5–8 6 USB Overview Description A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a single personal computer (see Figure 6–1). PC With Root Hub Monitor With 4-Port Hub (Self-Powered) Keyboard With 4-Port Hub (Bus-Powered) Left Speaker Mouse Modem Telephone Right Speaker Printer With 4-Port Hub (Self-Powered) Scanner Digital Scanner Figure 6–1. USB Tiered Configuration Example Another advantage of USB is that all peripherals are connected using a standardized 4-wire cable which provides both communication and power distribution. The three power configurations are bus-powered, self-power and high-power mode. For all three configurations, 100 mA is the maximum current that may be drawn from the USB 5 V line during power-up. For bus-power mode, a hub can draw a maximum of 500 mA from the 5 V line of the USB cable. A bus-powered hub must always be connected downstream to a self-powered hub unless it is the only hub connected to the PC and there are no high-powered functions connected downstream. In the self-power mode, the hub is connected to its own power supply and can supply up to 500 mA to each downstream port. High-powered functions may draw a maximum of 500 mA and may only be connected downstream to self-powered hubs. Per USB Specification, in the bus-powered mode, each downstream port can provide a maximum of 100 mA of current, and in the self-powered mode, each downstream port can provide a maximum of 500 mA of current. Both bus-powered and self-powered hubs require over-current protection for all downstream ports. The two types of protection are individual port management (individual port basis) or ganged port management (multiple port basis). Individual port management requires power management devices for each individual downstream port, but adds robustness to your USB system because, in the event of an over-current condition, the USB host will only power-down the port that has the condition. The ganged configuration uses fewer power management devices and thus has lower system costs, but in the event of an over-current condition on any of the downstream ports, all the ganged ports will be disabled by the USB host. Using a combination of the BUSPWR and GANGED inputs, the TUSB2140B supports four modes of power management: Bus-pPowered hub with either individual port power management or ganged port power management and the self-powered hub with either individual port power management or ganged port power management. When a local micro-controller is connected to the TUSB2140B, the BUSPWR terminal must be pulled to 3.3 V, thus only allowing the self-powered mode with either individual-port or ganged-port power management modes. Texas Instruments supplies complete hub solutions that include this TUSB2140B, the TUSB2043 (4–port), and the TUSB2073 (7-port) hubs along with the power management chips needed to implement a fully USB Specification 1.0 compliant system. See Figure 6–4, 6–5 and 6–6 for example configurations. 6–1 6.1 Application Information The following sections provide examples of how to connect the TUSB2140B chip for different working modes. The terminal number assigned for Figures 6–2, 6–4, 6–5 and 6–6 are for the TUSB2140BN DIP package. Figure 6–2 shows a typical application for the I2C pin-out portion of the TUSB2140B. Depending on the clock rate needed for the MCU, the specific pin configuration for CLKSEL0 and CLKSEL1 is listed on Table 4–2. The 2140B requires a 48-MHz clock signal for correct operation. Figures 6–3 and 6–4 are two examples of how to generate the required 48-MHz signal. Figures 6–4, 6–5 and 6–6 show typical applications for the hub pin-out portion of the TUSB2140B. TUSB2140B I2C Interface 6 29 48–MHz Clock Signal † OVRCUR5 XTAL1 28 PWRON5 XTAL2 VCC 5V Power Management Chips ‡ 36 40 5V 5.1 kΩ 5.1 kΩ 39 3.3 V SCL 38 1.5 kΩ 5 4 3 SDA CLKSEL1 IRQ CLKSEL0 FUNCSUSP WAKEUP GND CLKOUT 37 Any Micro-Controller Unit (MCU) 35 1 2 † See Figures 6–3 and 6–4. ‡ Depending on the application, connect as shown in Figures 6–4, 6–5, or 6–6. NOTE: The CLKSEL1 and CLKSEL0 pins are configured for a 4.0 MHz output at the CLKOUT pin (see Table 4.2) Terminal numbers shown are for the N package Figure 6–2. Typical I2C Interface Connection to a Microcontroller Ceralock Resonator XTAL1 C1 XTAL2 C2 NOTES: A. A simple way to achieve the required 48-MHz clock signal is to use a resonator such as the Ceralock resonator in Figure 6–3. MuRata Electronics, Inc. manufactures a surface mount version, P/N CSACV48.00MXJ4XXXX–TC20, and two dip versions, P/N CSA48.00MXZ4XXXX and P/N CST48.00MXW4XXXX. To meet the ±0.25% total frequency tolerance defined by USB specifications, MuRata will make special sorting available with customers actual PCB, using the TUSB2140B. The above XXXX in the part number determined with the customers PCB. MuRata will assign a full part number when sorting is complete. Please contact the local MuRata sales office for assistance. B. The exact values of the load capacitors C1 and C2 are dependant on the capacitance of the board layout. Increasing the capacitance decreases the amplitude of the clock signal. If the capacitors are too large, the amplitude of the clock signal will not be large enough for the successful numeration of the TUSB2140B by the USB host. Below are the recommended part numbers with the load capacitor values: CSACV48.00MXJ4XXXX–TC20 (without a built-in load capacitor): C1 = C2 = Open; CSA48.00MXZ4XXXX (without a built-in load capacitor): C1 = C2 = 5 pF; CST48.00MXW4XXXX (with built-in load capacitor): C1 = C2 = Open. Ceralock is a trademark of MuRata Electronics Incorporated. Figure 6–3. Resonator Clock Circuit 6–2 6.1 Application Information (continued) R70 2.2 kΩ XTAL2 XTAL1 Y1 C66 47 pF L1 C68 1000 pF 5.6 µH C67 12 pF NOTE A: This application shows a third harmonic 48-MHz crystal, P/N HC-18/U 48-MHz, manufactured by US Crystal, Inc. Since the first harmonic of most crystals is not 48-MHz, a tuning circuit such as this must be used to tune the crystal to the required 48-MHz clock signal. When tuning the crystal (Y1) for different board implementations, the capacitor (C67) and the resistor (R70) are subject to change and the other components should remain the same. Figure 6–4. Crystal Tuning Circuit 6–3 6.2 Bus-Powered Hub, Ganged Port Power Management When used in bus-powered mode, the TUSB2140B supports up to four downstream ports by controlling a TPS2041 device which is capable of supplying 100 mA of current to each downstream port. Bus-powered hubs must implement power switching to ensure current demand is held below 100 mA when the hub is hot-plugged into the system. Utliizing the TPS2041 for ganged power management provides overcurrent protection for the downstream ports. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data lines. The OVRCUR signals should be tied together for a ganged operation. operation. TUSB2140B HUB Portion 3.3 V Upstream Port BUSPWR Downstream Ports 1.5 kΩ 3.3 V GANGED D+ DP0 D– DM0 SN75240† DP1 D+ DM1 A B A C B D 15 kΩ C D D– Ferrite Beads GND 15 kΩ SN75240† 5V DP2 DM2 3.3 V LDO 5V 4.7 µF 0.1 µF 15 kΩ VCC 3.3 V GND GND 100 µF§ 15 kΩ 5V D+ DP3 4.7 µF D– Ferrite Beads DM3 A B XTAL1 48-MHz Clock Signal‡ GND 15 kΩ C D 15 kΩ 5V SN75240† DP4 DM4 100 µF§ 15 kΩ XTAL21 15 kΩ D+ 3.3 V OCSOFF IN 15 kΩ System Power-On Reset PWRON1 RESET PWRON2 D– TPS2041 Ferrite Beads GND 1 µF IN EN 5V OC 100 µF§ PWRON3 PWRON4 OVRCUR1 OVRCUR2 OUT D+ OUT Ferrite Beads OVRCUR3 GND D– GND OVRCUR4 5V † TPS2041 and SN75240 are Texas Instruments devices. The TPS2041 is a single enable, single out power distribution switch device. The TPS2042 is its dual version and the TPS2044 is the quad version. ‡ See Figures 6–3 and 6–4. § 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100 µF low ESR tantulum capacitor per port for immunity to voltage droop. NOTES: A. Terminal numbers shown are for the N package. B. LDS is a 5 V to 3.3 V voltage regulator. 100 µF§ Figure 6–5. TUSB2140B Bus-Powered Hub, Ganged Port Power Management Application 6–4 6.3 Self-Powered Hub, Ganged Port Power Management The TUSB2140B can also be implemented for ganged port power management in a self-powered configuration. The implementation is very similar to the bus-powered example with the exception that a self-powered port supplies 500 mA of current to each downstream port. The over-current protection can be provided by a TPS2044 quad device. TUSB2140B HUB Portion 3.3 V Upstream Port 1.5 kΩ D– GANGED DP1 DM0 SN75240† D+ D– DM1 A C B D 5V Downstream Ports BUSPWR DP0 D+ 3.3 V A B 3.3 V LDO 4.7 µF 0.1 µF 5V 3.3 V VCC 15 kΩ GND 5V DM2 15 kΩ GND GND Ferrite Beads SN75240† DP2 4.7 µF 15 kΩ C D 15 kΩ 100 µF§ DP3 D+ DM3 XTAL1 D– 15 kΩ 48-MHz Clock Signal‡ A B 15 kΩ C D Ferrite Beads GND SN75240† XTAL2 5V DP4 DM4 100 µF§ 15 kΩ 15 kΩ System Power-On Reset 3.3 V RESET 15 kΩ TPS2044† GND PWRON1 D+ D– PWRON2 EN1 EN2 PWRON3 EN3 PWRON4 EN4 OVRCUR1 OVRCUR2 OC1 OC2 100 µF§ OVRCUR3 OC3 D+ OVRCUR4 OC4 IN1 IN2 Ferrite Beads GND 5V D– OUT1 Ferrite Beads OUT2 OCSOFF GND OUT3 OUT4 5V 100 µF§ 5-V Board Power Supply † TPS2044 and SN75240 are Texas Instruments devices. ‡ See Figures 6–3 and 6–4. § 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100 µF low ESR tantulum capacitor per port for immunity to voltage droop. NOTES: A. Terminal numbers shown are for the N package. B. LDS is a 5 V to 3.3 V voltage regulator. Figure 6–6. TUSB2140B Self-Powered Hub, Ganged Port Power Management Application 6–5 6.4 Self-Powered Hub, Individual Port Power Management In a self-powered configuration, the TUSB2140B can be implemented for individual port-power management when used with the TPS2044 because it is capable of supplying 500 mA of current to each downstream port and can provide current limiting on a per port basis. When the hub detects a fault on a downstream port, power is removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data lines. 3.3 V Upstream Port TUSB2140B HUB Portion D+ DP0 D– DM0 5V SN75240† B Downstream Ports BUSPWR DP1 DM1 1.5 kΩ A 3.3 V D+ D– GANGED A C B D 15 kΩ 15 kΩ SN75240† 5V DP2 DM2 C 15 kΩ D 0.1 µF GND DP3 DM3 5V 3.3 V 100 µF§ 15 kΩ 3.3 V LDO 4.7 µF GND 4.7 µF VCC GND A C B D D+ 15 kΩ 15 kΩ D– SN75240† GND DP4 DM4 3.3 V 5V TPS2044† 15 kΩ XTAL1 EN1 PWRON1 48-MHz Clock Signal‡ OUT2 3.3 V D+ OUT3 15 kΩ XTAL2 100 µF§ OUT1 D– EN2 OUT4 PWRON2 3.3 V OCSOFF GND 15 kΩ PWRON3 5V EN3 3.3 V 100 µF§ 15 kΩ System Power-On Reset PWRON4 EN4 D+ D– RESET GND OVRCUR1 OC1 OVRCUR2 OC2 OVRCUR3 OC3 OVRCUR4 OC4 15 kΩ 15 kΩ IN1 IN2 0.1 µF 5-V Board Power Supply GND 5V 100 µF§ † TPS2044 and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044. ‡ See Figures 6–3 and 6–4. § 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100 µF low ESR tantulum capacitor per port for immunity to voltage droop. NOTES: A. Terminal numbers shown are for the N package. B. LDS is a 5 V to 3.3 V voltage regulator. Figure 6–7. TUSB2140B Self-Powered Hub, Individual-Port Power Management Application 6–6 Appendix A Firmware Development Overview of Firmware The flowchart for the main structure of the software program is depicted in Figure A-1. Power up causes all bits in the interrupt register to be set to zeros which then sets the pin IRQ = 1 (no interrupt). After power up, the embedded function must then be enabled (connected logically) to the hub. Enabling the embedded function results from enabling endpoint 0. Endpoint 0 is enabled by setting the EP0 TXEN and EP0 RXEN bits to 1. The interrupt mask register bits then need to be set to 1 in order to allow the corresponding bits of the interrupt register to assert the IRQ signal. Each bit of the interrupt register corresponds to a different interrupt that could occur. The interrupt routines are EP0 transmit, EP0 receive, EP1 transmit, function reset, and function suspend. If any of the five interrupt routines are not desired, the corresponding bit in the interrupt mask register should remain a 0, thus disabling the interrupt bit from asserting the IRQ signal. If the interrupt endpoint (endpoint 1) functionality is desired, the endpoint 1 enable bit (EP1EN) should be set. Now that the proper bits have been set per the above paragraph, the microcontroller will then be in idle state and ready for an occurrence of an interrupt. Upon an interrupt (IRQ=0), the MCU will read the value stored in the interrupt register and based on the value, it will execute one of the five interrupt routines. However, the host controller may decide to initiate a reset or another setup transaction before the current interrupt routine has been completed. The reset or setup transaction will cause hardware to write 0 to all the bits in the interrupt register and the IRQ bit will be set to 1. Then, the hardware will set a bit in the interrupt register that signals the new interrupt conditions. If an error occurs, the ACK handshake may become corrupted which will cause the device to hang because the host and function may disagree on whether the transaction was completed successfully. (Please see the Error Handling on the Last Data Transaction section of the USB Specification for further explanation of error handling by the USB host.) In order to deal with errors, the software must implement a timeout timer which is used to tell the micro-controller when to check the STSGE bit of the EP0 TX status register. If the timer times out, the microcontroller should set the RXFEN bit to 1 in the EP0 RX control register. This will enable the FIFO to receive the data from the host once again. A–1 Enable Endpoint 0 Set Interrupt Mask Register Bits If Endpoint 1 is Needed, Set EP1EN No Yes IRQ = 1 Time Out Identify Interrupt By Reading Interrupt Register Yes EP0TX Yes No EP0 Transmit Service Routine STSGE Error Enable Stall No Yes EP0RX EP0 Receive Service Routine No Yes EP1TX EP1 Transmit Service Routine No Yes FRST Function Reset Service Routine No Yes FSUSP Clear Function Suspend Interrupt No Figure A–1. Flow Chart for TUSB2140B Firmware A–2 No Yes Enable RX FIFO Endpoint 0 Transmit Service Routine The flow diagram for the endpoint 0 transmit service routine is shown in Figure A-2. After detecting that the endpoint 0 transmit interrupt bit (EP0TX) has been set, the MCU should branch to the endpoint 0 transmit service routine. First, the endpoint 0 transmit status register should be read to determine the source of the interrupt. If a successful transmit transaction has occurred, the endpoint 0 transmit acknowledge bit (ACK) will be set. The MCU should clear the interrupt condition by clearing the ACK bit. If the next transaction should be an in data stage, the MCU should load the endpoint 0 transmit FIFO with the next data packet, write the new byte count value to the endpoint 0 transmit byte count register, and reset the timeout timer. However, if the next transaction should be an out status stage, the MCU should set the endpoint 0 receive FIFO enable bit (RXFEN) to allow the status stage to be successfully acknowledged. If the EP0TX interrupt resulted from an endpoint 0 transmit FIFO under-run or over-run condition, the endpoint 0 transmit FIFO under-run (UNDR) or over-run (OVRR) bit will be set, respectively. The under-run or over-run condition should be cleared by setting the endpoint 0 transmit clear bit (TXCLR). EP0TX = 1 Check Transmit Status by Reading TX Status Register No No Yes ACK Clear Interrupt by Writing ACK = 0 in TX Status Register UNDR In Data Yes OVRR Clear Transmit FIFO and Interrupt by Writing TXCLR = 1 in TX Control Register No EMPT Yes No Error Stall EP0 Next Transaction Stage For EP0 Out Status SETUP Stop Timeout Timer Load New Data to Transmit FIFO Write The Number of Data Bytes to TX Byte Count Register Which Also Enables Transmit FIFO Reset Timeout Timer Enable EP0 Receive FIFO RETURN Figure A–2. Endpoint 0 Transmit Interrupt Service Routine A–3 Endpoint 0 Receive Service Routine The flow diagram for the endpoint 0 receive service routine is shown in Figure A-3. After detecting that the endpoint 0 receive interrupt bit (EP0RX) has been set, the MCU should branch to the endpoint 0 receive service routine. First, the endpoint 0 receive status register should be read to determine the source of the interrupt. If a receive transaction has occurred, the endpoint 0 receive acknowledge bit (ACK) will be set. In addition, if the transaction was a setup stage transaction, the endpoint 0 receive setup stage transaction bit (SETUP) will also be set. The MCU should clear the ACK and SETUP bits to clear the interrupt. Note that the SETUP bit must be cleared to enable reading the endpoint 0 receive FIFO. Next, the endpoint 0 receive byte count should be read to determine the number of bytes in the FIFO. Then the FIFO data should be read based on the byte count value. If a FIFO under-run occurs while reading the FIFO, the endpoint 0 receive FIFO under-run bit (UNDR) will be set to indicate the condition. To clear an under-run condition, the MCU should set the endpoint 0 receive clear bit (RXCLR). After successfully reading the data packet from the receive FIFO, the MCU should branch to either the setup stage, out data stage, or out status stage routine based on the current transaction stage flags. In the out data stage routine, the MCU should set the endpoint 0 receive FIFO enable bit (RXFEN) to allow the next data stage data packet to be received. However, if the last data stage is detected, then the MCU should write a value of zero to the endpoint 0 transmit byte count register, which will automatically set the endpoint 0 transmit FIFO enable bit (TXFEN). As a result, the TUSB2140B will acknowledge the next In status stage transaction from the host. In the setup stage routine, the MCU should decode the received data to determine the request type. In addition, the data stage length, direction of data transfer, and direction of status stage should be determined. The MCU should take the appropriate action for each control transfer based on this information. A control read for instance, requires the MCU to load data into the endpoint 0 transmit FIFO for each In data stage. The transmit FIFO can hold a maximum of eight bytes per in data stage transaction. Also, the MCU must enable the endpoint 0 receive FIFO to allow the control read out status stage to be successfully acknowledged. During endpoint 0 receive operations, a receive FIFO over-run condition could occur, which is indicated by an endpoint 0 receive interrupt being generated and the endpoint 0 receive FIFO over-run bit (OVRR) being set. The over-run condition can be cleared by setting the endpoint 0 receive clear bit (RXCLR) in the control register. Once in the endpoint 0 service routine, if the MCU determines that neither the ACK bit or OVRR bit has been set, then the MCU should return to the main program. This scenario can occur when a new setup stage transaction is received while the MCU is branching from the main program to the receive service routine. When the new setup stage is received, the ACK bit will automatically be cleared. A–4 EP0RX = 1 Check Receive Status by Reading Receive Status Register Yes No ACK STSGE = 1 SETUP = 1 Check Overrun by Reading RX Flag Register SETUP or STSGE SETUP = 0 STSGE = 0 Setup Stage Clear Interrupt and Set Flag OVRR Data Stage Clear Interrupt Status Stage Clear Interrupt and Set Flag No Yes Read The Number of Bytes of Data From RX Byte Count Register Read Data From RXFIFO UNDR Yes Clear RX FIFO by Enabling RX CLR in RX Control Register No OUT Status OUT Data Current Transaction Stage SETUP Stop Timer Stop Timer CTL Write Reset Timeout Timer No-Data CTL Write Decode Command Next Stage Status Yes CTL Read Enable RX FIFO Load TX FIFO and Write to TX Byte Count Reg. No Write 0 to TX Byte Count Reg. Enable RX FIFO Enable TX FIFO RETURN Figure A–3. Endpoint 0 Receive Interrupt Service Routine A–5 Endpoint 1 Transmit Service Routine The flow diagram for the endpoint 1 transmit service routine is shown in Figure A-4. After detecting the endpoint 1 transmit interrupt bit (EP1TX) has been set, the MCU should branch to the endpoint 1 transmit service routine. First, the endpoint 1 transmit status register should be read to determine the source of the interrupt. If a successful transmit transaction has occurred, the endpoint 1 transmit acknowledge bit (ACK) will be set. The MCU should clear the interrupt condition by clearing the ACK bit. Next, the MCU should load the endpoint 1 transmit FIFO with the next data packet and write the new byte count value to the endpoint 1 transmit byte count register. If the EP1TX interrupt resulted from an endpoint 1 transmit FIFO under-run or over-run condition, the endpoint 1 transmit FIFO under-run (UNDR) or over-run (OVRR) bit will be set, respectively. The under-run or over-run condition should be cleared by setting the endpoint 1 transmit clear bit (TXCLR). EP1TX = 1 Check Transmit Status by Reading TX Status Register No No UNDR Yes OVRR No ACK Yes Yes Clear Interrupt by Writing ACK = 0 in TX Status Register Clear Transmit FIFO and Interrupt by Writing TXCLR = 1 in TX Control Register No EMPT Yes Error Stall EP1 Load New Data to Transmit FIFO Write The Number of Data Bytes to TX Byte Count Register and Enable Transmit FIFO RETURN Figure A–4. Endpoint 1 Transmit Interrupt Service Routine A–6 Function Reset Service Routine After detecting the function reset interrupt bit (FRST) has been set, the MCU should branch to the function reset service routine. As a result of the TUSB2140B device receiving the USB function reset, all control and status registers will be cleared except the interrupt mask register bits, the endpoint 0 receive enable bit (RXEN), the endpoint 0 transmit enable bit (TXEN) and the function reset interrupt bit (FRST). To clear the function reset interrupt, the MCU should write 08h to the interrupt register. Function Suspend Service Routine When a global or selective suspend condition is detected by the TUSB2140B device, the function suspend interrupt bit (FSUSP) will be set. After detecting the FSUSP bit has been set, the MCU should complete the current routine being processed then write 10h to the interrupt register in order to clear the function suspend interrupt. As a result of the FSUSP bit being cleared by the MCU, the TUSB2140B device will enter the low-power suspend mode and will disable the device clocks. A–7 A–8 Appendix B Firmware Example const BYTE DeviceDescriptor[SIZEOF_DEVICE_DESCRIPTOR] = { SIZEOF_DEVICE_DESCRIPTOR, /*bLength*/ DESC_TYPE_DEVICE, /*bDescriptorType*/ 0x00, 0x01, /*bcdUsb*/ USB_MONITOR_CLASS, /*bDeviceClass*/ USB_MONITOR_SUBCLASS, /*bDeviceSubClass*/ USB_MONITOR_PROTOCOL, /*bDeviceProtocol*/ EP0_MAX_PACKET_SIZE, /*bMaxPacketSize0*/ VENDOR_ID_L, VENDOR_ID_H, /*idVendor*/ PRODUCT_ID_L, PRODUCT_ID_H, /*idProduct*/ MINOR_DEVICE_VER, MAJOR_DEVICE_VER, /*bcdDevice*/ 0x00, /*iManufacturer*/ 0x00, /*iProduct*/ 0x00, /*iSerialNumber*/ 0x01 /*bNumConfigurations*/ }; #define SIZEOF_CONFIG_DESC_GROUP SIZEOF_CONFIG_DESCRIPTOR SIZEOF_INTERFACE_DESCRIPTOR + SIZEOF_HID_DESCRIPTOR + SIZEOF_ENDPOINT_DESCRIPTOR + const BYTE ConfigDescriptorGroup[SIZEOF_CONFIG_DESC_GROUP] = { /* Configuration Descriptor*/ SIZEOF_CONFIG_DESCRIPTOR, /*bLength*/ DESC_TYPE_CONFIG, /*bDescriptorType*/ SIZEOF_CONFIG_DESC_GROUP, 0x00, /*wTotalLength*/ 0x01, /*bNumInterfaces*/ 0x01, /*bConfigurationValue*/ 0x00, /*iConfiguration*/ CFG_DESC_ATTR_SELF_POWERED, /*bmAttributes*/ 0x00, /*MaxPower*/ /* Interface Descriptor*/ SIZEOF_INTERFACE_DESCRIPTOR, DESC_TYPE_INTERFACE, 0x00, 0x00, 0x01, USB_MONITOR_CLASS, USB_MONITOR_SUBCLASS, USB_MONITOR_PROTOCOL, 0x00, /*bLength*/ /*bDescriptorType*/ /*bInterfaceNumber*/ /*bAlternateSetting*/ /*bNumEndpoints*/ /*bInterfaceClass*/ /*bInterfaceSubClass*/ /*bInterfaceProtocol*/ /*iInterface*/ /* HID Descriptor*/ SIZEOF_HID_DESCRIPTOR, /*bLength*/ DESC_TYPE_HID, /*bDescriptorType*/ 0x00, 0x01, /*bcdHid*/ 0x00, /*bCountryCode*/ 0x01, /*bNumDescriptors*/ DESC_TYPE_REPORT, /*bSubDescriptorType*/ SIZEOF_REPORT_DESCRIPTOR, 0x00, /*wSubDescriptorLength*/ /* Endpoint Descriptor*/ SIZEOF_ENDPOINT_DESCRIPTOR, DESC_TYPE_ENDPOINT, 0x01 | EP_DESC_ADDR_DIR_IN, EP_DESC_ATTR_TYPE_INT, 0x08, 0x00, 0xFF /*bLength*/ /*bDescriptorType*/ /*bEndpointAddress*/ /*bmAttributes*/ /*wMaxPacketSize*/ /*bInterval*/ }; #define INT_DESC_OFFSET SIZEOF_CONFIG_DESCRIPTOR #define HID_DESC_OFFSET INT_DESC_OFFSET + SIZEOF_INTERFACE_DESCRIPTOR #define ENDP_DESC_OFFSET HID_DESC_OFFSET + SIZEOF_HID_DESCRIPTOR B–1 /* ––––––––––––––– Global Variables –––––––––––––––*/ DEVICE_REQUEST DeviceRequest; /*Holds last 8 byte device request*/ /* received by endpoint 0*/ BYTE UtilBuf[EP0_MAX_PACKET_SIZE]; /* /*Holds DataIn/DataOut stage packets*/ received or transmitted by endpoint 0*/ BYTE Ep0TxBytesRemaining; /*Holds count of bytes remaining to be*/ /* transmitted by endpoint 0. A value*/ /* of 0 means that a 0 length data packet*/ /* should be transmitted. A value of 0xFF*/ /* means that transfer is complete.*/ BYTE Ep0RxCount; */ /*Holds number of bytes to be read from EP0 Rx FIFO BYTE far * Ep0TxBufferPtr; /*Pointer to buffer of bytes remaining*/ /* to be transmitted by endpoint 0*/ BYTE ConfiguredFlag; /*Set to 1 when USB device has been*/ /* configured, set to 0 when unconfigured*/ BYTE RemoteWakeupEnabledFlag; /*Set to 1 when remote wakeup is enable,*/ /* set to 0 when not enabled*/ BYTE Endpoint1StallFlag; /*Set to 1 when endpoint 1 is stalled,*/ /* set to 0 when not stalled*/ BYTE IdleDuration; /*Contains the value sent in the last*/ /* SetIdle command to any ReportId*/ BYTE ActiveProtocol; /*Set to 0 when boot protocol is active,*/ /* set to 1 when report protocol is active*/ /* =================================== Code ===================================*/ void main (void) /*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––* | This function initializes the TUSB2140 part and then enters the main | | program loop. | | | | Input: Nothing | | | | Uses: Nothing | | | | Output: Nothing | | | | Modifies: Nothing | *––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/ { WORD LoopCount; BYTE temp; SetLedState (3, 0); UsbDataInitialize(); I2CInitialize(); VirtualControlInitialize(); UsbInitialize(); /* Signal start of firmware execution */ /* Init global variables */ /* Init CPU / platform I2C modules */ /* Reset and init monitor / DDC */ /* Init TUSB2140 registers */ LoopCount = 0; while (TRUE) { CheckUsbInterrupt(); ++LoopCount; if (((LoopCount > 20000) && (ConfiguredFlag == 0)) || ((LoopCount > 5000) && (ConfiguredFlag == 1))) { LoopCount = 0; SetLedState (3, !GetLedState (3)); } } } B–2 void UsbDataInitialize (void) /*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––* | This function initializes global variables to a know state. | | | | Input: Nothing | | | | Uses: Nothing | | | | Output: Nothing | | | | Modifies: Ep0TxBytesRemaining = Set to 0xFF to indicate no data is pending | | on the endpoint 0 transmit FIFO | | Ep0TxBufferPtr = Set to NULL | | ConfiguredFlag = Set to 0x00 | | RemoteWakeupEnabledFlag = Set to 0x00 | | Endpoint1StallFlag = Set to 0x00 | | IdleDuration = Set to 0x00 | | ActiveProtocol = Set to 0x00 | *––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/ { /* Clear any bytes remaining to be tranmitted on endpoint 0*/ Ep0TxBytesRemaining = 0xFF; Ep0TxBufferPtr = NULL; /* Set device state to unconfigured*/ ConfiguredFlag = 0x00; /* Set remote wakeup to disabled*/ RemoteWakeupEnabledFlag = 0x00; /* Set endpoint 1 to not stalled*/ Endpoint1StallFlag = 0x00; /* Set idle time to infinite*/ IdleDuration = 0x00; /* Set current protocol to boot*/ ActiveProtocol = 0x00; } void UsbInitialize (void) /*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––* | This function initializes the TUSB2140 internal registers allowing the | | device to be enumerated. Relevant global variables are also cleared. | | | | Input: Nothing | | | | Uses: Nothing | | | | Output: Nothing | | | | Modifies: Nothing | *––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/ { BYTE i; Delay (2000); WakeupTusb2140(); Delay (5); /* Perform register read / write test on the interrupt mask register to ensure the I2C connection to the TUSB2140 is working properly */ for (i=0; i