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TUSB522P
SLLSEV9D – JULY 2016 – REVISED MAY 2019
TUSB522P 3.3 V Dual-Channel USB 3.1 GEN 1 Redriver, Equalizer
1 Features
3 Description
•
The TUSB522P is a fourth generation, dual-channel,
single-lane USB 3.1 GEN1 redriver and signal
conditioner supporting 5 Gbps. The device offers low
power consumption on a 3.3 V supply with its ultralow-power architecture. The redriver also supports
the USB 3.1 low power modes, which further reduces
idle power consumption.
1
•
•
•
•
•
•
•
•
USB3.1 GEN1 5 Gbps, Dual-Channel Re-Driver
with 3.3-V Power Supply
Ultra-Low-Power Architecture
– Active: 98 mA
– U2, U3: 1.2 mA
– Disconnect 265 µA
– Shutdown 60 µA
Optimal Receiver Equalization
– of 3, 6, 9 dB at 2.5 GHz
Output Driver De-emphasis of 0, 3.5, and 6 dB
Automatic LFPS De-Emphasis Control to Meet
USB 3.1 Certification Requirements
No Host/Device-Side Requirement
Hot-Plug Capable
Industrial Temperature Range: –40ºC to 85ºC
TUSB522PI
Commercial Temperature Range: 0ºC to 70ºC
TUSB522P
The dual-channel capability enables the system to
maintain signal integrity on both transmit and receive
data paths. The receiver equalization has three gain
settings to overcome channel degradation from
insertion loss and inter-symbol interference. These
settings are controlled from the EQ pins. To
compensate for transmission line losses, the output
driver supports configuration of De-Emphasis with
pins DE. Additionally, automatic LFPS De-Emphasis
control allows for full USB 3.1 compliance. These
settings allow optimal performance, increased
signaling distance, and flexibility in placement of the
TUSB522P in the USB 3.1 GEN1 path.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
TUSB522P
Cell Phones
Tablets
Notebooks
Desktops
Docking Stations
Backplanes and Active Cables
PACKAGE
BODY SIZE (NOM)
VQFN (24)
TUSB522PI
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
Simplified Schematic
Main PCB
RX1P
RX1N
Connector
Device
DE1
TX2N
TX2N
20"
3m USB
3.0 Cable
1"-6"
TX1N
DEMP
CNTRL
DE2
Dual
Termination
Device PCB
Redriver
TX1P
EQ
CNTRL
EQ2
Main PCB
USB Host
Driver
CHANNEL 1
LFPS
CONTROLLER
EQ1
20"
Receiver/
Equalizer
Dual
Termination
USB
Connector
Detect
Driver
Receiver/
Equalizer
CHANNEL 2
OS
Cntrl.
Dual
Termination
Redriver
Dual
Termination
Detect
USB Host
RX2P
RX2N
EN_RXD
OS1
OS2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB522P
SLLSEV9D – JULY 2016 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics, Power Supply ..................
Electrical Characteristics, DC ...................................
Electrical Characteristics, AC....................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
Changes from Revision C (May 2019) to Revision D
•
Changed pin 11 From: TX1N To: TX2N and pin 12 From: TX1P To: TX2P in Figure 2...................................................... 11
Changes from Revision B (November 2017) to Revision C
•
2
Page
Changed the values in the FOR OS = HIGH column of Table 1 ......................................................................................... 10
Changes from Original (July 2016) to Revision A
•
Page
Deleted the RGE0024F mechanical pages .......................................................................................................................... 15
Changes from Revision A (October 2016) to Revision B
•
Page
Page
Changed the device From Preview To: Production................................................................................................................ 1
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SLLSEV9D – JULY 2016 – REVISED MAY 2019
5 Pin Configuration and Functions
RGE Package
24-Pin (VQFN)
Top View
EN_RXD OS2
NC
6
NC
7
RX1N
8
5
4
DE2
EQ1
VCC
3
2
1
24
NC
23
TX1N
22
TX1P
21
GND
20
RX2N
19
RX2P
CH1
RX1P
9
GND
10
TX2N
11
PAD
(must be soldered to GND)
CH2
TX2P
12
13
14
15
16
17
18
VCC
RSV
OS1
DE1
EQ2
NC
Pin Functions
PIN
NAME
NO.
RX1N
8
I/O
DESCRIPTION
Differential I
Differential input for 5 Gbps negative signal on Channel 1
Differential input for 5 Gbps positive signal on Channel 1
RX1P
9
Differential I
TX1N
23
Differential O Differential output for 5 Gbps negative signal on Channel 1
TX1P
22
Differential O Differential output for 5 Gbps positive signal on Channel 1
RX2N
20
Differential I
Differential input for 5 Gbps negative signal on Channel 2
RX2P
19
Differential I
Differential input for 5 Gbps positive signal on Channel 2
TX2N
11
Differential O Differential output for 5 Gbps negative signal on Channel 2
TX2P
12
Differential O Differential output for 5 Gbps positive signal on Channel 2
EQ1
DE1
OS1
EQ2
2
16
15
17
I, CMOS
Sets the receiver equalizer gain for Channel 1. 3-state input with integrated pull-up and pulldown resistors.
EQ1 = Low = 3 dB
EQ1 = Mid = 6 dB
EQ1 = High = 9 dB
I, CMOS
Sets the output de-emphasis for Channel 1. 3-state input with integrated pull-up and pulldown resistors.
DE1 = Low = 0 dB
DE1 = Mid = -3.5 dB
DE1 = High = -6.2 dB
Note: When OS = Low
I, CMOS
Sets the output swing (differential voltage amplitude) for Channel 1. 2-state input with an
integrated pull down resistor.
OS1 = Low = 0.9 mV
OS1 = High = 1.1 mV
I, CMOS
Sets the receiver equalizer gain for Channel 2. 3-state input with integrated pull-up and pulldown resistors.
EQ2 = Low = 3 dB
EQ2 = Mid = 6 dB
EQ2 = High = 9 dB
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SLLSEV9D – JULY 2016 – REVISED MAY 2019
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Pin Functions (continued)
PIN
NAME
I/O
NO.
DE2
3
DESCRIPTION
I, CMOS
Sets the output de-emphasis for Channel 2. 3-state input with integrated pull-up and pulldown resistors.
DE2 = Low = 0 dB
DE2 = Mid = -3.5 dB
DE2 = High = -6.2 dB
Note: When OS = Low
OS2
4
I, CMOS
Sets the output swing (differential voltage amplitude) for Channel 2. 2-state input with an
integrated pull down resistor.
OS2 = Low = 0.9 mV
OS2 = High = 1.1 mV
EN_RXD
5
I, CMOS
Enable. The device has a 660-kΩ pulldown resistor. Device is active when EN_RXD = High.
Drive actively high or install a pullup resistor (recommend 4.7 KΩ) for normal operation. Does
reset state machine.
RSV
14
I, CMOS
Reserved. Can be left as No-connect.
VCC
1, 13
P
Positive Power Supply. Power Supply is 3.3 V.
GND
10, 21, PAD
G
Ground. PAD must be connected to Ground. Pins 10, 21 can be connected to Ground or left
unconnected.
NC
6, 7, 18, 24
No Connection. These pins can be tied to any desired voltages including connecting them to
GND.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage Range (2)
Voltage Range at any input or output terminal
MIN
MAX
UNIT
VCC
–0.5
4
V
Differential I/O
–0.5
1.5
V
CMOS Inputs
–0.5
4
V
105
°C
150
°C
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
NOM
3
3.3
MAX
UNIT
3.6
V
Supply Ramp Requirement
100
ms
V(PSN)
Supply Noise on VCC Terminals
100
mV
TA
Operating free-air temperature
°C
C(AC)
AC coupling capacitor
VCC
4
Main power supply
MIN
TUSB522P
0
70
TUSB522PI
–40
85
°C
200
nF
75
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6.4 Thermal Information
TUSB522P
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
51.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.9
°C/W
RθJB
Junction-to-board thermal resistance
28.3
°C/W
ψJT
Junction-to-top characterization parameter
2.0
°C/W
ψJB
Junction-to-board characterization parameter
28.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics, Power Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ICC(ACTIVE)
Average active current
Link in U0 with GEN1 data transmission.
RSV, EQ cntrl pins = NC, EN_RXD = VCC,
k28.5 pattern at 5 Gbps,
VID = 1000 mVpp, OS = 900 mV and DE =
3.5 dB
ICC(U2U3)
Average current in U2/U3
ICC(NC)
Average current disconnect mode
ICC(SHUTDOWN)
Average shutdown current
EN_RXD = L
MIN
TYP
MAX
UNIT
98
mA
Link in U2 or U3
1.2
mA
Link in Disconnect mode
265
µA
60
µA
6.6 Electrical Characteristics, DC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3-State CMOS Inputs(EQ1/2, DE1/2)
VIH
High-level input voltage
VIM
Mid-level input voltage
VCC x 0.8
VIL
Low-level input voltage
VF
Floating voltage
RPU
Internal pull-up resistance
RPD
Internal pull-down resistance
IIH
High-level input current
VIN = 3.6 V
IIL
Low-level input current
VIN = GND, VCC = 3.6.V
V
VCC / 2.
V
VCC x 0.2
VIN = High impedance
V
0.36 x VCC
V
410
kΩ
240
kΩ
26
–26
µA
µA
2-State CMOS Input (OS1/2, EN_RXD)
VIH
High-level input voltage
VIL
Low-level input voltage
VCC x 0.7
RPD
Internal pull-down resistance
IIH
Low-level input current
VIN = 3.6 V
IIL
Low-level input current
VIN = GND, VCC = 3.6.V
V
VCC x 0.3
660
25
–10
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V
kΩ
µA
µA
5
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SLLSEV9D – JULY 2016 – REVISED MAY 2019
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6.7 Electrical Characteristics, AC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1200
mVpp
Differential Receiver (RXP, RXN)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
Input differential voltage swing.
V(RX-DIFF-PP)
V(RX-DC-CM)
Common-mode voltage bias in the
receiver (DC)
R(RX-DIFF-DC)
Differential input impedance (DC)
R(RX-CM-DC)
Receiver DC Common Mode
impedance
Z(RX-HIGH-IMP-DC-POS)
0.7
Present after a GEN1 device is
detected on TXP/TXN
Common-mode input impedance with
termination disabled (DC)
Present when no GEN1 device is
detected on TXP/TXN. Measured over
the range of 0-500 mV with respect to
GND.
V(RX-SIGNAL-DET-DIFF-PP)
Input Differential peak-to-peak Signal
Detect Assert Level
V(RX-IDLE-DET-DIFF-PP)
Input Differential peak-to-peak Signal
Detect De-assert Level
V(RX-LFPS-DET-DIFF-PP)
Low Frequency Periodic Signaling
(LFPS) Detect Threshold
Below the minimum is squelched.
V(RX-CM-AC-P)
Peak RX AC common mode voltage
V(detect)
Voltage change to allow receiver detect
C(RX-PARASITIC)
Voltage change to allow receiver detect At 2.5 GHz
RL(RX-DIFF)
Differential Return Loss
RL(RX-CM)
Common Mode Return Loss
100
V
72
120
Ω
18
30
Ω
25
At 5 Gbps, no input channel loss clock
pattern
kΩ
85
mV
85
mV
100
300
mV
Measured at package pin
150
mV
Positive voltage to sense receiver
termination
600
mV
0.17
0.63
0.99
pF
50 MHz – 1.25 GHz at 90 Ω
–19
dB
2.5 GHz at 90 Ω
–14
dB
50 MHz – 1.25 GHz at 90 Ω
–13
dB
Differential Transmitter (TXP, TXN)
V(TX-DIFF-PP)
Transmitter differential voltage swing
(transition-bit)
OS Low, 0dB DE
V(TX-DIFF-PP-LFPS)
LFPS differential voltage swing
OS Low, High
0.8
OS High, 0dB DE
1.1
0.8
DE = Low
V(TX-DE-RATIO)
Transmitter differential voltage DeEmphasis ratio
dB
dB
DE = High
–6.2
dB
Transmitter idle common-mode voltage
change while in U2/U3 and not actively
transmitting LFPS
V(TX-DC-CM)
Common-mode voltage bias in the
transmitter (DC)
V(TX-CM-AC-PP-ACTIVE)
Tx AC Common-mode voltage active
Max mismatch from Txp + Txn for both
time and amplitude
V(TX-IDLE-DIFF-AC-PP)
AC Electrical idle differential peak-topeak output voltage
At package pins
V(TX-IDLE-DIFF-DC)
DC Electrical idle differential output
voltage
At package pins after low pass filter to
remove AC component
DELTA)
Absolute DC common mode voltage
between U1 and U0
C(TX)
TX input capacitance to GND
R(TX-DIFF)
Differential impedance of the driver
R(TX-CM)
Common-mode impedance of the
driver
Measured with respect to AC ground
over 0-500 mV
I(TX-SHORT)
TX short circuit current
TX± shorted to GND
C(TX-PARASITIC)
TX input capacitance for return loss
Package Pins
6
Vpp
–3.5
V(TX-CM-IDLE-DELTA)
Differential Return Loss
Vpp
1.2
DE = Floating
V(TX-RCV-DETECT)
RL(RX-DIFF)
Vpp
1.2
0
Amount of voltage change allowed
during Receiver Detection
V(TX-CM-DC-ACTIVE-IDLE-
0.9
–600
600
mV
600
mV
0.7
V
100
mVpp
0
10
mV
0
10
mV
At package pin
200
mV
At 2.5 GHz
1.25
pF
72
120
Ω
18
30
Ω
60
mA
50 MHz – 1.25 GHz at 90 Ω
1.25 – 2.5 GHz at 90 Ω
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0.63
1.02
F
12
dB
8
dB
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Electrical Characteristics, AC (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RL(RX-CM)
TEST CONDITIONS
Common Mode Return Loss
MIN
TYP
MAX
UNIT
50 MHz – 1.25 GHz at 90 Ω
13
dB
1.25 –2.5 GHz
11
dB
–40
dB
AC Characteristic
Xtalk
Differential Cross Talk between TX and
RX signal Pairs
At 2.5 GHz
V(CM-TX-AC)
AC Common-mode voltage swing in
active mode
Within U0 and within LFPS
V(TX-IDLE-DIFF -AC-PP)
Differential voltage swing during
electrical idle
Tested with a high-pass filter
RL(TX-DIFF)
Differential Return Loss
RL(TX-CM)
Common Mode Return Loss
0
f = 50 MHz - 1.25 GHz
Total Jitter
V(TX-CM-ΔU1-U0)
Absolute delta of DC CM voltage during
active and idle states
V(TX-IDLE-DIFF-DC)
DC Electrical idle differential output
voltage
mVpp
10
V
12
dB
8
dB
f = 50 MHz - 1.25 GHz
16
dB
1.25 –2.5 GHz
13
dB
Minimum input and output trace at 2.5
GHz, VCC = 3.3 V
15
ps
1.25 –2.5 Ghz
tJ
100
Voltage must be low pass filtered to
remove any AC component
0
100
mV
12
mV
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7 Detailed Description
7.1 Overview
The TUSB522P is designed to overcome channel loss due to inter-symbol interference and crosstalk when 5
Gbps USB3.1 GEN1 signals travel across a PCB or cable. The dual channel architecture is a one-chip, lowpower solution, extending the possible channel length for transmit and receive data paths in an application. For a
Host application, this enables the system to pass both transmitter compliance and receiver jitter tolerance tests.
The re-driver recovers incoming data by applying equalization that compensates for channel loss, and drives out
signals with a high differential voltage. Each channel has a receiver equalizer with selectable gain settings. The
equalization should be set based on the amount of insertion loss in channel 1 or 2 before the TUSB522P
receivers. Likewise, the output drivers support configuration of De-Emphasis. Independent equalization and deemphasis control for each channel can be set using EQ1/2 and DE1/2 pins.
The TUSB522P advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB522P periodically performs receiver detection on the TX pairs. If it detects a USB3.1 GEN1 receiver, the
RX termination is enabled, and the TUSB522P is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves Enhanced performance.
The automatic LFPS De-Emphasis control further enables the system to be USB3.1 compliant.
7.2 Functional Block Diagram
EQ1
DE1
OS1
TX1+
CHANNEL 1
Driver
Detect
Receiver/
Equalizer
Termination
Termination
RX1+
TX1-
RX1-1
4th Generation
State Machine
VCC
GND
LFPS
Controller
RX2-
CHANNEL 2
Driver
Receiver/
Equalizer
RX2+
TX2+
OS2
8
Termination
Termination
Detect
TX2-
DE2
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EQ2
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7.3 Feature Description
7.3.1 Receiver Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TUSB522P. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TUSB522P receivers. The gain
setting may differ for channel 1 and channel 2.
7.3.2 De-Emphasis Control and Output Swing
The differential driver output provides selectable de-emphasis and output swing control in order to achieve
USB3.1 compliance. The TUSB522P offers a unique way to adjust output de-emphasis and transmitter swing
based on the OS1/2 and DE1/2 pins. The level of de-emphasis required in the system depends on the channel
length after the output of the re-driver. The output swing and de-emphasis levels may differ for channel 1 and
channel 2.
Figure 1. Transmitter Differential Voltage, OS = Floating
7.3.3 Automatic LFPS Detection
The TUSB522P features an intelligent low frequency periodic signaling (LFPS) controller. The controller senses
the low frequency signals and automatically disables the driver de-emphasis, for full USB3.1 compliance.
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7.4 Device Functional Modes
7.4.1 Device Configuration
Table 1. Control Pin Settings (Typical Values)
PIN
EQ1/EQ2
DESCRIPTION
Equalization Amount
PIN
DESCRIPTION
OS1/OS2
Output Swing Amplitude
LOGIC STATE
GAIN
Low
3 dB
Floating
6 dB
High
9 dB
LOGIC STATE
OUTPUT DIFFERENTIAL VOLTAGE FOR
THE TRANSISTION BIT
LOW
0.9 Vpp
HIGH
1.1 Vpp
DE-EMPHASIS RATIO
PIN
DESCRIPTION
LOGIC STATE
Low
0 dB
0 dB
DE1/DE2
De-Emphasis Amount
Floating
–3.5 dB
–3.5 dB
High
–6.2 dB
–6.2 dB
FOR OS = LOW
FOR OS = HIGH
7.4.2 Power Modes
The TUSB522P has 3 primary power modes:
7.4.2.1 U0 Mode (Active Power Mode)
During active power mode, U0, the device is transmitting USB SS data or USB LFPS signaling. The U0 mode is
the highest power state of the TUSB522P. Anytime super-speed traffic is being received, the TUSB522P remains
in this mode.
7.4.2.2 U2/U3 (Low Power Mode)
While in this mode, the TUSB522P periodically performs far-end receiver detection.
7.4.2.3 Disconnect Mode - RX Detect
In this state, the TUSB522P periodically checks for far-end receiver termination on both TX. Upon detection of
the far-end receiver’s termination on both ports, the TUSB522P will transition to U0 mode.
7.4.2.4 Shutdown Mode
Shutdown mode is entered when the EN_RXD pin is driven low. This is lowest power setting for the device.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TUSB522P is a dual-channel single-lane re-driver and signal conditioner designed to compensate for ISI
jitter caused by attenuation through passive mediums such as traces or cables. The TUSB522P has two
independent channels to allow optimization in both upstream and downstream directions through three EQ and
six De-Emphasis settings.
8.2 Typical Application
2
DN
3
DP
TXN
USB Host
TXP
RXN
RXP
3.3 V
10 mF 0.1 mF
0.1 mF
8
0.1 mF
9
0.1 mF
11
12
0.1 mF
TX1N
RX1N
RX1P
TX1P
TX2N
RX2N
TX2P
RX2P
3.3 V
1
13 VCC
7
NC
NC 24 NC
6
NC
0.1 mF
NC 18
14
NC
RSV
Thermal Pad
10
21 GND
DN
DP
23
0.1 mF
8
SSTXN
22
0.1 mF
9
SSTXP
5
20
19
6
SSRXN
SSRXP
3.3 V
TUSB522P
47 kW
OS1
DE1
EQ1
OS2
DE2
EQ2
EN_RXD
15
16
2
4
3
17
5
USB3.1 Type-A
Receptacle
47 kW
Figure 2. Embedded Host Application
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUE
VCC Supply (3 V – 3.6 V)
3.3 V
AC Coupling Capacitor (75nF to 265nF)
100 nF
Host to TUSB522P FR4 Length (Inches)
20
Host to TUSB522P FR4 Trace Width (mils)
4
TUSB522P to Connector FR4 Length (Inches)
6
TUSB522P to Connector FR4 Trace Width (mils)
4
EQ1 (RX1P/RX1N)
9 dB (EQ1 = High)
De-Emphasis 2 (TX2P/TX2N)
-6.2 dB (OS2 = Low, DE2 = High)
EQ2 (RX2P/RX2N)
6 dB (EQ2 = Floating)
De-Emphasis 1 (TX1P/TX1N)
-3.5 dB (OS1 = Low, DE1 = Floating)
Output Swing 1 (OS1)
900 mV (OS1 = Low)
Output Swing 2 (OS2)
900 mV (OS2 = Low)
8.2.2 Detailed Design Procedure
The TUSB522P differential receivers and transmitters have internal BIAS and termination. Due to this, the
TUSB522P must be connected to the USB Host and receptacle through ac-coupling capacitors. In this example,
as depicted in Table 1, 100 nF capacitors are placed on TX2P, TX2N, RX1P, RX1N, TX1P and TX1N. No accoupling capacitors are placed on the RX2P and RX2N pins because it is assumed the device downstream of the
TUSB522P will have ac-coupling capacitors on its transmitter as defined by the USB 3.1 specification.
12
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8.2.3 Application Curves
BERT > 24"6mil > char-board > RX2-to-TX2 > char-board > Scope
1ft SMP-SMP cable
1ft SMP-SMP cable
MP1800 BERT
5Gbps, 680mVpp
PRBS7
TUSB522
RX2 > TX2
1ft SMP-SMP cable
Input PCB trace
Output PCB trace
25" FR-4
1.0" FR-4
-10.5dB Loss
DCAX
35GHz BW
PTB
-0.8dB Loss
EQ = H, OS = L, DE = L
9 Power Supply Recommendations
The TUSB522P is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power supply integrity.
A 0.1-µF capacitor should be used on each power pin.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
Keep away from other high speed signals.
Intra-pair routing should be kept to within 2mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left
and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will
minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity; and will therefore, negatively impact signal
performance. If test points are used, they should be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair.
The 100-nF capacitors on the TXP and SSTXN nets must be placed close to the USB connector (Type A,
Type B, and so forth).
The ESD and EMI protection devices (if used) must also be placed as close as possible to the USB
connector.
Place voltage regulators as far away as possible from the differential pairs.
In order to minimize crosstalk, TI recommends keeping high-speed signals away from each other. Each pair
must be separated by at least 5 times the signal trace width. Separating with ground also helps minimize
crosstalk.
10.2 Layout Example
Figure 3. Example Layout
14
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TUSB522PIRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TUSB
522P
TUSB522PIRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TUSB
522P
TUSB522PRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB
522P
TUSB522PRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB
522P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of