TUSB8040A1 Evaluation Module
User's Guide
Literature Number: SLLU183A
June 2013 – Revised July 2013
Contents
........................................................................................................................ 3
2
Hardware Overview ............................................................................................................. 4
1
TUSB8040A1 ....................................................................................................................... 4
2
USB Port Connectors .......................................................................................................... 4
2.1
USB Port Connector - Power .......................................................................................... 4
2.2
USB Port Connector – Noise Filtering ................................................................................ 5
3
Hub Configuration ............................................................................................................... 5
4
Optional Serial EEPROM ...................................................................................................... 5
5
Power/Reset ....................................................................................................................... 5
6
Optional Circuitry ................................................................................................................ 6
3
Hardware Set Up ................................................................................................................. 7
1
Configuration Switches ........................................................................................................ 7
2
Hardwired Configurations .................................................................................................... 8
3
EVM Installation .................................................................................................................. 8
4
Troubleshooting .................................................................................................................. 9
Appendix A Schematics ............................................................................................................. 10
Appendix B TUSB8040A1EVM Bill of Materials .............................................................................. 14
1
Introduction
2
Table of Contents
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SLLU183A – June 2013 – Revised July 2013
Introduction
The TI TUSB8040A1EVM is a functional board design of a single device that implements both a USB 3.0
hub and a USB 2.0 hub. The EVM can support both SuperSpeed (SS) and USB 2.0 (HS, FS, and LS)
operation on its USB ports. This EVM is intended for use in evaluating system compatibility, developing
optional EEPROM firmware, and validating interoperability. This EVM also acts as a hardware reference
design for any implementation of the TUSB8040A1.
Upon request, layout files for the EVM can be provided to illustrate techniques used to route the
differential pairs, use of split power planes, placement of filters and other critical components, and
methods used to achieve length matching of critical signals.
Note the EVM dimensions of 3” × 4” accommodates various lab test components, actual production implementations
can be much smaller. Also, the TUSB8040A1EVM is laid out to accept either a TUSB8040A1 unit or a socket. This
socket functionality would not need to be duplicated on a production implementation.
Figure 1. TUSB8040A1EVM Top Layer Layout
Microsoft, Windows are registered trademarks of Microsoft Corporation.
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Introduction
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SLLU183A – June 2013 – Revised July 2013
Hardware Overview
The TUSB8040A1EVM (EVM) board hardware can be divided into five functional areas:
1
TUSB8040A1
The TUSB8040A1 on the EVM (U1 on the schematic) operates as a functional interconnect between an
upstream connection to a USB host or hub and up to four directly connected downstream devices or hubs.
More devices and hubs can be supported if arranged in tiers. The TUSB8040A1 is capable of supporting
operation at USB SuperSpeed (SS), High-Speed (HS), Full Speed (FS) or Low Speed (LS). In general, the
speed of the upstream connection of the EVM limits the downstream connections to that speed (SS, HS,
and FS) or lower.
The TUSB8040A1 requires a 24-MHz low ESR crystal, Y1 with a 1-MΩ feedback resistor. The crystal
should be fundamental mode with a load capacitance of 12–24 pF and a frequency stability rating of ±100
PPM or better. To ensure a proper startup oscillation condition, a maximum crystal equivalent series
resistance (ESR) of 50 Ω is recommended.
The TUSB8040A1 can also use an oscillator or other clock source. When using an external clock source
such as an oscillator, the reference clock should have ±100 PPM (or better) frequency stability and have
less than 50 ps absolute peak-to-peak jitter (or less) than 25 ps peak-to-peak jitter after applying the USB
3.0 jitter transfer function.
2
USB Port Connectors
The EVM is equipped with 5 standard nine pin USB 3.0 port connectors. One of these five connectors, J1,
is a Type B connector designed to interface with an upstream USB host or hub. The remaining
connectors, J2–J5, are Type A connectors for connection to downstream devices or hubs. Standard size
connectors were used on the EVM design, but USB micro connectors can be used if desired. It is also
possible to implement a legacy USB connector on one or more of the downstream ports if SS operation is
not desired.
The USB ports can be attached via a standard USB cable to any USB 3.0 or legacy USB host, hub or
device. The TUSB8040A1 will automatically connect to any upstream USB 3.0 host or hub at both SS and
HS. Using a legacy USB cable between the EVM and a USB 3.0 host or hub will force it to HS operation.
The same is true if a legacy USB cable is used between the EVM and a downstream SS-capable device
in that operation will be limited to USB HS.
2.1
USB Port Connector - Power
VBUS is received from the upstream host or hub on J1. The TUSB8040A1 is configured as a self-powered
hub, so there should not be any significant current draw by the EVM from VBUS. The TUSB8040A1 does
monitor the VBUS input after filtering through a resistor divider network of a 90.9-kΩ 1% resistor, R1, and
a 10-kΩ 1% resistor, R3. VBUS cannot be directly connected to the TUSB8040A1 device.
A bulk capacitor of at least 1 µF is required on the upstream port VBUS input to comply with the USB
specification. The EVM uses a 10-µF capacitor, C37.
VBUS, sourced by the 5-V wall power input, J6, is provided to the downstream port connectors so that bus
powered devices may be attached to the downstream ports. The USB 3.0 specification limits the current
consumption of a USB 3.0 device to 900 mA @ 5 V. The current limiting parameter of the TPS2560
devices, U19 and U21, is configured to 1.5 A to avoid any spurious overcurrent events due to buspowered HDD spin-up power fluctuations: (TPS2560). A production implementation could place stricter
limits on this power consumption. An overcurrent event on any of the downstream port connectors will be
reported to the TUSB8040A1 via the OVERCURxZ inputs.
4
Hardware Overview
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Hub Configuration
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2.2
USB Port Connector – Noise Filtering
Each downstream VBUS output has a 150-µF bulk capacitor (C65, C67, C72, C75) as recommended by
the TPS2560 data manual to prevent in-rush current events on the downstream devices. In addition, there
are ferrite beads and small capacitors on the VBUS lines to reduce noise and address ESD or EMI
concerns.
The EVM also implements optional isolation using two small noise filtering capacitors and a 1-MΩ resistor
between the earth ground of each connector and the digital ground of the EVM, this is not a requirement
but should be used if ground isolation is desired.
Please note that the series capacitors implemented on the SS TX pairs are incorporated to satisfy the
USB 3.0 requirement that differential links be AC coupled on the transmit pair.
3
Hub Configuration
The EVM can be configured by setting several inputs to the TUSB8040A1 that are sampled at power-on
reset or using an optional serial EEPROM. See Configuration Switches for a full description of these
inputs and how to configure them. A production implementation would either rely on the default internal
pull-up or pull-down resistor for each configuration input or override it with an external pull-up or pull-down
resistor.
4
Optional Serial EEPROM
Each EVM is equipped with an onboard EEPROM / socket placeholder. A small I2C EEPROM can be
installed to set the configuration registers as defined in the TUSB8040A1 Data Manual (SLLSEE5). In its
default setting, the EVM does not have an EEPROM installed and instead uses the configuration inputs to
determine any optional settings of the TUSB8040A1.
The EEPROM interface defaults to programmable (not write-protected) so that any installed EEPROM’s
contents may be modified to test various settings. If an EEPROM data change is required, the values may
be changed using the register access methods outlined in the TUSB8040A1 Datasheet. In addition, a
Microsoft® Windows®-based EEPROM utility is available upon request.
5
Power/Reset
The EVM operates from the power provided by a 5-V wall power adapter, not bus power supplied by a
USB host. It is recommended to use a wall power adapter that is capable of sourcing 4.0–5.0 A, because
the hub must be able to source significant power on its downstream ports (900 mA per port).
The EVM uses a single channel LDO voltage regulator to drop 5 V to 3.3 V. The TPS7A4533, U20, is a
1.5-A output linear regulator: TPS7A4533. The 1.1-V core voltage required by the TUSB8040A1 is
sourced by the 3.3-V rail to reduce unnecessary heat dissipation. The TPS74801, U22, is a 1.5-A output
single channel LDO linear regulator: TPS74801. Both regulators require few external passive components
and are appropriately rated for heat dissipation.
The reset source is the RC circuit created by the internal pull-up resistor of GRSTz and the 1-µF
capacitor, C18. The TUSB8040A1 requires a power on reset of 3 ms, the value of the capacitor used in
the RC circuit would vary based on the voltage ramp characteristics of the implementation.
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Optional Circuitry
6
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Optional Circuitry
The EVM design implements a variety of LEDs, none of which are required by the USB specification. They
are provided to make testing and debug easier.
• D1 – Indicates that the upstream USB port is connected at HS.
• D2 – Indicates that the upstream USB port is connected at SS.
• D3 – Indicates that the upstream USB port has entered a HS suspend state.
• D4 - Indicates that the upstream USB port has entered a SS suspend state.
• D7, D8, D10, D11 – Indicate when VBUS is applied to the downstream USB ports. The EVM enables
or disables power to all downstream USB ports simultaneously.
The switches present on the EVM are intended for TI lab evaluation only and are not required for
production designs.
6
Hardware Overview
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Hardware Set Up
1
Configuration Switches
This EVM has two sets of switches to facilitate configuration changes. Changing these switch settings
without a complete understanding of the result is not recommended. Configuration inputs are only read by
the TUSB8040A1 during power-on reset, changing the switch settings while the EVM is powered on will
have no effect. Please refer to Appendix A for additional information in the EVM schematics.
The switch definitions are as follows, with the standard setting in parenthesis:
SW1_1 (on): FULLPWRz Switch. The TUSB8040A1 has an internal pull up on this terminal, so the
TUSB8040A1 defaults to a non full power management mode. If the switch is set to the ON position, the
terminal is pulled low and full power management mode is enabled. This means that the TUSB8040A1
reports that it supports downstream port power switching in the USB descriptors it sends to the USB host.
Since the EVM does implement downstream port power switching, full power management mode should
be enabled.
SW1_2 (off): SMBUSz Switch. The TUSB8040A1 has an internal pull up on this terminal, so I2C interface
mode is enabled by default. If the switch is set to the ON position, the terminal is pulled low and SMBUS
mode is enabled.
SW1_3 (off): SCL (Serial Clock) Switch. The TUSB8040A1 has an internal pull down on this terminal, so
the serial EEPROM/SMBUS interface is disabled. If the switch is set to the ON position, a pull-up resistor
is connected to the serial clock terminal to indicate that an I2C EEPROM may be attached (along with a
pull-up resistor on SDA).
The SCL_SMBCLK terminal is also sampled at the deassertion of reset to determine if USB 3.0 SS low
power states U1 and U2 initiation is disabled. If SCL_SMBCLK is high, U1 and U2 low power state
initiation is disabled. If SCL_SMBCLK is low, U1 and U2 low power states are completely enabled. If the
optional EEPROM or SMBUS is implemented, the value of the u1u2TimerOvr bit of the Device
Configuration Register determines if the low power state initiation is enabled.
SW1_4 (off): SDA (Serial Data) Switch. The TUSB8040A1 has an internal pull down on this terminal, so
the serial EEPROM/SMBUS interface is disabled. If the switch is set to the ON position, a pull-up resistor
is connected to the serial clock terminal to indicate that an I2C EEPROM may be attached (along with a
pull-up resistor on SCL).
The SDA_SMBDAT terminal is also sampled at the deassertion of reset to determine if the USB 3.0 SS
low power states U1 and U2 are disabled. If SDA_SMBDAT is high, U1 and U2 low power states are
completely disabled. If SDA_SMBDAT is low, U1 and U2 low power states are enabled. If the optional
EEPROM or SMBUS is implemented, the value of the u1u2Disable bit of the Device Configuration
Register determines if the low power state U1 and U2 are enabled. Note that disabling U1 and U2 via the
SDA_SMBDAT terminal, overrides the U1 and U2 initiation disable of the SCL_SMBCLK terminal.
SW1_5 (off): PWRz_BAT1 Switch. The TUSB8040A1 has an internal pull down on this terminal, so USB
Battery Charging mode on Port 1 is disabled by default. If the switch is set to the ON position, the terminal
is pulled high and battery charging is enabled on downstream port 1.
SW1_6 (off): PWRz_BAT2 Switch. The TUSB8040A1 has an internal pull down on this terminal, so USB
Battery Charging mode on Port 2 is disabled by default. If the switch is set to the ON position, the terminal
is pulled high and battery charging is enabled on downstream port 2.
SW1_7 (off): PWRz_BAT3 Switch. The TUSB8040A1 has an internal pull down on this terminal, so USB
Battery Charging mode on Port 3 is disabled by default. If the switch is set to the ON position, the terminal
is pulled high and battery charging is enabled on downstream port 3.
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Hardwired Configurations
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SW1_8 (off): PWRz_BAT4 Switch. The TUSB8040A1 has an internal pull down on this terminal, so USB
Battery Charging mode on Port 4 is disabled by default. If the switch is set to the ON position, the terminal
is pulled high and battery charging is enabled on downstream port 4.
SW2_1 (off): USED1 Switch. The TUSB8040A1 has an internal pull up on this terminal, so Port 1 is
enabled by default. If the switch is set to the ON position, the terminal is pulled low, Port 1 is disabled and
the TUSB8040A1 will report as 3 port hub (or less, if other USEDx terminals are set low).
SW2_2 (off): USED2 Switch. The TUSB8040A1 has an internal pull up on this terminal, so Port 2 is
enabled by default. If the switch is set to the ON position, the terminal is pulled low, Port 2 is disabled and
the TUSB8040A1 will report as 3 port hub (or less, if other USEDx terminals are set low).
SW2_3 (off): USED3 Switch. The TUSB8040A1 has an internal pull up on this terminal, so Port 3 is
enabled by default. If the switch is set to the ON position, the terminal is pulled low, Port 3 is disabled and
the TUSB8040A1 will report as 3 port hub (or less, if other USEDx terminals are set low).
SW2_4 (off): USED4 Switch. The TUSB8040A1 has an internal pull up on this terminal, so Port 4 is
enabled by default. If the switch is set to the ON position, the terminal is pulled low, Port 4 is disabled and
the TUSB8040A1 will report as 3 port hub (or less, if other USEDx terminals are set low).
SW2_5 (off): RMBL1 Switch. The TUSB8040A1 has an internal pull up on this terminal, so any devices
connected to Port 1 are reported as removable by default. If the switch is set to the ON position, the
terminal is pulled low and the TUSB8040A1 will report a device connected to Port 1 as non-removable.
SW2_6 (off): RMBL2 Switch. The TUSB8040A1 has an internal pull up on this terminal, so any devices
connected to Port 2 are reported as removable by default. If the switch is set to the ON position, the
terminal is pulled low and the TUSB8040A1 will report a device connected to Port 2 as non-removable.
SW2_7 (off): RMBL3 Switch. The TUSB8040A1 has an internal pull up on this terminal, so any devices
connected to Port 3 are reported as removable by default. If the switch is set to the ON position, the
terminal is pulled low and the TUSB8040A1 will report a device connected to Port 3 as non-removable.
SW2_8 (off): RMBL4 Switch. The TUSB8040A1 has an internal pull up on this terminal, so any devices
connected to Port 4 are reported as removable by default. If the switch is set to the ON position, the
terminal is pulled low and the TUSB8040A1 will report a device connected to Port 4 as non-removable.
2
Hardwired Configurations
PORTINDz - The TUSB8040A1 has an internal pull up on this terminal, so port indicator LED support is
not reported to the USB host, by default.
GANGED - The TUSB8040A1 has an internal pull up on this terminal, so ganged downstream power
switch support is reported to the USB host, by default. Since the EVM has individual downstream port
power switches, this terminal has been pulled low.
HS_SUSPEND_POLARITY - The TUSB8040A1 samples HS_SUSPEND_POLARITY at the deassertion
of reset to determine the polarity of the downstream port power switch enables. The TUSB8040A1 has an
internal pull down on this terminal to set the power enables to active low.
SS_SUSPEND_SSC - The TUSB8040A1 samples SS_SUSPEND_SSC at the deassertion of reset to
determine if SSC is enabled. The TUSB8040A1 has an internal pull down on this terminal to enable SSC.
3
EVM Installation
Install the EVM with the following steps:
1. Attach a 5-V wall power source to J6. LEDs D6 and D9 should turn on.
2. Attach a USB cable between J1 and a USB host. LEDs D5, D7, D8, D10, and D11 should turn on.
(a) If the EVM is attached to a USB 3.0 host, D1 and D2 should turn on.
(b) If the EVM is attached to a USB 2.0 host, D1 should turn on.
8
Hardware Set Up
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Troubleshooting
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4
Troubleshooting
Case 1: Device function(s) are “banged out” in Device Manager.
• Make sure that the latest updates are installed for the operating system.
• Make sure that the latest drivers are installed for the host controller.
Case 2: The EVM does not work at all.
• Verify that all switches are in their default state and the EVM is powered on with a 5-V source with
adequate current.
• If installed, remove the serial EEPROM from the EEPROM socket. The EVM does not require an
EEPROM to operate.
• In the case where a 12-V power supply has been attached to the EVM, the fault is non-recoverable.
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Appendix A Schematics
Figure 2 through Figure 4 contain the schematics for this EVM.
10
Schematics
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Appendix A
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VDD33
BOARD_3P3V
FB1
C2
C1
1uF
0.001uF
C3
1uF
C4
C5
C6
0.001uF
0.01uF
0.1uF
C7
1uF
C8
C9
C10
C11
C12
C13
0.001uF
0.01uF
0.1uF
0.001uF
0.01uF
0.1uF
220 @ 100MHZ
R1
U1_VBUS
PAGE2,3 USB_VBUS_UP
R2
R3
10K
0402
1%
VDD11
Y1
D3
LED
D4
LED
R99
R11
R12
0402
5%
0402
5%
R13
1K
0402
5%
A14
B24
B2
A10
B28
B35
A45
A47
B48
B46
OVERCUR0Z
OVERCUR1Z
OVERCUR2Z
OVERCUR3Z
PORTINDZ_SMBA3
GANGED_SMBA2
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRSTZ
FULLPWRMGMTZ_SMBA1
SMBUSZ
A25
A27
A28
A30
B23
B25
B26
B27
LEDG0Z_USED0
LEDG1Z_USED1
LEDG2Z_USED2
LEDG3Z_USED3
LEDA0Z_RMBL0
LEDA1Z_RMBL1
LEDA2Z_RMBL2
LEDA3Z_RMBL3
PWRON0Z_BATEN0
PWRON1Z_BATEN1
PWRON2Z_BATEN2
PWRON3Z_BATEN3
PAGE3
PAGE3
PAGE3
PAGE3
LEDG0Z_USED0
LEDG1Z_USED1
LEDG2Z_USED2
LEDG3Z_USED3
LEDA0Z_RMBL0
LEDA1Z_RMBL1
LEDA2Z_RMBL2
LEDA3Z_RMBL3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
BOARD_3P3V
R9
NOPOP
R8
9.09K
0402
1%
GANGED
SS
R14
1K
0402
5%
A17
B18
B19
A21
B20
A22
R100
HS
18pF
USB_DP_DN3 PAGE2
USB_DM_DN3 PAGE2
USB_SSRXP_DN3 PAGE2
USB_SSRXM_DN3 PAGE2
USB_SSTXP_DN3 PAGE2
USB_SSTXM_DN3 PAGE2
B21
A23
B22
A24
B37
A41
TUSB8040A1
BOARD_3P3V
D2
LED
SCL_SMBCLK
SDA_SMBDAT
HS
SS
HS_SUSPEND
SS_SUSPEND
B13
B14
B15
A15
A16
1uF
GRSTz
USB_R1
USBR1_RTN
A11
A12
B11
A13
B17
A19
A18
HS
SS
HS_SUSPEND_POLARITY
SS_SUSPEND_SSC
C18
C15
18pF
USB_DP_DN1 PAGE2
USB_DM_DN1 PAGE2
USB_SSRXP_DN1 PAGE2
USB_SSRXM_DN1 PAGE2
USB_SSTXP_DN1 PAGE2
USB_SSTXM_DN1 PAGE2
B29
A31
B30
A33
B31
A34
FULLPWRMGMTZ_SMBA1
SMBUSZ
PWRON0Z_BATEN0
PWRON1Z_BATEN1
PWRON2Z_BATEN2
PWRON3Z_BATEN3
USB_DP_DN2
USB_DM_DN2
USB_SSRXP_DN2
USB_SSRXM_DN2
USB_SSTXP_DN2
USB_SSTXM_DN2
GND
PAD
A9
B9
B6
A7
B7
A8
PAGE2 USB_DP_DN2
PAGE2 USB_DM_DN2
PAGE2 USB_SSRXP_DN2
PAGE2 USB_SSRXM_DN2
PAGE2 USB_SSTXP_DN2
PAGE2 USB_SSTXM_DN2
B36
A39
B33
A36
B34
A37
USB_DP_DN3
USB_DM_DN3
USB_SSRXP_DN3
USB_SSRXM_DN3
USB_SSTXP_DN3
USB_SSTXM_DN3
USB_DP_DN0
USB_DM_DN0
USB_SSRXP_DN0
USB_SSRXM_DN0
USB_SSTXP_DN0
USB_SSTXM_DN0
C14
A49
A48
B45
XI
XO
VSS_OSC
USB_DP_DN1
USB_DM_DN1
USB_SSRXP_DN1
USB_SSRXM_DN1
USB_SSTXP_DN1
USB_SSTXM_DN1
USB_DP_UP
USB_DM_UP
USB_SSRXP_UP
USB_SSRXM_UP
USB_SSTXP_UP
USB_SSTXM_UP
A50
B47
B1
A1
B3
A3
B4
A4
PAGE2 USB_DP_DN0
PAGE2 USB_DM_DN0
PAGE2 USB_SSRXP_DN0
PAGE2 USB_SSRXM_DN0
PAGE2 USB_SSTXP_DN0
PAGE2 USB_SSTXM_DN0
USB_VBUS
A43
A53
B44
A46
B42
A44
B40
B39
A42
PAGE2 USB_DP_UP
PAGE2 USB_DM_UP
PAGE2 USB_SSRXP_UP
PAGE2 USB_SSRXM_UP
PAGE2 USB_SSTXP_UP
PAGE2 USB_SSTXM_UP
ECS-24MHZ
QFN 100
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDDA33_OSC
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
VDD11
U1
D1
LED
1M
VDD33
A2
A5
A6
B8
B10
B12
B16
A20
A26
A29
A32
A35
A38
B38
B41
B43
A52
90.9K
0402
1%
OVERCUR3Z
OVERCUR2Z
OVERCUR1Z
OVERCUR0Z
SCL_SMBCLK
SDA_SMBDAT
PAGE3
PAGE3
PAGE3
PAGE3
R16
4.7K
BOARD_3P3V
BOARD_3P3V
BOARD_3P3V
R93
NOPOP
2
4
6
8
10
Optional EEPROM Circuitry
C19
0.1uF
R35
1K
0402
5%
R36
1K
0402
5%
R37
1K
0402
5%
R95
NOPOP
1
3
5
7
9
A0
A1
A2
GND
VCC
WP
SCLK
SDATA
8
7
6
5
R23
1K
0402
5%
SW1
8-POS 50-MIL SMT
C&K (ITT-CANNON)
TDA08H0SK1R
R96
NOPOP
1
2
3
4
5
6
7
8
FULLPWRMGMTZ_SMBA1
SMBUSZ
SCL_SMBCLK
SDA_SMBDAT
PWRON0Z_BATEN0
PWRON1Z_BATEN1
PWRON2Z_BATEN2
PWRON3Z_BATEN3
TRSTZ
TDO
TDI
TMS
TCK
16
15
14
13
12
11
10
9
JTAG is for lab evaluation only.
The customer can leave these
pins unconnected except for
the pulldown on JTAG_TRSTZ
SCL_SMBCLK
SDA_SMBDAT
R22
1K
0402
5%
R21
4.7K
0402
5%
R20
4.7K
0402
5%
R19
4.7K
0402
5%
R18
4.7K
0402
5%
FULLPWR
SMBUS
SCL_PUP
SDA_PUP
BATEN0
BATEN1
BATEN2
BATEN3
R15
1K
Conn 2x5 shroud_NOPOP
U3
1
2
3
4
JP1
R94
NOPOP
R33
4.7K
0402
5%
R34
4.7K
0402
5%
AT24C04
USE DIP SOCKET:
AMP 2-641260-1
R38
1K
0402
5%
VDD11
BOARD_1P1V
FB2
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
0.001uF
0.01uF
0.1uF
0.001uF
0.01uF
0.1uF
0.001uF
0.01uF
0.1uF
0.001uF
0.01uF
0.1uF
C33
10uF
C34
C35
C36
0.001uF
0.01uF
0.1uF
GND1
0 OHM
GND2
1
C21
1
C20
10uF
Figure 2. TUSB8040A1EVM Schematic
SLLU183A – June 2013 – Revised July 2013
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Copyright © 2013, Texas Instruments Incorporated
11
Appendix A
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USB_VBUS_UP
PAGE1,3
J1
VBUS
DM
DP
GND
SSTXN
SSTXP
GND
SSRXN
SSRXP
SHIELD0
SHIELD1
1
2
3
4
5
6
7
8
9
10
11
C38
0.1uF
C39
0.1uF
C40
0.1uF
C41
0.001uF
PAGE1
USB_DP_UP
PAGE1
USB_SSTXM_UP PAGE1
CAP_UP_TXM
CAP_UP_TXP
USB3_TYPEB_CONNECTOR
USB_DM_UP
C37
10uF
USB_SSTXP_UP PAGE1
USB_SSRXM_UP PAGE1
USB_SSRXP_UP PAGE1
R39
1M
0402
5%
FB3
FB4
DN0_VBUS
C42
0.1uF
J2
DS PORT 1
(Logical DS Port 0)
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
1
2
3
4
5
6
7
8
9
10
11
DN0_VBUS
DN2_VBUS
PAGE3
J3
VBUS_DS0
USB_DM_DN0
USB_DP_DN0
C44
0.1uF
C46
0.1uF
CAP_DN_TXM0
CAP_DN_TXP0
1
2
3
4
5
6
7
8
9
10
11
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
PAGE1
PAGE1
USB_SSRXM_DN0 PAGE1
USB_SSRXP_DN0 PAGE1
USB_SSTXM_DN0 PAGE1
USB_SSTXP_DN0 PAGE1
USB3_TYPEA_CONNECTOR
VBUS_DS2
C49
0.001uF
USB_DM_DN2
USB_DP_DN2
C45
0.1uF
C47
0.1uF
R45
1M
0402
5%
C50
0.1uF
DS PORT 3
(Logical DS Port 2)
C51
0.001uF
USB_SSTXP_DN2 PAGE1
R46
1M
0402
5%
FB6
DN1_VBUS
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
PAGE1
PAGE1
USB_SSRXM_DN2 PAGE1
USB_SSRXP_DN2 PAGE1
USB_SSTXM_DN2 PAGE1
CAP_DN_TXM2
CAP_DN_TXP2
FB5
C52
0.1uF
J4
DS PORT 2
(Logical DS Port 1)
PAGE3
USB3_TYPEA_CONNECTOR
C48
0.1uF
1
2
3
4
5
6
7
8
9
10
11
DN2_VBUS
C43 220 @ 100MHZ
0.1uF
220 @ 100MHZ
DN1_VBUS
220 @ 100MHZ
USB_DM_DN1
USB_DP_DN1
C54
0.1uF
C56
0.1uF
USB3_TYPEA_CONNECTOR
C53
0.1uF
J5
VBUS_DS1
CAP_DN_TXM1
CAP_DN_TXP1
DN3_VBUS
PAGE3
PAGE1
PAGE1
USB_SSRXM_DN1 PAGE1
USB_SSRXP_DN1 PAGE1
USB_SSTXM_DN1 PAGE1
USB_SSTXP_DN1 PAGE1
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
1
2
3
4
5
6
7
8
9
10
11
DN3_VBUS
PAGE3
220 @ 100MHZ
VBUS_DS3
USB_DM_DN3
USB_DP_DN3
C55
0.1uF
C57
0.1uF
CAP_DN_TXM3
CAP_DN_TXP3
PAGE1
PAGE1
USB_SSRXM_DN3 PAGE1
USB_SSRXP_DN3 PAGE1
USB_SSTXM_DN3 PAGE1
DS PORT 4
(Logical DS Port 3)
USB_SSTXP_DN3 PAGE1
USB3_TYPEA_CONNECTOR
C58
0.1uF
C59
0.001uF
R51
1M
0402
5%
C60
0.1uF
C61
0.001uF
R52
1M
0402
5%
Figure 3. TUSB8040A1EVM USB 3 Connectors
12
Schematics
SLLU183A – June 2013 – Revised July 2013
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Copyright © 2013, Texas Instruments Incorporated
Appendix A
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DOWNSTREAM PORTS 1 & 3 POWER
(Logical DS Ports 0 & 2)
BOARD_5V
SILKSCREEN: TIP +5v
J6
2
3
1
BOARD_5V
S
T
2.1mm x 5.5mm
C62
R55
330
0402
5%
0.1uF
U19
2
3
LED5V
C63
10uF
PAGE1 PWRON2Z_BATEN2
PAGE1 PWRON0Z_BATEN0
PWRON2Z_BATEN2
4
PWRON0Z_BATEN0
5
1
11
D6
LED Green 0805
IN
IN
OUT1
FAULT1Z
EN1Z
OUT2
EN2Z
FAULT2Z
GND
PAD
ILIM
9
DN2_VBUS
DN2_VBUS
PAGE2
DN0_VBUS
PAGE2
10
8
DN0_VBUS
6
7
ILIM1
C64
0.1uF
TPS2560DRC
OVERCUR2Z
PAGE1
OVERCUR0Z
PAGE1
OVERCUR1Z
PAGE1
OVERCUR3Z
PAGE1
C66
+
R56
25.5K
0402
5%
C65
150uF
0.1uF
+
C67
150uF
D7
LED Green 0805
D8
LED Green 0805
Limiting DS Port VBUS current to 2.0A per port.
R57
330
0402
5%
BOARD_5V
R58
330
0402
5%
DOWNSTREAM PORTS 2 & 4 POWER
(Logical DS Ports 1 & 3)
3.3V REGULATOR
BOARD_3P3V
BOARD_5V
U20
C68
0.1uF
OUT
TPS7A4533
SENSE
U21
4
2
3
5
C70
10uF
GND
SHDN/
GND
C69
10uF
IN
3
1
PAGE1 PWRON1Z_BATEN1
PAGE1 PWRON3Z_BATEN3
PWRON1Z_BATEN1
4
PWRON3Z_BATEN3
5
1
11
TAB
2
IN
IN
OUT1
FAULT1Z
EN1Z
OUT2
EN2Z
FAULT2Z
GND
PAD
ILIM
9
DN1_VBUS
DN1_VBUS
PAGE2
DN3_VBUS
PAGE2
10
8
DN3_VBUS
6
7
ILIM2
TPS2560DRC
C71
0.1uF
C73
+
R62
25.5K
0402
5%
C72
150uF
0.1uF
+
C75
150uF
D10
LED Green 0805
D11
LED Green 0805
Limiting DS Port VBUS current to 2.0A per port.
R63
330
0402
5%
R64
330
0402
5%
1.1V REGULATOR
PORT USED / REMOVABLE SETTINGS
1P1V_SS
BOARD_3P3V
BOARD_1P1V
SW2
8-POS 50-MIL SMT
C&K (ITT-CANNON)
TDA08H0SK1R
R81
NOPOP
2
3
4
13
14
17
15
TPS74801RGW
GND
PAD
BIAS
OUT1
OUT2
OUT3
OUT4
FB
GND
10
IN1
IN2
IN3
IN4
EN
12
C76
10uF
NC1
NC2
NC3
NC4
NC5
NC6
SS
U22
5
6
7
8
11
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PAGE3
PG
1
18
19
20
16
9
1P1V_FB
R82
1.87K
0402
5%
LEDG0Z_USED0
LEDG1Z_USED1
LEDG2Z_USED2
LEDG3Z_USED3
LEDA0Z_RMBL0
LEDA1Z_RMBL1
LEDA2Z_RMBL2
LEDA3Z_RMBL3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R83
4.7K
0402
5%
C77
10uF
R91
4.99K
0402
5%
R84
4.7K
0402
5%
R85
4.7K
0402
5%
R86
4.7K
0402
5%
R87
4.7K
0402
5%
R88
4.7K
0402
5%
R89
4.7K
0402
5%
R90
4.7K
0402
5%
Figure 4. TUSB8040A1EVM Power
SLLU183A – June 2013 – Revised July 2013
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Schematics
Copyright © 2013, Texas Instruments Incorporated
13
www.ti.com
Appendix B TUSB8040A1EVM Bill of Materials
14
TUSB8040A1EVM Bill of Materials
SLLU183A – June 2013 – Revised July 2013
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Appendix B
www.ti.com
Table 1 contains the BOM for the EVM.
Table 1. TUSB8040A1EVM BOM
Item
Qty
Reference
Part
Manufacturer
Part Number
Pkg
1
4
C1,C3,C7,C18
1uF
TDK
C2012X7R1A105K
805
2
14
C2,C4,C8,C11,C21,C24,C27,
0.001uF
TDK
C1005X7R1H102K
402
0.01uF
AVX
0402YC103KAT2A
402
0.1uF
Yageo
CC0402KRX5R6BB104
402
0.1uF
TDK
C0603X5R0J104M
201
C30,C34,C41,C49,C51,C59,
C61
3
8
C5,C9,C12,C22,C25,C28,
C31,C35
4
24
C6,C10,C13,C19,C23,
C26,C29,C32,C36,C40,C42,
C43,C48,C50,C52,C53,C58,
C60,C62,C64,C66,C68,C71,
C73
5
10
C38,C39,C44,C45,C46,C47
C54,C55,C56,C57
6
2
C14,C15
18pF
AVX
04025A180JAT2A
402
7
8
C20,C33,C37,C63,C69,C70,
10uF
Murata Electronics
GRM31CR61C106KC31L
1206
Kemet
B45197A2157K409
(Tantalum)
7343
C76,C77
8
4
C65,C67,C72,C75
150uF
9
6
R9,R81,R93,R94,R95,R96
NOPOP
10
9
D1,D2,D3,D4
LED Green 0805
Lite On
LTST-C171GKT
805
603
402
D6,D7,D8,D10,D11
11
5
FB1,FB3,FB4,FB5,FB6
220 @ 100MHZ Ferrite Bead
Murata
BLM18PG221SN1D
12
2
SW1,SW2
8-POS 50-MIL SMT
C&K Components
SD08H0SBR
13
1
J1
USB3_TYPEB_CONNECTOR
FoxConn
UEB1112C-2AK1-4H
9_RA_TH_B
14
4
J2,J3,J4,J5
USB3_TYPEA_CONNECTOR
FoxConn
UEA1112C-4HK1-4H
9_RA_TH_A
15
1
J6
2.1mm x 5.5mm DC Power Jack
CUI Inc.
PJ-202AH (PJ-002AH)
2.1mm x 5.5mm
16
6
R2,R39,R45,R46,R51,R52
1M
Rohm Semiconductor
MCR01MZPJ105
402
17
1
R1
90.9K 1%
Rohm Semiconductor
MCR01MZPF9092
402
18
1
R3
10K 1%
Rohm Semiconductor
MCR01MZPF1002
402
19
15
R16,R18,R19,R20,R21,R33,
4.7K
Rohm Semiconductor
MCR01MZPJ472
402
1K
Rohm Semiconductor
MCR01MZPJ102
402
R34,R83,R84,R85,R86,R87,
R88,R89,R90
20
11
R11,R12,R13,R14,R15,R22,
SLLU183A – June 2013 – Revised July 2013
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TUSB8040A1EVM Bill of Materials
Copyright © 2013, Texas Instruments Incorporated
15
Appendix B
www.ti.com
Table 1. TUSB8040A1EVM BOM (continued)
Item
Qty
Reference
Part
Manufacturer
Part Number
Pkg
330
Rohm Semiconductor
MCR01MZPJ331
402
R23,R35,R36,R37,R38
21
7
R55,R57,R58,R63,R64,R99,
R100
22
2
R56,R62
25.5K
Panasonic - ECG
ERJ-2RKF2552X
402
23
1
R82
1.87K
Vishay / Dale
CRCW04021K87FKED
402
24
1
R91
4.99K
Vishay / Dale
CRCW04024K99FKED
402
25
1
U1
TUSB8040A1 - USB 3.0 Hub
Texas Instruments
TUSB8040A1
100QFN
26
1
U3
AT24C04 / SOCKET - I2C EEPROM
Atmel / Tyco
AT24C04A-10PU-1.8 /
2-641260-1
8DIP / 8SOIC SOCKET
27
2
U19,U21
TPS2560DRC - USB Power Switch
Texas Instruments
TPS2560DRC
10SON
28
1
U20
TPS7A4533 - 3.3V Voltage Regulator
Texas Instruments
TPS7A4533KTT
DDPAK-5
29
1
U22
TPS74801RGW - 1.1V Voltage
Regulator
Texas Instruments
TPS74801RGW
20VQFN
30
1
Y1
ECS-24MHZ Crystal
ECS
ECX-53B
(ECS-240-20-30B-TR)
5.0mm x 3.2mm
31
1
JP1
Conn 2x5 shroud
3M
2510-6003UB
HDR5X2 M 0.1" TH
32
1
R8
9.09K 1%
Panasonic - ECG
ERJ-2RKF9091X
402
33
1
FB2
0 ohm
Panasonic - ECG
ERJ-3GEY0R00V
603
16
TUSB8040A1EVM Bill of Materials
SLLU183A – June 2013 – Revised July 2013
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