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TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
TUSB8044A带
带有 USB 告示板四端口 USB 3.2 第 1 代集线器
1 特性
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四端口 USB 3.2 第 1 代 (5Gbps) 集线器
USB 2.0 集线器 特性
– 多个转发器 (MTT) 集线器：四个转发器
– 每个转发器具有两个异步端点缓冲器
支持电池充电：
– 在未连接或未配置上行端口的情况下，可支持
D+/D- 分频器充电端口（ACP1、ACP2 和
ACP3）
– 在未连接上行端口的情况下，可支持自动模式以
在 DCP 或 ACP 模式之间进行切换
– 支持 galaxy 充电
– CDP 模式（上行端口已连接）
– DCP 模式（上行端口未连接）
– DCP 模式符合中国电信行业标准 YD/T 15912009
支持作为一个 USB 3.2 第 1 代或者 USB 2.0 复合
设备运行
支持 USB 告示板 1.21
支持每端口或成组电源开关以及过流通知输入
支持四个外部下行端口且内部仅支持 USB 2.0 端
口，适用于 USB HID 至 I2C 功能和 USB2.0 告示
板
适用于通过 USB HID 以实现 I2C 控制的内部下行
端口支持高速、全速运行。其运行速度与上行端口
速度匹配。
支持读取和写入 I2C 的供应商请求，并且在 100k
和 400k（默认）条件下支持 EEPROM 读取
I2C 主机支持时钟扩展
OTP ROM、串行 EEPROM 或 I2C/SMBus 从机接
口可实现定制配置：
– VID 和 PID
– 端口定制
– 制造商和产品字符串（非通过 OTP ROM）
– 序列号（非通过 OTP ROM）
提供 128 位通用唯一标识符 (UUID)
支持通过 USB 2.0 上行端口进行板载和系统内
EEPROM 编程
单个时钟输入、24MHz 晶体或晶振
仅可对 USB2.0 下行端口进行配置
64 引脚 QFN 封装 (RGC)
3 说明
TUSB8044A 是一款四端口 USB 3.2 第 1 代
（5Gbps）集线器。该器件在上行端口上可提供同步超
快速和高速/全速 USB 连接，在下行端口上可提供超快
速、高速、全速或者低速 USB 连接。当上行端口连接
到一个仅支持高速或全速/低速连接的电气环境中时，
下行端口上的超快速 USB 连接将会禁用。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TUSB8044A
VQFN (64)
9.00mm x 9.00mm
TUSB8044AI
VQFN (64)
9.00mm x 9.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
图
USB 3.1 System Implementation
USB 3.x Host Controller
USB 2.0
Billboard
USB 2.0
Device
USB 3.x Hub
USB 1.1
Device
USB 2.0
HID to I2C
TUSB8044A
USB 2.0
Device
USB 2.0 Hub
USB 2.0
Device
USB 3.x
Device
USB 3.x
Device
USB 3.x
Device
USB 1.1
Device
USB 1.x Connection
USB 2.0 Connection
USB 2.0/3.x Device
USB 2.0 Device
USB 3.x Connection
USB 3.x Device
USB 1.x Device
2 应用
计算机系统、扩展坞、监视器和机顶盒
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF92
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
说明 （续） ..............................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
1
1
1
2
3
4
9
Absolute Maximum Ratings ...................................... 9
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information .................................................. 9
Electrical Characteristics......................................... 10
Timing Requirements .............................................. 12
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
24
8.5 Register Maps ......................................................... 27
9
Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application .................................................. 47
10 Power Supply Recommendations ..................... 56
10.1 TUSB8044A Power Supply ................................... 56
10.2 Downstream Port Power ....................................... 56
10.3 Ground .................................................................. 56
11 Layout................................................................... 57
11.1 Layout Guidelines ................................................. 57
11.2 Layout Examples................................................... 58
12 器件和文档支持 ..................................................... 60
12.1
12.2
12.3
12.4
12.5
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
60
60
60
60
60
13 机械、封装和可订购信息 ....................................... 60
4 修订历史记录
Changes from Original (February 2019) to Revision A
Page
•
将产品说明书状态从“预告信息”更改为“生产数据” ................................................................................................................... 1
2
版权 © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
5 说明 （续）
当上行端口连接到一个仅支持全速/低速连接的电气环境中时，下行端口上的超快速 USB 和高速连接将会禁用。
TUSB8044A 支持每端口或成组电源开关和过流保护，并且还支持电池充电 应用。
按照 USB 主机的要求，一个端口电源单独控制集线器开关为每个下行端口上电或者断电。同样地，当一个端口电
源单独控制集线器感测到一个过流事件时，它只关闭到受影响的下行端口的电源。
当需要为任一端口供电时，一个成组集线器开关打开到其所有下行端口的电源。只有当所有端口处于电源可被移除
的状态时，到下行端口的电源才可被关闭。同样地，当一个成组集线器感测到一个过流事件时，到所有下行端口的
电源将被关闭。
TUSB8044A 下行端口可提供电池充电下行端口 (CDP) 握手支持，以此为电池充电 应用 提供支持。在未连接上行
端口的情况下，该器件还支持专用充电端口 (DCP) 模式。DCP 模式适用于支持 USB 电池充电、Galaxy 充电和符
合中国电信行业标准 YD/T 1591-2009 的 USB 器件。 此外，在未连接上行端口的情况下，TUSB8044A 支持分频
器充电端口模式（ACPx 模式），并且可在所有模式之间进行自动切换，切换顺序从 ACP3 模式开始，到 DCP 模
式结束。
TUSB8044A 中集成了一个 USB2.0 告示板器件，该器件符合“适用于告示板器件的 USB 器件类定义版本 1.21”规
格。告示板器件与TUSB8044A USB 2.0 集线器编号最大的下行端口连接。告示板可用于将交替模式状态告知主机
系统。TUSB8044A 仅支持一种交替模式。
TUSB8044A 能够为包括电池充电支持在内的部分 特性 提供引脚搭接配置，还能够通过 OTP ROM、I2C
EEPROM 或 I2C/SMBus 从机接口为 PID、VID、自定义端口和物理层配置提供定制支持。使用 I2C EEPROM 或
I2C/SMBus 从机接口时，还可以提供定制字串支持。
TUSB8044A 通过内部 USB HID 和 I2C 接口支持连接的 EEPROM 编程。
该器件采用 64 引脚 RGC 封装，商用版 (TUSB8044A) 的工作温度范围为 0°C 至 70°C，工业版 (TUSB8044AI) 的
工作温度范围为 –40°C 至 85°C。
Copyright © 2019, Texas Instruments Incorporated
3
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
6 Pin Configuration and Functions
USB_R1
VDD33
XI
XO
NC
USB_SSRXM_UP
USB_SSRXP_UP
VDD
USB_SSTXM_UP
USB_SSTXP_UP
USB_DM_UP
USB_DP_UP
VDD33
VDD
GRSTz
TEST
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
64 Pin (VQFN)
(Top View)
USB_DP_DN1
1
48
USB_VBUS
USB_DM_DN1
2
47
OVERCUR2z
USB_SSTXP_DN1
3
46
OVERCUR1z
USB_SSTXM_DN1
4
45
BBbmConfigured1/AUTOENz/
HS_SUSPEND
VDD
5
44
OVERCUR3z
USB_SSRXP_DN1
6
43
OVERCUR4z
USB_SSRXM_DN1
7
42
BBEN/GANGED,HS_UP
VDD
8
41
PWRCTL_POL
40
BBbmConfigured0/FULLAUTOz/
FULLPWRMGMTz/SS_UP
USB_DP_DN2
9
Thermal
Pad
29
30
31
32
VDD
PWRCTL4/BATEN4
28
VDD
USB_SSRXP_DN4
27
USB_SSTXM_DN4
USB_SSRXM_DN4
26
USB_SSTXP_DN4
PWRCTL3/BATEN3
25
VDD33
33
24
34
16
USB_DP_DN4
15
VDD33
USB_DM_DN4
USB_SSRXM_DN2
23
PWRCTL2/BATEN2
22
35
USB_SSRXP_DN3
14
USB_SSRXM_DN3
USB_SSRXP_DN2
21
PWRCTL1/BATEN1
VDD
SDA/SMBDAT
36
20
37
13
19
12
VDD
USB_SSTXP_DN3
USB_SSTXM_DN2
USB_SSTXM_DN3
SCL/SMBCLK
18
SMBUSz,SS_SUSPEND
38
17
39
11
USB_DP_DN3
10
USB_DM_DN3
USB_DM_DN2
USB_SSTXP_DN2
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Clock and Reset Signals
GRSTz
50
I, PU
Global power reset. This reset brings all of the TUSB8044A internal registers to their default
states. When GRSTz is asserted, the device is completely nonfunctional.
XI
62
I
Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately
be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback
resistor is required between XI and XO.
XO
61
O
Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an
external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback
resistor is required between XI and XO.
USB_SSTXP_UP
55
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP
56
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP
58
I
USB SuperSpeed receiver differential pair (positive)
USB Upstream Signals
4
Copyright © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
USB_SSRXM_UP
59
I
USB_DP_UP
53
I/O
USB SuperSpeed receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB_DM_UP
54
I/O
USB High-speed differential transceiver (negative)
USB_R1
64
USB_VBUS
48
I
Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1
and GND.
I
USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal
USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground
through a 10-kΩ ±1% resistor from the signal to ground.
USB Downstream Signals
USB_SSTXP_DN1
3
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1
4
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1
6
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1
7
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN1
1
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN1
2
I/O
USB High-speed differential transceiver (negative)
USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 1. This pin be left unconnected if
power management is not implemented.
PWRCTL1/BATEN1
36
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 1 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
USB Port 1 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 1.
0 = An over current event has occurred
OVERCUR1z
46
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN2
11
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2
12
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2
14
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2
15
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN2
9
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN2
10
I/O
USB High-speed differential transceiver (negative)
USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 2. This pin be left unconnected if
power management is not implemented.
PWRCTL2/BATEN2
35
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 2 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
Copyright © 2019, Texas Instruments Incorporated
5
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
USB Port 2 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 2.
0 = An over current event has occurred
OVERCUR2z
47
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN3
19
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3
20
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3
22
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3
23
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN3
17
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN3
18
I/O
USB High-speed differential transceiver (negative)
USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 3. This pin be left unconnected if
power management is not implemented.
PWRCTL3/BATEN3
33
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 3 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
USB Port 3 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 3.
0 = An over current event has occurred
OVERCUR3z
44
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN4
26
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN4
27
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN4
29
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN4
30
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN4
24
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN4
25
I/O
USB High-speed differential transceiver (negative)
USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 4. This pin be left unconnected if
power management is not implemented.
PWRCTL4/BATEN4
32
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 4 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
USB Port 4 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 4.
0 = An over current event has occurred
OVERCUR4z
43
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
I2C/SMBUS I2C Signals
6
Copyright © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
SCL/SMBCLK
38
I/O, PD
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
Can be left unconnected if external interface not implemented.
I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
SDA/SMBDAT
37
I/O, PD
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
Can be left unconnected if external interface not implemented.
I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled
at the de-assertion of reset set I2C or SMBus mode as follows:
1 = I2C Mode Selected
SMBUSz,SS_SUSPEN
D
39
I/O, PU
0 = SMBus Mode Selected
Can be left unconnected if external interface not implemented.
After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if
enabled through the stsOutputEn bit in the Additional Feature Configuration register. When
enabled, a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
Power Control Polarity.
41
The value of the pin is sampled at the de-assertion of reset to set the polarity of
I/O, PU PWRCTL[4:1].
0 = PWRCTL polarity is active low
42
When configured for I2C mode, this pin functions as Billboard Enable. When high, the
billboard device is enabled and presented to system. When low, the billboard device is
disabled. If SMBus is selected, then Billboard enable is controlled by a register.
If SMBus is selected and stsOutputEn bit is set, this pin will function as a HS_UP (upstream
HS connection indicator). When enabled, a value of 1 indicates the upstream port is
I/O, PD
connected to a High-speed USB capable port.
If SMBus is selected, the value of the pin is sampled at the de-assertion of reset to set the
power switch and over current detection mode as follows: 0= Individual port power control
supported. 1= Ganged port Power control supported. SMBus master can at a later time
override the register.
40
When configured for I2C mode, this pin along with BBbmConfigured1 directly controls the
bmConfigurated field in the Billboard Capability descriptor. If SMBus is selected, then
bmConfigured[0] field is determined by a register.
If SMBus is selected and battery charging is enabled on any port, the sampled state of this
pin will set or clear the FullAutoEn bit in the Device Configuration Register 3. SMBus master
can at a later time override the register.
If SMBus is selected and battery charging is disabled, then the value of the pin is sampled at
I/O, PD
the de-assertion of reset to set the power switch control: SMBus master can at a later time
override this function
0 = Power Switching and over current inputs supported.
1= Power Switch and over current inputs not supported.
If SMBus is selected and stsOutputEn bit is set, ths pin will function as a SS_UP (upstream
SS connection indicator). When enabled, a value of 1 indicates the upstream port is
connected to a SuperSpeed USB capable port.
BBbmConfigured1/AUT
OENz/HS_SUSPEND
45
When configured for I2C mode, this pin along with BBbmConfigured0 directly controls the
bmConfigurated field in the Billboard Capability descriptor. If SMBus is selected, then
bmConfigured[1] field is determined by a register.
If SMBus is selected, the sampled value of this pin will set or clear the autoEnz bit in the
I/O, PD
Battery Charging Support Register. SMBus master can at a later time override the register.
If SMBus is selected and stsOutputEn bit is set, this pin will function as a HS_SUSPEND
(upstream HS suspend indicator). When enabled, a value of 1 indicates the connection is
suspended.
TEST
49
PWRCTL_POL
1 = PWRCTL polarity is active high
BBEN/GANGED,HS_UP
BBbmConfigured0/FULL
AUTOz/FULLPWRMGM
Tz/SS_UP
I
This pin is reserved for factory test. For normal operation, this pin requires an external pull
down resistor to ground on PCB. Recommend 10k or stronger resistor.
Power and Ground Signals
Copyright © 2019, Texas Instruments Incorporated
7
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
VDD
5, 8,
13, 21,
28, 31,
51, 57
PWR
1.1-V power rail
VDD33
16, 34,
52, 63
PWR
3.3-V power rail
60
—
NC
8
No connect, leave floating
Copyright © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage
Range
Voltager Range
Tstg
(1)
MIN
MAX
VDD Supply voltage range
-0.3
1.4
UNIT
V
VDD33 Supply voltage range
-0.3
3.8
V
USB_SSRXP_UP, USB_SSRXN_UP, SSRXP_DN[4:1],
USB_RXN_DP[4:1] and USB_VBUS terminals
-0.3
1,4
V
XI terminal
-0.3
2.45
V
All other terminals
-0.3
3.8
V
Storage temperature
-65
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
1.1V Supply voltage
0.99
1.1
1.26
V
VDD33
3.3V Supply voltage
3.0
3.3
3.6
V
0
1.155
V
USB_VBU
Voltage at USB_VBUS terminal.
S
TA
TUSB8044A Ambient temperature
0
70
°C
TA
TUSB8044AI Ambient temperature
-40
85
°C
TJ
Junction temperature
-40
105
°C
7.4 Thermal Information
TUSB8044A
THERMAL METRIC (1)
RGC
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
26
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
11.5
°C/W
RθJB
Junction-to-board thermal resistance
5.3
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
5.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2019, Texas Instruments Incorporated
9
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
7.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low Power Modes
IDD_PWRO
VDD current after Power On (after reset)
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
18
mA
VDD33 current after Power On (after
reset)
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
2
mA
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
20
mA
VDD33 current when upstream port is
disconnected
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
2
mA
VDD current in Suspend
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
25
mA
VDD33 current in Suspend
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
2
mA
VDD current during SMbus programming
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
295
mA
VDD33 current during SMbus
programming
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
75
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 1 SS device, and 0 HS
device. Links in U1/U2.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
240
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 0 HS
device. Links in U1/U2.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
365
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_2S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 2 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
301
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_2S USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
457
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_3S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 3 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
372
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 3 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
N
IDD33_PW
RON
IDD_UPDIS VDD current when upstream port is
disconnected
C
IDD33_UP
DISC
IDD_SUSP
END
IDD33_SUS
PEND
Active Power Modes (US State / DS State)
IDD_SMBU
S
IDD33_SM
BUS
IDD33_3H_
1SS_0HS_
U12
IDD33_3H_
1SS_0HS_
U0
IDD33_3H_
2SS_0HS_
U12
IDD33_3H_
2SS_0HS_
U0
IDD33_3H_
3SS_0HS_
U12
10
Copyright © 2019, Texas Instruments Incorporated
TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD current upstream port connected to
IDD_3H_3S USB 3.0 Host, downstream port(s)
connected to 3 SS devices, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
563
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 3 SS devices, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_4S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 4 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
440
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_4S USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
672
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_4S USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
S_0HS_BB
device. Links in U0. Billboard enabled
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
680
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
device. Links in U0. Billboard enabled
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 1 HS
S_1HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
372
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 1 SS devices, and 1 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
84
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
connected to 2 SS device, and 2 HS
S_2HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
512
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 2 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
95
mA
VDD current upstream port connected to
IDD_2H_0S USB 2.0 Host, downstream port(s)
connected to 0 SS device, and 1 HS
S_1HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
55
mA
VDD33 current upstream port connected
IDD33_2H_ to USB 2.0 Host, downstream port(s)
connected to 0 SS devices, and 1 HS
0SS_1HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_2H_0S USB 2.0 Host, downstream port(s)
connected to 0 SS device, and 4 HS
S_4HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
74
mA
IDD33_3H_
3SS_0HS_
U0
IDD33_3H_
4SS_0HS_
U12
IDD33_3H_
4SS_0HS_
U0
IDD33_3H_
4SS_0HS_
BB
IDD33_3H_
1SS_1HS_
U0
IDD33_3H_
1SS_2HS_
U0
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www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD33 current upstream port connected
IDD33_2H_ to USB 2.0 Host, downstream port(s)
connected to 0 SS devices, and 4 HS
0SS_4HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
76
mA
VDD current upstream port connected to
IDD_2H_0S USB 2.0 Host, downstream port(s)
connected to 0 SS device, and 4 HS
S_4HS_BB
device. Billboard enabled.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
76
mA
VDD33 current upstream port connected
to USB 2.0 Host, downstream port(s)
connected to 0 SS devices, and 4 HS
device. Billboard enabled.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
76
mA
IDD33_2H_
0SS_4HS_
BB
3.3V I/O
VIH
High-level input voltage (1)
2
3.6
V
VIL
Low-level input voltage (1)
0
0.8
V
VI
Input voltage
0
3.6
V
VO
Output voltage (2)
0
3.6
V
tt
Input transition time (tRISE and tFALL)
25
ns
VHYS
Input hysteresis (3)
1.3 x
VDD33
V
VOH
High-level output voltage
IOH = -4 mA
VOL
Low-level output voltage
IOH = 4 mA
IOZP
High-impedance output current with
internal pullup or pulldown resistor. (4)
VI = 0 to VDD33;
VI = 0 to VDD33;
(5)
2.4
V
0.4
V
-250
250
µA
-15
15
µA
II
Input current
RPD
Internal pull-down resistance
13.5
19
27.5
kΩ
RPU
Internal pull-up resistance
14.5
19
25
kΩ
(1)
(2)
(3)
(4)
(5)
Applies to external inputs and bi-directional buffers
Applies to external outputs and bi-directional buffers
Applies to GRSTZ
Applies to pins with internal pullups/pulldowns.
Applies to external input buffers
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Power-on timings. Refer to 图 1
(1) (2)
td1
VDD stable before VDD33 stable.
td2
VDD and VDD33 before de-assertion of GRSTz.
tsu_io
Setup for MISC inputs.
thd_io
tVDD33_RAM
P
tVDD_RAMP
(1)
(2)
(3)
12
Hold for MISC inputs.
(3)
(3)
0
ms
3
ms
0.1
µs
0.1
µs
VDD33 supply ramp requirement.
0.2
100
ms
VDD supply ramp requirement.
0.2
100
ms
As long as GRSTz is de-asserted after both supplies are stable, there is no power-on relationship between VDD33 and VDD. If GRSTz is
only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33.
An active reset is required if the VDD33 supply is stable before VDD supply. This active reset shall meet the 3 ms power-up delay
counting from both power supplies stable to de-assertion of GRSTz.
MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.
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TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
ttd2
GRSTz
VDD33
td1
VDD
tSU_IO
tHD_IO
MISC_IO
图 1. Power-Up Timing Requirements
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TUSB8044A
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www.ti.com.cn
8 Detailed Description
8.1 Overview
The TUSB8044A is a four-port USB 3.2 x1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and
high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed,
or low-speed connections on the downstream ports. When the upstream port is connected to an electrical
environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is
disabled on the downstream ports. When the upstream port is connected to an electrical environment that only
supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the
downstream ports.
8.2 Functional Block Diagram
Power
Distribution
VBUS
Detect
USB 2.0 Hub
XI
SuperSpeed Hub
Oscilator
USB_SSTXM_DN4
USB_SSTXP_DN4
USB_SSRXM_DN4
USB_SSRXP_DN4
USB_SSTXM_DN3
USB_SSTXP_DN3
USB_SSRXM_DN3
USB_SSRXP_DN3
USB_SSTXM_DN2
USB_SSTXP_DN2
USB_SSRXM_DN2
USB_SSRXP_DN2
PWRCTL_POL
SMBUSz/SS_SUSPEND
USB_SSTXM_DN1
USB_SSTXP_DN1
BBbmConfigured0/FULLAUTOz/FULLPWRMGMTz/SS_UP
USB DM DN4
_ _
USB_DP_DN4
HID
to
I2C
TEST
BBEN/GANGED/HS_UP
USB_ DM_ DN3
USB_DP_DN3
USB_DP_DN2
USB_DM_DN2
USB_DP_DN1
USB_DM_DN1
Clock
and
Reset
Distribution
USB_SSRXM_DN1
USB_SSRXP_DN1
XO
GRSTz
USB_SSTXM_UP
USB_SSTXP_UP
USB_SSRXM_UP
USB_SSRXP_UP
VDD
VSS
USB_VBUS
USB_DM_UP
USB_DP_UP
USB_R1
VDD33
Billboard
BBbmConfigured1/AUTOENz/HS_SUSPEND
SCL/SMBCLK
SDA/SMBDAT
OVERCUR1z
PWRCTL1/BATEN1
OVERCUR2z
PWRCTL2/BATEN2
GPIO
I2C
SMBUS
Control
Registers
OTP
ROM
OVERCUR3z
PWRCTL3/BATEN3
OVERCUR4z
PWRCTL4/BATEN4
14
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TUSB8044A
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8.3 Feature Description
8.3.1 Battery Charging Features
The TUSB8044A provides support for USB Battery Charging (BC1.2) and custom charging. Battery charging
support may be enabled on a per port basis through the REG_6h(batEn[3:0]) or the BATEN[4:1] pins.
USB Battery charging support includes both Charging Downstream Port (CDP) and Dedicated Charging Port
(DCP) modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 15912009. CDP is enabled when the upstream port has detected valid VBUS, configured, and host sets port power.
When the upstream port is not connected and battery charging support is enabled, the TUSB8044A will enable
DCP mode once all other battery modes such as ACPx have failed or are disabled.
In addition to USB Battery charging (BC1.2), the TUSB8044A supports custom charging indications: Divider
Charging (ACP3, ACP2, ACP1 modes), and Galaxy compatible charging. These custom charging modes are
only supported when upstream port is unconnected and AUTOMODE is enabled. AUTOMODE can be enabled
either thru AUTOENz pin or from Reg_0Ah bit 1 (autoModeEnz) . When in AUTOMODE and upstream port is
disconnected, the port will automatically transition from ACP mode to the DCP mode depending on the portable
device connected. The divided mode places a fixed DC voltage on the ports DP and DM signals which allows
some devices to identify the capabilities of the charger. The default divider mode indicates support for up to 10W
(ACP3). The divider mode can be configured to report a lower-current setting (up to 5 W) through REG_0Ah
(HiCurAcpModeEn).
When the upstream port is not connected and battery charging support is enabled for a port, the TUSB8044A
drives the port power enable active. If AUTOMODE is disabled, then DCP mode is used. If AUTOMODE is
enabled and fully automatic mode is disabled (FullAutoEn bit is cleared (Reg_25h Bit 0) or FULLAUTOz pin = 0),
then TUSB8044A will start with highest enabled divider current mode (ACPx). The TUSB8044A will remain in
highest current mode as long as a pull-up is not detected on DP pin. If an pull-up is detected on DP pin, then
TUSB8044A will drive the port power enable inactive and switch to Galaxy mode, if enabled, or to DCP mode if
Galaxy mode is disabled. The TUSB8044A will again drive the port power enable active. The TUSB8044A will
remain in Galaxy mode as long as no pull-up is detected on DP pin. If an pull-up is detected on DP pin, then
TUSB8044A will drive the port power enable inactive and transition to DCP mode. The TUSB8044A will again
drive the port power enable active. In DCP mode, the TUSB8044A will look for a pull-up detected on DP pin or
RxVdat. If a pull-up or RxVdat is detected on DP, the TUSB8044A will remain in DCP mode. If no pull-up or
RxVdat is detected on DP pin after 2 seconds, the TUSB8044A will drive the port power enable inactive and
transition back to ACPx mode. This sequence will repeat until upstream port is connected.
When Automatic mode is enabled and full automatic mode is enabled (FullAutoEn Reg_25h bit 0 is set or
FULLAUTOz pin = 1), TUSB8044A will perform same sequence described in previous paragraph with the
addition of attempting all supported ACPx modes before sequencing to Galaxy Mode (if enabled) or DCP mode.
The supported battery charging modes when TUSB8044A configured for SMBus or external EEPROM is detailed
in Battery Charging Modes with SMBus/EEPROM Table.
The supported battery charging modes when TUSB8044A configured for I2C but without an external EEPROM is
determined by the sampled state of the pins. These modes are detailed in Battery Charging Modes without
EEPROM Table.
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Feature Description (接
接下页)
batEn[n] Reg_06h Bits 3:0
Upstream VBUS
HiCurAcpMode En Reg_0Ah Bit 4
autoModeEnz Reg_0Ah Bit 1
FullAutoEn Reg_25h Bit 0
Galaxy_Enz Reg_25h Bit 1
表 1. TUSB8044A Battery Charging Modes with SMBus or I2C EEPROM
Battery Charging Mode Port x
(x = n + 1)
0
Don’t Care
Don't Care
Don’t Care
Don't Care
Don't Care
No Charging support
1
> 4V
Don't Care
Don't Care
Don't Care
Don't Care
CDP
1
< 4V
Don't Care
1
Don't Care
Don't Care
DCP
1
< 4V
X
0
1
1
AUTOMODE enabled. Sequences through all ACPx modes and DCP
Alternate ACP3, ACP2, ACP1, DCP
1
Logical Port1 for USB 3.2 and USB2.0.
1111
1111
0000
4 Port USB 3.2 Hub
6 Port USB2.0 Hub
Port 5 is permanently attached HID
Port 6 is permanently attached Billboard
Physical2 => Logical Port2 for USB 3.2 and USB2.0.
Physical3 => Logical Port3 for USB 3.2 and USB2.0.
Physical4 => Logical Port4 for USB 3.2 and USB2.0.
Physical5 => Logical Port5 for USB2.0.
Physical6 => Logical Port6 for USB2.0.
Physical1 Not used.
1110
1111
0000
3 Port USB 3.2 Hub
5 Port USB2.0 Hub
Port 4 is permanently attached HID
Port 5 is permanently attached Billboard.
Physical2 => Logical Port1 for USB 3.2 and USB2.0.
Physical3 => Logical Port2 for USB 3.2 and USB2.0.
Physical4 => Logical Port3 for USB 3.2 and USB2.0.
Physical5 => Logical Port4 for USB 2.0.
Physical6 => Logical Port5 for USB2.0.
Physical1 Not used.
1100
0111
0000
2 Port USB 3.2 Hub
4 Port USB2.0 hub with permanently attached
device on Port 2
Port 3 is a permanently attached HID
Port 4 is a permanently attached Billboard
Physical2 Not used.
Physical3 => Logical Port1 for USB 3.2 and USB2.0.
Physical4 => Logical Port2 for USB 3.2 and USB2.0.
Physical5 => Logical Port3 for USB2.0.
Physical6 => Logical Port4 for USB2.0.
Physical1 => Logical Port1 for USB 3.2 and USB2.0.
0011
1111
0010
1 Port USB 3.2 Hub
4 Port USB 2.0 Hub
Port 3 is a permanently attached HID
Port 4 is a permanently attached Billboard
Physical2 => Logical Port2 for USB2.0.
Physical3 Not Used.
Physical4 Not used.
Physical5 => Logical Port3 for USB2.0.
Physical6 => Logical Port4 for USB2.0.
Physical1 Not used.
1000
1111
0010
1 Port USB 3.2 Hub
4 Port USB 2.0 Hub
Port 3 is a permanently attached HID
Port 4 is a permanently attached Billboard
Physical2 => Logical Port2 for USB2.0.
Physical3 Not used
Physical4 => Logical Port1 for USB 3.2 and USB2.0.
Physical5 => Logical Port3 for USB2.0.
Physical6 => Logical Port4 for USB2.0.
Physical1 => Logical Port1 for USB 3.2 and USB2.0.
1111
1111
1110
1 Port USB 3.2 Hub
6 Port USB 2.0 Hub
Port 5 is a permanently attached HID
Port 6 is a permanently attached Billboard
Physical2 => Logical Port2 for USB2.0.
Physical3 => Logical Port3 for USB2.0.
Physical4 => Logical Port4 for USB2.0.
Physical5 => Logical Port5 for USB2.0.
Physical6 => Logical Port6 for USB2.0.
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8.4.4 SMBus Slave Operation
When the SMBus interface mode is enabled, the TUSB8044A supports read block and write block protocols as a
slave-only SMBus device.
表 8. TUSB8044A SMBus 7-bit address Mapping
TUSB8044A 7-bit
Address
Register Range
Description
7'b1000100
00h thru FFh
Base 0 Registers
7'b1000101
100h thru 1FFh
Base 1 Registers for Billboard string 1 and 2
7'b1000110
200h thru 2DFh
Base 2 Registers for Billboard string 1 and 2
For details on SMBus requirements, refer to the System Management Bus Specification.
注
If the TUSB8044A is addressed by a host using an unsupported protocol it will not
respond. The TUSB8044A waits indefinitely for configuration by the SMBus host and will
not connect on the upstream port until the SMBus host indicates configuration is complete
by clearing the CFG_ACTIVE bit.
26
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TUSB8044A
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8.5 Register Maps
8.5.1 Configuration Registers
The internal configuration registers are accessed on byte boundaries. The configuration register values are
loaded with defaults but can be over-written when the TUSB8044A is in I2C or SMBus mode. Refer to 表 6 for
registers configurable from OTP.
表 9. TUSB8044A Register Map
BYTE
ADDRESS
CONTENTS
EEPROM CONFIGURABLE
00h
ROM Signature Register
Yes
01h
Vendor ID LSB
Yes
02h
Vendor ID MSB
Yes
03h
Product ID LSB
Yes
04h
Product ID MSB
Yes
05h
Device Configuration Register
Yes
06h
Battery Charging Support Register
Yes
07h
Device Removable Configuration Register
Yes
08h
Port Used Configuration Register
Yes
09h
Reserved. Must default to 00h.
Yes
0Ah
Device Configuration Register 2
Yes
0Bh
USB 2.0 Port Polarity Control Register
Yes
0Ch - 0Fh
Billboard AlternateModeVdo
Yes
10h-1Fh
UUID Byte [15:0]
No
20h-21h
LangID Byte [1:0]
Yes
22h
Serial Number Length
Yes
23h
Manufacturer String Length
Yes
24h
Product String Length
Yes
25h
Device Configuration Register 3
Yes
26h
USB 2.0 Only Port Register
Yes
27h
Billboard SVID LSB
Yes
28h
Billboard SVID MSB
Yes
29h
Billboard PID LSB
Yes
2Ah
Billboard PID MSB
Yes
2Bh
Billboard Configuration
Yes
2Ch
Billboard String1Len
Yes
2Dh
Billboard String2Len
Yes
2Eh
Reserved
No
2Fh
Reserved
No
30h-4Fh
Serial Number String Byte [31:0]
Yes
50h-8Fh
Manufacturer String Byte [63:0]
Yes
90h-CFh
Product String Byte [63:0]
Yes
D0h-D4h
Reserved
Yes, but do not change default.
D5h-D7h
Reserved
No
D8h-DCh
Reserved
Yes, but do not change default.
DDh-EFh
Reserved
No
F0h
Additional Features Configuration Register
Yes
F1h-F7h
Reserved
No
F8h
SMBus Device Status and Command Register
No
F9h - FFh
Reserved
No
版权 © 2019, Texas Instruments Incorporated
27
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表 9. TUSB8044A Register Map (接
接下页)
28
BYTE
ADDRESS
CONTENTS
EEPROM CONFIGURABLE
100h - 2DFh
USB Billboard Strings 1 and 2
Yes
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8.5.2 ROM Signature Register
图 3. Register Offset 0h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 10. Bit Descriptions – ROM Signature Register
Bit
7:0
Field
romSignature
Type
Description
RW
ROM Signature Register. This register is used by the TUSB8044A in
I2C mode to validate the attached EEPROM has been programmed.
The first byte of the EEPROM is compared to the mask 55h and if not
a match, the TUSB8044A aborts the EEPROM load and executes with
the register defaults.
8.5.3 Vendor ID LSB Register
图 4. Register Offset 1h
Bit No.
Reset State
7
0
6
1
5
0
4
1
3
0
2
0
1
0
0
1
表 11. Bit Descriptions – Vendor ID LSB Register
Bit
7:0
Field
vendorIdLsb
Type
Description
RO/RW
Vendor ID LSB. Least significant byte of the unique vendor ID
assigned by the USB-IF; the default value of this register is 51h
representing the LSB of the TI Vendor ID 0451h. The value may be
over-written to indicate a customer Vendor ID.
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 51h.
8.5.4 Vendor ID MSB Register
图 5. Register Offset 2h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
表 12. Bit Descriptions – Vendor ID MSB Register
Bit
7:0
Field
vendorIdMsb
版权 © 2019, Texas Instruments Incorporated
Type
Description
RO/RW
Vendor ID MSB. Most significant byte of the unique vendor ID
assigned by the USB-IF; the default value of this register is 04h
representing the MSB of the TI Vendor ID 0451h. The value may be
over-written to indicate a customer Vendor ID.
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 04h.
29
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8.5.5 Product ID LSB Register
图 6. Register Offset 3h
Bit No.
Reset State
7
0
6
1
5
0
4
0
3
0
2
0
1
0
0
0
表 13. Bit Descriptions – Product ID LSB Register
Bit
7:0
Field
productIdLsb
Type
Description
RO/RW
Product ID LSB. Least significant byte of the product ID assigned by
Texas Instruments and reported in the SuperSpeed Device descriptor.
the default value of this register is 40h representing the LSB of the
SuperSpeed product ID assigned by Texas Instruments The value
reported in the USB 2.0 Device descriptor is the value of this register
bit wise XORed with 00000010b. The value may be over-written to
indicate a customer product ID.
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 40h .
8.5.6 Product ID MSB Register
图 7. Register Offset 4h
Bit No.
Reset State
7
1
6
0
5
0
4
0
3
0
2
1
1
0
0
0
表 14. Bit Descriptions – Product ID MSB Register
Bit
7:0
30
Field
productIdMsb
Type
Description
RO/RW
Product ID MSB. Most significant byte of the product ID assigned by
Texas Instruments; the default value of this register is 84h representing
the MSB of the product ID assigned by Texas Instruments. The value
may be over-written to indicate a customer product ID.
Value used for this field will be the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field
will be the non-zero value from OTP. If a zero value is written by OTP,
then value used for this field will be 84h.
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8.5.7 Device Configuration Register
图 8. Register Offset 5h
Bit No.
Reset State
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
0
表 15. Bit Descriptions – Device Configuration Register
Bit
7
6
Field
customStrings
customSernum
Type
Description
RW
Custom strings enable. This bit controls the ability to write to the
Manufacturer String Length, Manufacturer String, Product String
Length, Product String, and Language ID registers
0 = The Manufacturer String Length, Manufacturer String, Product
String Length, Product String, and Language ID registers are read only
1 = The Manufacturer String Length, Manufacturer String, Product
String Length, Product String, and Language ID registers may be
loaded by EEPROM or written by SMBus
The default value of this bit is 0.
RW
Custom serial number enable. This bit controls the ability to write to the
serial number registers.
0 = The Serial Number String Length and Serial Number String
registers are read only
1 = Serial Number String Length and Serial Number String registers
may be loaded by EEPROM or written by SMBus
The default value of this bit is 0.
5
u1u2Disable
RW
U1 U2 Disable. This bit controls the U1/U2 support.
0 = U1/U2 support is enabled
1 = U1/U2 support is disabled, the TUSB8044A will not initiate or
accept any U1 or U2 requests on any port, upstream or downstream,
unless it receives or sends a Force_LinkPM_Accept LMP. After
receiving or sending an FLPMA LMP, it will continue to enable U1 and
U2 according to USB 3.2 protocol until it gets a power-on reset or is
disconnected on its upstream port.
When the TUSB8044A is in I2C mode, the TUSB8044A loads this bit
from the contents of the EEPROM.
When the TUSB8044A is in SMBUS mode, the value may be overwritten by an SMBus host.
4
RSVD
RO
Reserved. This bit is reserved and returns 1 when read.
RW
Ganged.
0 = When fullPwrMgmtz = 0, each port is individually power switched
and enabled by the PWRCTL[4:1]/BATEN[4:1] pins
1 = When fullPwrMgmtz = 0, the power switch control for all ports is
ganged and enabled by the PWRCTL[4:1]/BATEN1 pin
When the TUSB8044A is in I2C mode, the TUSB8044A loads this bit
from the contents of the EEPROM.
When the TUSB8044A is in SMBUS mode, the value may be overwritten by an SMBus host.
RW
Full Power Management.
0 = Port power switching status reporting is enabled
1 = Port power switching status reporting is disabled
When the TUSB8044A is in I2C mode, the TUSB8044A loads this bit
from the contents of the EEPROM.
When the TUSB8044A is in SMBUS mode, the value may be overwritten by an SMBus host.
3
2
ganged
fullPwrMgmtz
1
u1u2TimerOvr
RW
U1 U2 Timer Override. When this field is set, the TUSB8044A will
override the downstream ports U1/U2 timeout values set by USB 3.2
Host software. If software sets value in the range of 1h - FFh, the
TUSB8044A will use the value of FFh. If software sets value to 0, then
TUSB8044A will use value of 0.
0
RSVD
RO
Reserved. This field is reserved and returns 0 when read.
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8.5.8 Battery Charging Support Register
图 9. Register Offset 6h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
X
2
X
1
X
0
X
表 16. Bit Descriptions – Battery Charging Support Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only, returns 0 when read.
RW
Battery Charger Support. The bits in this field indicate whether the
downstream port implements the charging port features.
0 = The port is not enabled for battery charging support features
1 = The port is enabled for battery charging support features
Each bit corresponds directly to a downstream port, i.e. batEn0
corresponds to downstream port 1, and batEN1 corresponds to
downstream port 2.
The default value for these bits are loaded at the de-assertion of reset
with the value of PWRCTL/BATEN[3:0].
When in I2C/SMBus mode the bits in this field may be over-written by
EEPROM contents or by an SMBus host.
3:0
batEn[3:0]
8.5.9 Device Removable Configuration Register
图 10. Register Offset 7h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
X
2
X
1
X
0
X
表 17. Bit Descriptions – Device Removable Configuration Register
Bit
7
6:4
3:0
Field
Type
Description
customRmbl
RW
Custom Removable. This bit controls selection of port removable bits,
port used bits, and USB2_ONLY bits.
0 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read only and the
values are loaded from the OTP ROM
1 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read/write and can
be loaded by EEPROM or written by SMBus
This bit may be written simultaneously with rmbl[3:0].
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Removable. The bits in this field indicate whether a device attached to
downstream ports 4 through 1 are removable or permanently attached.
0 = The device attached to the port is not removable
1 = The device attached to the port is removable
Each bit corresponds directly to a downstream port n + 1, i.e. rmbl0
corresponds to downstream port 1, rmbl1 corresponds to downstream
port 2, etc.
This field is read only unless the customRmbl bit is set to 1. Otherwise
the value of this filed reflects the inverted values of the OTP ROM
non_rmb[3:0] field.
rmbl[3:0]
8.5.10 Port Used Configuration Register
图 11. Register Offset 8h
Bit No.
Reset State
32
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
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表 18. Bit Descriptions – Port Used Configuration Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only.
RO/RW
Used. The bits in this field indicate whether a port is enabled.
0 = The port is not used or disabled
1 = The port is used or enabled
Each bit corresponds directly to a downstream port, i.e. used0
corresponds to downstream port 1, used1 corresponds to downstream
port 2, etc. This field is read only unless the customRmbl bit is set to 1.
When the corresponding USB2_ONLY bit is set, the USB2 port will be
used and enabled regardless of the bit programmed into this field.
3:0
used[3:0]
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8.5.11 Device Configuration Register 2
图 12. Register Offset Ah
Bit No.
Reset State
7
0
6
0
5
X
4
0
3
0
2
0
1
0
0
0
表 19. Bit Descriptions – Device Configuration Register 2
Bit
7
6
5
4
3:2
34
Field
Type
Description
Reserved
RO
Reserved. Read-only, returns 0 when read.
RW
Custom Battery Charging Feature Enable. This bit controls the ability
to write to the battery charging feature configuration controls.
0 = The HiCurAcpModeEn is read only and the values are loaded from
the OTP ROM.
1 = The HiCurAcpModeEn bit is read/write and can be loaded by
EEPROM or written by SMBus.
This bit may be written simultaneously with HiCurAcpModeEn.
RW
Power enable polarity. This bit is loaded at the de-assertion of reset
with the value of the PWRCTL_POL pin.
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
When the TUSB8044A is in I2C mode, the TUSB8044A loads this bit
from the contents of the EEPROM.
When the TUSB8044A is in SMBUS mode, the value may be overwritten by an SMBus host.
HiCurAcpModeEn
RO/RW
High-current ACP mode enable. This bit enables the high-current tablet
charging mode when the automatic battery charging mode is enabled
for downstream ports.
0 = High current divider mode disabled . High current is ACP2(default)
1 = High current divider mode enabled. High current mode is ACP3
This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the
OTP ROM HiCurAcpModeEn bit.
Reserved
RW
Reserved. These registers are unused and will return whatever value
was written.
customBCfeatures
pwrctlPol
1
autoModeEnz
RW
Automatic Mode Enable.
The automatic mode only applies to downstream ports with battery
charging enabled when the upstream port is not connected. Under
these conditions:
0 = Automatic mode battery charging features are enabled.
1 = Automatic mode is disabled; only Battery Charging DCP and CDP
mode is supported.
NOTE: When the upstream port is connected, Battery Charging CDP
mode will be supported on all ports that are enabled for battery
charging support regardless of the value of this bit.
0
RSVD
RO
Reserved. Read only, returns 0 when read.
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8.5.12 USB 2.0 Port Polarity Control Register
图 13. Register Offset Bh
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 20. Bit Descriptions – USB 2.0 Port Polarity Control Register
Bit
7
6:5
4
3
2
1
0
Field
Type
Description
customPolarity
RW
Custom USB 2.0 Polarity. This bit controls the ability to write the
p[4:0]_usb2pol bits.
0 = The p[4:0]_usb2pol bits are read only and the values are loaded
from the OTP ROM.
1 = The p[4:0]_usb2pol bits are read/write and can be loaded by
EEPROM or written by SMBus.
This bit may be written simultaneously with the p[4:0]_usb2pol bits
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Downstream Port 4 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p4_usb2pol bit.
RO/RW
Downstream Port 3 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p3_usb2pol bit.
RO/RW
Downstream Port 2 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p2_usb2pol bit.
RORW
Downstream Port 1 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p1_usb2pol bit.
RO/RW
Upstream Port DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p0_usb2pol bit.
p4_usb2pol
p3_usb2pol
p2_usb2pol
p1_usb2pol
p0_usb2pol
8.5.13 Billboard AlternateModeVdo
图 14. Register Offset 0Ch - 0Fh (Billboard AlternateModeVdo)
Bit No.
Reset State
7
X
6
X
版权 © 2019, Texas Instruments Incorporated
5
X
4
X
3
X
2
X
1
X
0
X
35
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www.ti.com.cn
表 21. Bit Descriptions – Billboard AlternateModeVdo
Bit
7:0
36
Field
AlternateModeVdo
Type
Description
W
Billboard AlternateModeVdo. This field can only be written to and can
not be read from.
Defaults to 0x00001C45.
The default can be changed using an external I2C EEPROM or
SMBus.
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
8.5.14 UUID Registers
图 15. Register Offset 10h-1Fh
Bit No.
Reset State
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
X
表 22. Bit Descriptions – UUID Byte N Register
Bit
Field
Type
Description
7:0
uuidByte[n]
RO
UUID byte N. The UUID returned in the Container ID descriptor. The
value of this register is provided by the device and is meets the UUID
requirements of Internet Engineering Task Force (IETF) RFC 4122 A
UUID URN Namespace.
8.5.15 Language ID LSB Register
图 16. Register Offset 20h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
1
表 23. Bit Descriptions – Language ID LSB Register
Bit
7:0
Field
langIdLsb
Type
Description
RO/RW
Language ID least significant byte. This register contains the value
returned in the LSB of the LANGID code in string index 0. The
TUSB8044A only supports one language ID. The default value of this
register is 09h representing the LSB of the LangID 0409h indicating
English United States.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
8.5.16 Language ID MSB Register
图 17. Register Offset 21h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 24. Bit Descriptions – Language ID MSB Register
Bit
7:0
Field
langIdMsb
版权 © 2019, Texas Instruments Incorporated
Type
Description
RO/RW
Language ID most significant byte. This register contains the value
returned in the MSB of the LANGID code in string index 0. The
TUSB8044A only supports one language ID. The default value of this
register is 04h representing the MSB of the LangID 0409h indicating
English United States.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
37
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8.5.17 Serial Number String Length Register
图 18. Register Offset 22h
Bit No.
Reset State
7
0
6
0
5
0
4
1
3
1
2
0
1
0
0
0
表 25. Bit Descriptions – Serial Number String Length Register
Bit
Field
Type
Description
7:6
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Serial number string length. The string length in bytes for the serial
number string. The default value is 18h indicating that a 24 byte serial
number string is supported. The maximum string length is 32 bytes.
When customSernum is 1, this field may be over-written by the
contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a serial number string of
serNumbStringLen bytes is returned at string index 1 from the data
contained in the Serial Number String registers.
5:0
serNumStringLen
8.5.18 Manufacturer String Length Register
图 19. Register Offset 23h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 26. Bit Descriptions – Manufacturer String Length Register
Bit
Field
Type
Description
7
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Manufacturer string length. The string length in bytes for the
manufacturer string. The default value is 0, indicating that a
manufacturer string is not provided. The maximum string length is 64
bytes.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
When the field is non-zero, a manufacturer string of mfgStringLen
bytes is returned at string index 3 from the data contained in the
Manufacturer String registers.
6:0
mfgStringLen
8.5.19 Product String Length Register
图 20. Register Offset 24h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 27. Bit Descriptions – Product String Length Register
Bit
Field
Type
Description
7
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Product string length. The string length in bytes for the product string.
The default value is 0, indicating that a product string is not provided.
The maximum string length is 64 bytes.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
When the field is non-zero, a product string of prodStringLen bytes is
returned at string index 3 from the data contained in the Product String
registers.
6:0
38
prodStringLen
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TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
8.5.20 Device Configuration Register 3
图 21. Register Offset 25h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 28. Bit Descriptions – Device Configuration Register 3
Bit
Field
Type
Description
7:6
RSVD
RO
Reserved. Read only, returns 0 when read.
bcdUSB30
RW
This field when set will force SS hub to report bcdUSB = 3.0 instead of
3.2.
5
4
USB2.0_only
RW
USB 2.0 hub reports as 2.0 only. This bit disables the USB 2.0 hub
from reporting 5Gbps support in the wSpeedsSupported field of the
USB SS BOS SS device capability descriptor. This bit will also disable
the USB3.0 hub.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is enabled.
3
USB2_DFP_UNCONF
RW
This field when set enables USB 2.0-defined Unconfigured state on
DFPs.
R/W
I2C 100kHz. This bit controls the clock rate of the I2C master for both
USB to I2C requests . The EEPROM reads will occur at 400K unless
eFuse is used to set the rate to 100k.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is enabled.
R/W
Disable Galaxy compatible modes. When this field is high, Galaxy
charging compatible mode will not be included in AUTOMODE charger
sequence.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is disabled.
R/W
Enable all divider battery charging modes. When automode is enabled
and this bit is set, any DS port enabled for battery charging will attempt
all divider battery charging modes before DCP, starting with the
highest current option.
The bit is writable, but the value read back is the Boolean OR of this
bit and the corresponding eFuse control.
If either bit is set, eFuse or this register, this feature is enabled.
2
1
0
I2C_100k
Galaxy_Enz
FullAutoEn
8.5.21 USB 2.0 Only Port Register
图 22. Register Offset 26h
Bit No.
Reset State
7
0
6
0
5
1
4
1
3
0
2
0
1
0
0
0
表 29. Bit Descriptions – USB 2.0 Only Port Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only.
RO/RW
USB 2.0 Only Ports. The bits in this field primarily indicate whether a
port is enabled only for USB 2.0 operation. This field is read-only
unless customRmbl bit is set. Also, these bits will override the
corresponding USED bit.
A value of 0 indicates the hub port is enabled for both USB 3.2 and
USB 2.0.
A value of 1 indicates the hub port is enabled only for USB 2.0
operation.
3:0
USB2_ONLY[3:0]
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39
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8.5.22 Billboard SVID LSB
图 23. Register Offset 27h (Billboard SVID LSB)
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 30. Bit Descriptions – Billboard SVID LSB
Bit
7:0
Field
SVID_LSB
Type
Description
RW
SVID. This field is the LSB of the 16-bit SVID. When Billboard SVID
LSB and MSB are all zero, the ROM default is returned for descriptor
request by the BB device, but this register still reads back zero. This
field's default can be changed using an external I2C EEPROM or
SMBus.
8.5.23 Billboard SVID MSB
图 24. Register Offset 28h (Billboard SVID MSB)
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 31. Bit Descriptions – Billboard SVID MSB
Bit
7:0
40
Field
SVID_MSB
Type
Description
RW
SVID. This field is the MSB of the 16-bit SVID. When Billboard SVID
LSB and MSB are all zero, the ROM default is returned for descriptor
request by the BB device, but this register still reads back zero. This
field's default can be changed using an external I2C EEPROM or
SMBus.
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TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
8.5.24 Billboard PID LSB
图 25. Register Offset 29h (Billboard PID LSB)
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 32. Bit Descriptions – Billboard PID LSB
Bit
7:0
Field
BBPID_LSB
Type
Description
RW
Billboard PID LSB. This field represents the LSB of the 16-bit PID.
When Billboard PID LSB and MSB are all zero, ROM default is
selected for USB descriptor requests. This register however will
continue to read back zero. This field's default can be changed using
an external I2C EEPROM or SMBus
8.5.25 Billboard PID MSB
图 26. Register Offset 2Ah (Billboard PID MSB)
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 33. Bit Descriptions – Billboard PID MSB
Bit
7:0
Field
BBPID_LSB
版权 © 2019, Texas Instruments Incorporated
Type
Description
RW
Billboard PID MSB. This field represents the MSB of the 16-bit PID.
When Billboard PID LSB and MSB are all zero, ROM default is
selected for USB descriptor requests. This register however will
continue to read back zero. This field's default can be changed using
an external I2C EEPROM or SMBus.
41
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8.5.26 Billboard Configuration
图 27. Register Offset 2Bh (Billboard Configuration)
Bit No.
Reset State
7
1
6
0
5
0
4
0
3
X
2
X
1
0
0
0
表 34. Bit Descriptions – Billboard Configuration.
Bit
7:4
3:2
1
0
42
Field
VCONN_PWR
bbConfigured[1:0]
bAdditionalFailureInfo
BillboardEN
Type
Description
RW
VCONN power. This field is used when SMBus mode is selected.
When I2C mode is selected, this field is read-only and will always
return 1000b. The TUSB8044A will use value programmed into this
register to update the VCONN Power field in the Billboard Capability
Descriptor.
0000b: 1 Watt
0001b: 1.5 Watts
0010b: 2 Watts
0011b: 3 Watts
0100b: 4 Watts
0101b: 5 Watts
0110b: 6 Watts
0111b: Reserved.
1XXXb: The adapter does NOT require any Vconn power.
RW
bmConfigured[1:0]. This field is used when SMBus mode is selected.
Controls the bmConfigured[1:0] fields in the Billboard Capability
Descriptor. When I2C mode is selected, then bmConfigured[1:0] fields
are read-only and values are determined by BBbmConfigured[1:0]
pins.
00b: Unspecified Error
01b: Alternate Mode Configuration Not attempted.
10b: Alternate Mode configured attempted but unsuccessful.
11b: Alternate Mode configured successfully.
RW
bAdditionalFailureInfo. This field is used when SMBus mode is
selected. This field is ignored if VCONN_PWR[3] is set. The value
programmed into this field will be presented in the
bAdditionalFailureInfo field in the Billboard Capability Descriptor.
When in I2C mode, this field is read-only and defaults to 0.
RW
Billboard Enable. This field is used when SMBus mode is selected.
When I2C mode is selected, this field is read-only and Billboard
connected state is determined by BBEN pin.
0b: Billboard not connected.
1b: Billboard connected.
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TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
8.5.27 Billboard String1 Length
图 28. Register Offset 2Ch (Billboard String1 Length)
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 35. Bit Descriptions – Billboard String1 Length.
Bit
Field
Type
Description
Billboard String1Len. This field indicates the length in number of
UNICODE characters of the Billboard string1. This is not the length of
the string descriptor. BBString1Len size can not exceed 120
characters (240 bytes).
7:0
BBString1Len
RW
The bLength field of the Additional Info URL string descriptor is 2 + (2 *
BBString1Len).
This field defaults to 0x00 and reports the default string value shown in
Billboard String1_2 but can be changed using an external I2C
EEPROM or SMBus.
8.5.28 Billboard String2 Length
图 29. Register Offset 2Dh (Billboard String2 Length)
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 36. Bit Descriptions – Billboard String2 Length.
Bit
Field
Type
Description
Billboard String2Len. This field indicates the length in number of
UNICODE characters of the Billboard string2. BBString2Len size can
not exceed 120 characters (240 bytes).
7:0
BBString2Len
RW
The bLength field of the Alternate Mode string descriptor is 2 + (2 *
BBString2Len).
This field defaults to 0x00 and reports the default string value shown in
Billboard String1_2 but can be changed using an external I2C
EEPROM or SMBus.
8.5.29 Serial Number String Registers
图 30. Register Offset 30h-4Fh
Bit No.
Reset State
7
X
6
X
5
x
4
x
3
x
2
x
1
x
0
x
表 37. Bit Descriptions – Serial Number Registers
Bit
Field
Type
Description
7:0
serialNumber[n]
RO/RW
Serial Number byte N. The serial number returned in the Serial
Number string descriptor at string index 1. The default value of these
registers is assigned by TI. When customSernum is 1, these registers
may be over-written by EEPROM contents or by an SMBus host.
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8.5.30 Manufacturer String Registers
图 31. Register Offset 50h-8Fh
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 38. Bit Descriptions – Manufacturer String Registers
Bit
7:0
Field
mfgStringByte[n]
Type
Description
RW
Manufacturer string byte N. These registers provide the string values
returned for string index 3 when mfgStringLen is greater than 0. The
number of bytes returned in the string is equal to mfgStringLen.
The programmed data should be in UNICODE UTF-16LE encodings
as defined by The Unicode Standard, Worldwide Character Encoding,
Version 5.0.
8.5.31 Product String Registers
图 32. Register Offset 90h-CFh
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 39. Bit Descriptions – Product String Byte N Register
Bit
7:0
44
Field
prodStringByte[n]
Type
Description
RO/RW
Product string byte N. These registers provide the string values
returned for string index 2 when prodStringLen is greater than 0. The
number of bytes returned in the string is equal to prodStringLen.
The programmed data should be in UNICODE UTF-16LE encodings
as defined by The Unicode Standard, Worldwide Character Encoding,
Version 5.0.
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
8.5.32 Additional Feature Configuration Register
图 33. Register Offset F0h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 40. Bit Descriptions – Additional Feature Configuration Register
Bit
Field
Type
Description
7:5
Reserved
RW
Reserved. This field defaults to 3'b000 and must not be changed.
RW
Status output enable. This field when set enables of the Status output
signals, HS_UP, HS_SUSPEND, SS_UP, SS_SUSPEND.
0 = STS outputs are disabled.
1 = STS outputs are enabled.
This bit may be loaded by EEPROM or over-written by a SMBUS host.
4
3:1
stsOutputEn
pwronTime
RW
Power On Delay Time. When the efuse_pwronTime field is all 0s, this
field sets the delay time from the removal disable of PWRCTL to the
enable of PWRCTL when transitioning battery charging modes. For
example, when disabling the power on a transition from ACP to DCP
Mode. The nominal timing is defined as follows:
TPWRON_EN = (pwronTime x 1) x 200 ms
(1)
This field may be over-written by EEPROM contents or by an SMBus
host.
0
usb3spreadDis
版权 © 2019, Texas Instruments Incorporated
RW
USB3 Spread Spectrum Disable. This bit allows firmware to disable the
spread spectrum function of the USB3 phy PLL.
0 = Spread spectrum function is enabled
1= Spread spectrum function is disabled
This bit may be loaded by EEPROM or over-written by a SMBUS host.
45
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8.5.33 SMBus Device Status and Command Register
图 34. Register Offset F8h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
表 41. Bit Descriptions – SMBus Device Status and Command Register
Bit
Field
Type
Description
7:2
RSVD
RO
Reserved. Read only, returns 0 when read.
RSU
SMBus interface reset. This bit loads the registers back to their GRSTz
values. Note, that since this bit can only be set when in SMBus mode
the cfgActive bit is also reset to 1. When software sets this bit it must
reconfigure the registers as necessary.
This bit is set by writing a 1 and is cleared by hardware on completion
of the reset. A write of 0 has no effect.
RCU
Configuration active. This bit indicates that configuration of the
TUSB8044A is currently active. The bit is set by hardware when the
device enters the I2C or SMBus mode. The TUSB8044A shall not
connect on the upstream port while this bit is 1.
When in I2C mode, the bit is cleared by hardware when the
TUSB8044A exits the I2C mode.
When in the SMBus mode, this bit must be cleared by the SMBus host
in order to exit the configuration mode and allow the upstream port to
connect.
The bit is cleared by a writing 1. A write of 0 has no effect.
1
0
smbusRst
cfgActive
8.5.34 Billboard String1_2
图 35. Register Offset 100h - 2DFh (Billboard String1_2)
Bit No.
Reset State
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
X
表 42. Bit Descriptions – Billboard String1_2
Bit
7:0
46
Field
BBString12
Type
Description
W
Billboard String1 and String2. This field can only be written to and can
not be read from. String1 starts at address 0x100. String2 starts at
address 0x1F0.
String 1 defaults http://www.displayport.org
String 2 defaults to "DisplayPort"
The default can be changed using an external I2C EEPROM or
SMBus.
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TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB8044A is a four-port USB 3.2 x1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and
high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed,
or low speed connections on the downstream port. The TUSB8044A can be used in any application that needs
additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By
using the TUSB8044A, the notebook can increase the downstream port count to five.
9.2 Typical Application
9.2.1 Discrete USB Hub Product
A common application for the TUSB8044A is as a self powered standalone USB Type-C docking product. The
product is powered by an external 5V DC Power adapter. In this application, using a USB Type-C captive cable
the TUSB8044A upstream port is plugged into a USB Host controller. The downstream ports of the TUSB8044A
are exposed to users for connecting USB hard drives, cameras, flash drives, and so forth. There is also a
DisplayPort receptacle for connected an external DisplayPort monitor.
TUSB8044A
图 36. Discrete USB Hub Product
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Typical Application (接
接下页)
9.2.1.1 Design Requirements
表 43. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDD Supply
1.1 V
VDD33 Supply
3.3 V
Upstream Port USB Support (SS, HS, FS)
SS, HS, FS
Downstream Port 1 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Downstream Port 2 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Downstream Port 3 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Downstream Port 4 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Number of Removable external exposed Downstream Ports
4
Number of Non-Removable external exposed Downstream Ports
0
Full Power Management of Downstream Ports
Yes. (FULLPWRMGMTZ = 0)
Individual Control of Downstream Port Power Switch
Yes. (GANGED = 0)
Power Switch Enable Polarity
Active High. (PWRCTL_POL = 1)
Battery Charge Support for Downstream Port 1
Yes
Battery Charge Support for Downstream Port 2
Yes
Battery Charge Support for Downstream Port 3
Yes
Battery Charge Support for Downstream Port 4
Yes
I2C EEPROM Support
Yes
24MHz Clock Source
Crystal
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Upstream Port Implementation
The upstream of the TUSB8044A is connected to a USB Type-C captive cable. The system VBUS signal from
the USB3 Type C plug is fed through a voltage divider. The purpose of the voltage divider is to make sure the
system VBUS level meets TUSB8044A USB_VBUS input requirements. The voltage divider in this particular
implementation will support up to 11.4V VBUS. If VBUS needs to be greater, then PD controller will need to
directly control TUSB8044A USB_VBUS input. The USB-C plug has two pairs of USB 3.2 differential pairs
(RX1/TX1 and RX2/TX2). In this particular example, one pair of super speed signals (RX2 and TX2) from Type-C
plug is connected to the DP Hub/Retimer/Redriver. The other pair of super speed signals (RX1 and TX2) is
routed to the TUSB8044A. The CC1 and VCONN signals from the Type-C plug is connected to the USB PD
controller.
UFP_VBUS
UFP_VBUS
A9
A4
8044_UTX1P A2
8044_UTX1M A3
UFP_CC1
UFP_CC1 A5
8044_DP A6
8044_DM A7
A8
UFP_SBU1
DP1P
DP1M
DP1P
DP1M
A11
A10
A1
A12
S1
S2
VBUS
VBUS
SSTXp1
SSTXn1
VBUS
VBUS
SSRXp1
SSRXn1
CC1
CC2
B4
B9
UFP_VBUS
B11 8044_URX1P
B10 8044_URX1M
B5
90.9K
Dp1
Dn1
SBU1
SSRXp2
SSRXn2
SBU2
SSTXp2
SSTXn2
GND
GND
SHIELD
SHIELD
GND
GND
SHIELD
SHIELD
B8
B2 DP0P
B3 DP0M
DP0P
DP0M
48
R2
10k
1%
8044_DP
8044_DM
8044_UTX1P C2 0.1uF
UFP_SBU2
B1
B12
U1A
1%
R1
VCONN
53
54
55
56
8044_UTX1M C3 0.1uF
GND
8044_URX1P
8044_URX1M
C1
1uF
58
59
USB_VBUS
USB_DP_UP
USB_DM_UP
USB_SSTXP_UP
USB_SSTXM_UP
USB_SSRXP_UP
USB_SSRXM_UP
TUSB8044ARGCR
S3
S4
Type-C Plug
GND
GND
图 37. Upstream Port Implementation
48
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TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
9.2.1.2.2 Downstream Port 1 Implementation
The downstream port 1 of the TUSB8044A is connected to a USB Type-C receptacle. With BATEN1 pin pulled
up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on
BATEN1 should be uninstalled. A 1:2 MUX passive MUX is used to route the hub downstream port's super
speed signals to the appropriate location on the USB Type-C receptacle. The MUX orientation is controlled by
the PD controller through the SEL signal. A example 1:2 passive MUX that could be used is the Texas
Instrument's HD3SS3212.
DFP_VBUS
DFP_VBUS
3P3V
A4
A9
U2
U1B
OVERCUR1
PWRCTL1/BATEN1
USB_SSRXM_DN1
USB_SSRXP_DN1
USB_SSTXM_DN1
USB_SSTXP_DN1
USB_DM_DN1
USB_DP_DN1
46
36
R3
4.7k
C4 0.1uF DFP_TX1P
OVERCUR1z
PWRCT1_BATEN1
DFP_DM
DFP_DP
A7
A6
DFP_TX1M
DFP_TX1P
A3
A2
C5 0.1uF DFP_TX1N
7
6
DFP_RXM
DFP_RXP
DFP_TXP
DFP_TXM
4
3
DFP_TXM
DFP_TXP
DFP_RXP
DFP_RXM
2
1
DFP_DM
DFP_DP
DFP_RX1P
DFP_RX1M
SS MUX
DFP_RX2M A10
DFP_RX2P A11
C6 0.1uF DFP_TX2M
C7 0.1uF DFP_TX2P
DFP_CC1
DFP_CC1
DFP_RX2P
DFP_RX2M
TUSB8044ARGCR
VBUS
VBUS
DD+
DD+
TX1TX1+
TX2TX2+
RX2RX2+
RX1RX1-
A5
CC1
CC2
A8
SBU1
A1
A12
SS_SEL_DP
VBUS
VBUS
SS MUX
S1
S2
SBU2
GND
GND
GND
GND
Shield
Shield
Shield
Shield
B4
B9
B7
B6
DFP_DM
DFP_DP
B3
B2
DFP_TX2M
DFP_TX2P
DFP_RX1M
DFP_RX1P
B10
B11
B5
DFP_CC2
DFP_CC2
B8
B1
B12
C8
1uF
S4
S3
Type-C receptacle Port 1
GND
GND
图 38. Downstream Port 1 Implementation
9.2.1.2.3 Downstream Port 2 Implementation
The downstream port 2 of the TUSB8044A is connected to a USB3 Type A connector. With BATEN2 pin pulled
up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on
BATEN2 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
FB1
DN2_VBUS
220 ohm
3P3V
C12
0.1uF
1
R3
4.7k
U1C
OVERCUR2
PWRCTL2/BATEN2
USB_SSRXM_DN2
USB_SSRXP_DN2
USB_SSTXM_DN2
USB_SSTXP_DN2
USB_DM_DN2
USB_DP_DN2
47
35
GND
OVERCUR2z
PWRCT2_BATEN2
15 USB_RXM_DN2
14 USB_RXP_DN2
12 USB_TXM_DN2
11 USB_TXP_DN2
10 USB_DM_DN2
9 USB_DP_DN2
3
2
USB_RXP_DN2
USB_RXM_DN2
C13
6
5
USB_TXP_DN2
9
8
0.1uF
C14
USB_TXM_DN2
7
0.1uF
4
TUSB8044ARGCR
R4
1M
C15
C16
0.001uF 0.1uF
S1
S2
S3
S4
VBUS
D+
DSSRX+
SSRXSSTX+
SSTXGND_DRAIN
GND
SHIELD
SHIELD
SHIELD
SHIELD
TypeA_receptacle_Port2
GND
GND
图 39. Downstream Port 2 Implementation
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49
TUSB8044A
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www.ti.com.cn
9.2.1.2.4 Downstream Port 3 Implementation
The downstream port3 of the TUSB8044A is connected to a USB3 Type A connector. With BATEN3 pin pulled
up, Battery Charge support is enabled for Port 3. If Battery Charge support is not needed, then pull-up resistor on
BATEN3 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
FB2
DN3_VBUS
220 ohm
C17
0.1uF
3P3V
1
R5
4.7K
U1D
OVERCUR3
PWRCTL3/BATEN3
USB_SSRXM_DN3
USB_SSRXP_DN3
USB_SSTXM_DN3
USB_SSTXP_DN3
USB_DM_DN3
USB_DP_DN3
44
33
GND
OVERCUR3z
PWRCT3_BATEN3
3
2
USB_RXP_DN3
USB_RXM_DN3
C18
6
5
USB_TXP_DN3
23 USB_RXM_DN3
22 USB_RXP_DN3
0.1uF
C19
20 USB_TXM_DN3
19 USB_TXP_DN3
USB_TXM_DN3
0.1uF
R6
1M
TUSB8044ARGCR
C20
C21
0.001uF 0.1uF
D+
DSSRX+
SSRX-
9
8
SSTX+
SSTX-
7
GND_DRAIN
4
18 USB_DM_DN3
17 USB_DP_DN3
VBUS
S1
S2
S3
S4
GND
SHIELD
SHIELD
SHIELD
SHIELD
TypeA_receptacle_Port3
GND
GND
图 40. Downstream Port 3 Implementation
9.2.1.2.5 Downstream Port 4 Implementation
The downstream port 4 of the TUSB8044A is connected to a USB3 Type A connector. With BATEN4 pin pulled
up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then pull-up resistor on
BATEN4 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
FB3
DN4_VBUS
220 ohm
C22
0.1uF
3P3V
1
GND
U1E
OVERCUR4
PWRCTL4/BATEN4
USB_SSRXM_DN4
USB_SSRXP_DN4
USB_SSTXM_DN4
USB_SSTXP_DN4
USB_DM_DN4
USB_DP_DN4
TUSB8044ARGCR
3
2
R7
4.7k
43
32
OVERCUR4z
PWRCT4_BATEN4
USB_RXP_DN4
USB_RXM_DN4
C23
0.1uF
C24
30 USB_RXM_DN4
29 USB_RXP_DN4
USB_TXM_DN4
27 USB_TXM_DN4
26 USB_TXP_DN4
6
5
USB_TXP_DN4
0.1uF
R8
1M
C25
C26
0.001uF 0.1uF
D+
DSSRX+
SSRX-
9
8
SSTX+
SSTX-
7
GND_DRAIN
4
25 USB_DM_DN4
24 USB_DP_DN4
VBUS
S1
S2
S3
S4
GND
SHIELD
SHIELD
SHIELD
SHIELD
TypeA_receptacle_Port4
GND
GND
图 41. Downstream Port 4 Implementation
50
版权 © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
9.2.1.2.6 VBUS Power Switch Implementation
This particular example uses the Texas Instruments TPS2561 Dual Channel Precision Adjustable CurrentLimited power switch. For details on this power switch or other power switches available from Texas Instruments,
refer to the Texas Instruments website.
3P3V
5V
R9
10k
C27
0.1uF
C28
4.7uF
C29
0.1uF
DN2_VBUS
DN3_VBUS
U3
2
3
IN
IN
10
6
OVERCUR2z
OVERCUR3z
GND
R10
10k
OUT1
OUT2
FAULT1
FAULT2
4
5
PWRCT2_BATEN2
PWRCT3_BATEN3
9
8
EN1
EN2
C31
0.1uF
7
ILIM
R11
25.5k
1
11
GND
PAD
C32
150µF
C33
150µF
C30
0.1uF
TPS2561DRCR
5V
3P3V
GND
C34
0.1uF
C35
4.7uF
C36
0.1uF
R12
10k
DN4_VBUS
U4
2
3
5
OVERCUR4z
GND
4
PWRCT4_BATEN4
IN
IN
OUT
OUT
OUT
6
7
8
FLT
EN
PAD
GND
C37
0.1uF
9
1
C38
150µF
TPS2001CDGN
GND
图 42. VBUS Power Switch Implementation
9.2.1.2.7 PD Controller and EEPROM Implementation
In this specfic application, PD controller monitors and controls the CC line and the VBUS on both the upstream
Type-C port and the downstream Type-C port. It also utilizes BBconfigure0 and BBconfigure1 to set up the
billboard function of TUSB8044 and custom billboard information is stored in the EEPROM. Moreover, the
controller uses the GPIOs to control the super speed MUX.
The TUSB8044 loads the 256 bytes plus the billboard strings from an external EEPROM. The billboard string
starts at address 0x100 and ends at address 0x2DF for a total of 480 bytes. A minimum of 5.888Kbit EEPROM is
recommended. EEPROMs do not come in this size so an 8Kbit EEPROM (10-bit addressing) is recommended.
For example, an Atmel AT24C08A could be used.
图 43. PD Controller and EEPROM Implementation
U5
UFP_VBUS
DFP_VBUS
OVERCUR1z
UFP_CC1
VCONN
DFP_CC1
DFP_CC2
1
2
3
4
5
6
7
3P3V
8
BBEN
9
BBbmConfigured0
10
BBbmConfigured1
VBUS1
GPIO
VBUS2
GPIO
GPIO
GPIO
C1_CC1
GPIO
11
C1_CC2
GPIO
12
C2_CC1
SDA
C2_CC2
SCL
HPD
SS_SEL_DP
R15
4.7k
R16
4.7k
U1F
U6
I2C_SDA
I2C_SCL
37
38
SDA/SMBDAT
SCL/SMBCLK
I2C_SCL
PWRCT1_BATEN1
13
I2C_SCL
14
I2C_SDA
15
DP_hub_HPD
BBbmConfigured0 40
42
BBEN
BBbmConfigured1 45
BBbmConfigured0/FULLAUTO/SS_UP
BBEN/HS_UP
BBbmConfigu red1/AUTOEN/HS_SUSPEND
I2C_SDA
EEPROM
TUSB8044ARGCR
PD controller
图 44. PD Controller and EEPROM Implementation
版权 © 2019, Texas Instruments Incorporated
51
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
9.2.1.2.8 DisplayPort Implementation
The DisplayPort interface can be implemented with a DisplayPort MST Hub or a DisplayPort redriver/retimer. The
main channels and the AUX channels are connected to the DP receptacle after the HUB.
U7
DP0P
C39
0.1µF
DP0M
C40
0.1µF
DP1P
C41
0.1µF
DP1M
C42
0.1µF
U?
Driver
Driver
C47
0.1µF DP_hub_DP0P
C48
0.1µF DP_hub_DP0M
C49
0.1µF DP_hub_DP1P
C50
0.1µF DP_hub_DP1M
DP_hub_DP1P 4
DP_hub_DP1M 6
DP_hub_DP0P 1
DP_hub_DP0M 3
10
12
For HDMI
Driver
3P3V
7
9
3P3V
R17
1M
FOR DVI
Driver
UFP_SBU1
C43
0.2µF AUXSRC_P
AUX_P
C45
0.2µF
UFP_SBU2
C44
0.2µF AUXSRC_M
AUX_M
C46
0.2µF
3P3V
R18
1M
DP_hub_HPD
HPDIN
ML1_P
ML1_N
ML0_P
ML0_N
ML3_P
ML3_N
ML2_P
ML2_N
20
DP_PWR
15
17
AUX_P
AUX_N
18
CONFIG1
CONFIG2
RTN
GND
GND
GND
GND
GND
GND
GND
GND
GND
13
14
R21
R22
1M
5M
19
2
5
8
11
16
21
22
23
24
HPD
DisplayPort Receptacle
HPDIN
GND
R19
100k
DP HUB/ Redriver
R20
100k
GND
GND
图 45. DisplayPort Implementation
9.2.1.2.9 Clock, Reset, and Misc
The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2,
PWRCTL3, and PWRCTL4) for a USB VBUS power switch. SMBUSz pin is also left unconnected which will
select I2C mode. Both PWRCTL_POL and SMBUSz pins have internal pull-ups. The 1 µF capacitor on the
GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the
supply ramp of the two supplies the capacitor size may have to be adjusted.
3P3V
U1G
R21
4.7k DNI
R22
39
41
4.7k DNI
R20
1
TEST
50
GRST
61
62
Y1
64
XO
XI
USB_R1
TUSB8044ARGCR
24M Hz
C60
8pF
PWRCTL_POL
49
1M
2
SMBUS/SS_SUSPEND
C61
8pF
C62
1uF
R24
4.7k
R25
9.53k
1%
GND
GND
图 46. Clock, Reset, and Misc
52
版权 © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
9.2.1.2.10 TUSB8044A Power Implementation
BOARD_3P3V
FB5
220 ohm
BOARD_1P1V
3P3V
U1H
5
8
13
21
28
31
51
57
FB4
220 ohm
C63
0.1µF
C64
0.1µF
C65
0.1µF
1P1V
C66
0.1µF
C67
0.1µF
C68
0.1µF
C69
0.1µF
C70
10µF
60
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
VDD33
VDD33
VDD33
VDD33
16
34
52
63
VSS
65
C71
0.1µF
C72
0.1µF
C73
0.1µF
C74
0.1µF
C75
10µF
GND
TUSB8044ARGCR
GND
图 47. TUSB8044A Power Implementation
版权 © 2019, Texas Instruments Incorporated
53
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
9.2.1.3 Application Curves
54
图 48. Upstream Port
图 49. Downstream Port 1
图 50. Downstream Port 2
图 51. Downstream Port 3
图 52. Downstream Port 4
图 53. High-Speed Upstream Port
版权 © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
图 54. High-Speed Downstream Port 1
图 55. High-Speed Downstream Port 2
图 56. High-Speed Downstream Port 3
图 57. High-Speed Downstream Port 4
版权 © 2019, Texas Instruments Incorporated
55
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
10 Power Supply Recommendations
10.1 TUSB8044A Power Supply
VDD should be implemented as a single power plane, as should VDD33.
• The VDD pins of the TUSB8044A supply 1.1 V (nominal) power to the core of the TUSB8044A. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
• The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due
to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted
to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.
• The VDD33 pins of the TUSB8044A supply 3.3 V power rail to the I/O of the TUSB8044A. This power rail can
be isolated from all other power rails by a ferrite bead to reduce noise.
• All power rails require a 10 µF capacitor or 1 µF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as
close to the TUSB8044A power pins as possible with an optimal grouping of two of differing values per pin.
10.2 Downstream Port Power
•
•
•
The downstream port power, VBUS, must be supplied by a source capable of supplying 5V and up to 900 mA
per port. Downstream port power switches can be controlled by the TUSB8044A signals. It is also possible to
leave the downstream port power always enabled.
A large bulk low-ESR capacitor of 22 µF or larger is required on each downstream port’s VBUS to limit in-rush
current.
The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both
ESD and EMI reasons. A 0.1µF capacitor on the USB connector side of the ferrite provides a low impedance
path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.
10.3 Ground
It is recommended that only one board ground plane be used in the design. This provides the best image plane
for signal traces running above the plane. The thermal pad of the TUSB8044A and any of the voltage regulators
should be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port
connectors on a different plane for EMI and ESD purposes.
56
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TUSB8044A
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ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
11 Layout
11.1 Layout Guidelines
11.1.1 Placement
1. 9.53K +/-1% resistor connected to pin USB_R1 should be placed as close as possible to the TUSB8044A.
2. A 0.1 µF should be placed as close as possible on each VDD and VDD33 power pin.
3. The 100 nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (Type
A, Type B, and so forth).
4. The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB
connector.
5. If a crystal is used, it must be placed as close as possible to the TUSB8044A XI and XO pins.
6. Place voltage regulators as far away as possible from the TUSB8044A, the crystal, and the differential pairs.
7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to
the voltage regulators.
11.1.2 Package Specific
1. The TUSB8044A package has a 0.5-mm pin pitch.
2. The TUSB8044A package has a 6.0-mm x 6.0-mm thermal pad. This thermal pad must be connected to
ground through a system of vias.
3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid any
potential issues with thermal pad layouts.
11.1.3 Differential Pairs
This section describes the layout recommendations for all the TUSB8044A differential pairs: USB_DP_XX,
USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.
1. Must be designed with a differential impedance of 90 Ω ±10%.
2. In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each
pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the
layout example will also help minimize cross talk.
3. Route all differential pairs on the same layer adjacent to a solid ground plane.
4. Do not route differential pairs over any plane split.
5. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
6. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore
minimize the impact bends have on EMI.
7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS
differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very
careful routing to assure proper signal integrity.
8. Match the etch lengths of the differential pair traces (i.e. DP and DM or SSRXP and SSRXM or SSTXP and
SSTXM). There should be less than 5 mils difference between a SS differential pair signal and its
complement. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.
9. The etch lengths of the differential pair groups do not need to match (i.e. the length of the SSRX pair to that
of the SSTX pair), but all trace lengths should be minimized.
10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB8044A device.
11. To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be
routed to SSTXM or SSRXM can be routed to SSRXP.
版权 © 2019, Texas Instruments Incorporated
57
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
Layout Guidelines (接
接下页)
12. To ease routing of the USB2 DP and DM pair, the polarity of these pins can be swapped. If this is done, the
appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4, must be set.
13. Do not place power fuses across the differential pair traces.
11.2 Layout Examples
11.2.1 Upstream Port
图 58. Example Routing of Upstream Port
58
版权 © 2019, Texas Instruments Incorporated
TUSB8044A
www.ti.com.cn
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
Layout Examples (接
接下页)
11.2.2 Downstream Port
图 59. Example Routing of Downstream Port
The remaining three downstream ports routing can be similar to the example provided.
版权 © 2019, Texas Instruments Incorporated
59
TUSB8044A
ZHCSJD2A – FEBRUARY 2019 – REVISED MARCH 2019
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
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Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TUSB8044AIRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TUSB8044A
TUSB8044AIRGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TUSB8044A
TUSB8044ARGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB8044A
TUSB8044ARGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB8044A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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