TVP9900PFP

TVP9900 VSB/QAM Receiver Data Manual Literature Number: SLEA064A March 2007 – Revised July 2007 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TVP9900 VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 Contents 1 Introduction......................................................................................................................... 7 1.1 1.2 2 3 Block Diagram ..................................................................................................................... 8 Terminal Assignments .......................................................................................................... 9 3.1 3.2 4 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Analog Front End ........................................................................................................... VSB/QAM Demodulator ................................................................................................... Forward Error Correction (FEC) .......................................................................................... Output Formatter ........................................................................................................... I2C Host Interface .......................................................................................................... 4.5.1 I 2C Write Operation ............................................................................................. 4.5.2 I2C Read Operation ............................................................................................. Tuner Control Interface .................................................................................................... 4.6.1 Tuner Write Operation .......................................................................................... 4.6.2 Tuner Read Operation .......................................................................................... Antenna Control Interface ................................................................................................. 4.7.1 Antenna Interrogation/Initialization ............................................................................ 4.7.2 Transmit Data to Antenna Operation ......................................................................... 4.7.3 Receive Data from Antenna Operation ....................................................................... General-Purpose Input/Output (GPIO) .................................................................................. Clock Circuits ............................................................................................................... Power-Up Sequence ....................................................................................................... Reset ......................................................................................................................... Power Down ................................................................................................................ Power-Supply Voltage Requirements ................................................................................... 12 12 12 13 14 15 16 17 18 18 19 20 21 21 21 22 22 22 23 23 High-K PCB Design Recommendations ................................................................................. 24 Host Processor I2C Register Summary .................................................................................. 25 6.1 6.2 2 Pinout .......................................................................................................................... 9 Terminal Functions ......................................................................................................... 10 Functional Description ........................................................................................................ 12 4.1 4.2 4.3 4.4 4.5 5 6 Features ....................................................................................................................... 7 Ordering Information ........................................................................................................ 7 Overview..................................................................................................................... I2C Register Definitions .................................................................................................... 6.2.1 Receiver Control Register 1 / Soft Reset ..................................................................... 6.2.2 Receiver Control Register 2 .................................................................................... 6.2.3 VSB Control Register ........................................................................................... 6.2.4 AGC Control Register ........................................................................................... 6.2.5 VSB FEC Time Counter Register 1 ........................................................................... 6.2.6 VSB FEC Time Counter Register 2 ........................................................................... 6.2.7 VSB FEC Time Counter Register 3 ........................................................................... 6.2.8 QAM FEC Time Counter Register 1 .......................................................................... 6.2.9 QAM FEC Time Counter Register 2 .......................................................................... 6.2.10 QAM FEC Time Counter Register 3 .......................................................................... 6.2.11 VSB FEC Segment Error Count Threshold Register 1 ..................................................... 6.2.12 VSB FEC Segment Error Count Threshold Register 2 ..................................................... 6.2.13 Update Status Control Register ............................................................................... 6.2.14 Receiver Status Register ....................................................................................... 6.2.15 AGC Status Register 1.......................................................................................... 6.2.16 AGC Status Register 2.......................................................................................... 6.2.17 AGC Status Register 3.......................................................................................... 6.2.18 NTSC Rejection Filter Status Register ....................................................................... Contents 25 26 27 28 28 29 29 30 30 31 31 31 32 32 32 33 33 33 34 34 Submit Documentation Feedback TVP9900 VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.19 6.2.20 6.2.21 6.2.22 6.2.23 6.2.24 6.2.25 6.2.26 6.2.27 6.2.28 6.2.29 6.2.30 6.2.31 6.2.32 6.2.33 6.2.34 6.2.35 6.2.36 6.2.37 6.2.38 6.2.39 6.2.40 6.2.41 6.2.42 6.2.43 6.2.44 6.2.45 6.2.46 6.2.47 6.2.48 6.2.49 6.2.50 6.2.51 6.2.52 6.2.53 6.2.54 6.2.55 6.2.56 6.2.57 6.2.58 6.2.59 6.2.60 6.2.61 7 Timing Recovery Status Register 1 ........................................................................... Timing Recovery Status Register 2 ........................................................................... Timing Recovery Status Register 3 ........................................................................... Timing Recovery Status Register 4 ........................................................................... Timing Recovery Status Register 5 ........................................................................... Timing Recovery Status Register 6 ........................................................................... Pilot Tracking Status Register 1 ............................................................................... Pilot Tracking Status Register 2 ............................................................................... Pilot Tracking Status Register 3 ............................................................................... Carrier Recovery Status Register 1 ........................................................................... Carrier Recovery Status Register 2 ........................................................................... Carrier Recovery Status Register 3 ........................................................................... Carrier Recovery Status Register 4 ........................................................................... Carrier Recovery Status Register 5 ........................................................................... Carrier Recovery Status Register 6 ........................................................................... FEC Status Register 1 .......................................................................................... FEC Status Register 2 .......................................................................................... FEC Status Register 3 .......................................................................................... FEC Status Register 4 .......................................................................................... GPIO Alternate Function Select Register .................................................................... GPIO Output Data Register .................................................................................... GPIO Output Enable Register ................................................................................. GPIO Input Data Register ...................................................................................... MPEG Interface Output Enable Register 1 .................................................................. MPEG Interface Output Enable Register 2 .................................................................. Tuner Control Interface – I2C Slave Device Address Register ............................................ Tuner Control Interface – Data Register 1 Through 8 ...................................................... Tuner Control Interface – Control and Status Register ..................................................... Antenna Control Interface – Control and Status Register .................................................. Antenna Control Interface – Transmit Data Register 1 ..................................................... Antenna Control Interface – Transmit Data Register 2 ..................................................... Antenna Control Interface – Receive Data Register 1...................................................... Antenna Control Interface – Receive Data Register 2...................................................... Firmware ID – ROM Version Register ........................................................................ Firmware ID – RAM Major Version Register ................................................................. Firmware ID – RAM Minor Version Register ................................................................. Device ID LSB Register ........................................................................................ Device ID MSB Register ........................................................................................ Miscellaneous Control Register................................................................................ Software Interrupt Raw Status Register ...................................................................... Software Interrupt Status Register ............................................................................ Software Interrupt Mask Register ............................................................................. Software Interrupt Clear Register ............................................................................. 34 35 35 35 35 36 36 36 37 37 37 37 38 38 38 39 39 40 40 41 41 42 43 44 45 45 46 46 47 47 48 48 48 49 49 49 50 50 50 51 52 53 54 Electrical Specifications ...................................................................................................... 55 7.1 7.2 7.3 7.4 7.5 Absolute Maximum Ratings ............................................................................................... Recommended Operating Conditions ................................................................................... DC Electrical Characteristics ............................................................................................. Analog Input Characteristics .............................................................................................. Timing Characteristics ..................................................................................................... 7.5.1 Crystal and Input Clock ......................................................................................... 7.5.2 Device Reset ..................................................................................................... 7.5.3 MPEG Interface .................................................................................................. 7.5.3.1 Parallel Mode (Data Only) ...................................................................................... Contents 55 56 56 57 58 58 58 59 59 3 TVP9900 VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5.3.2 7.5.3.3 7.5.3.4 7.5.4 Serial Mode (Data Only) ........................................................................................ Parallel Mode (Data With Redundancy) ...................................................................... Serial Mode (Data With Redundancy) ........................................................................ Host and Tuner I2C Interface .................................................................................. 60 61 62 63 8 Application Circuit .............................................................................................................. 64 4 Contents Submit Documentation Feedback TVP9900 VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 List of Figures 2-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 .......................................................................................................... 8 Parallel Transport Stream Timing Diagram (Data Only) ..................................................................... 13 Serial Transport Stream Timing Diagram (Data Only) ....................................................................... 13 Parallel Transport Stream Timing Diagram (Data + Redundancy) ......................................................... 14 Serial Transport Stream Timing Diagram (Data + Redundancy) ........................................................... 14 Tuner Control Interface System ................................................................................................. 17 Antenna Control Interface System .............................................................................................. 19 25-MHz Crystal Oscillation ....................................................................................................... 22 4-MHz Clock Input ................................................................................................................ 22 Thermal Land Size and Via Array............................................................................................... 24 Crystal or Clock Timing Waveform ............................................................................................. 58 Device Reset Signal Timing Waveforms ....................................................................................... 58 MPEG Interface – Parallel Mode (Data Only) Timing Waveforms .......................................................... 59 MPEG Interface – Serial Mode (Data Only) Timing Waveforms ............................................................ 60 MPEG Interface – Parallel Mode (Data With Redundancy) Timing Waveforms .......................................... 61 MPEG Interface – Serial Mode (Data With Redundancy) Timing Waveforms ............................................ 62 I2C SCL and SDA Timing Waveforms .......................................................................................... 63 I2C Start and Stop Conditions Timing Waveforms ............................................................................ 63 TVP9900 Block Diagram List of Figures 5 TVP9900 VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 List of Tables 3-1 Terminal Functions ................................................................................................................ 10 4-1 MPEG-2 Transport Stream Interface ........................................................................................... 13 4-2 MPEG-2 Transport Stream Output Clock Frequency 4-3 4-4 4-5 4-6 4-7 4-8 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 6 ........................................................................ I C Terminal Description ......................................................................................................... I2C Host Interface Device Write Addresses.................................................................................... I2C Host Interface Device Read Address ...................................................................................... Tuner Control Interface Registers............................................................................................... Antenna Control Interface Registers............................................................................................ Antenna Control Interface Pins .................................................................................................. I2C Host Interface Registers ..................................................................................................... Crystal and Input Clock Timing .................................................................................................. Device Reset Timing .............................................................................................................. Parallel Mode (Data Only) Timing .............................................................................................. Serial Mode (Data Only) Timing................................................................................................. Parallel Mode (Data With Redundancy) Timing ............................................................................... Serial Mode (Data With Redundancy) Timing ................................................................................. Host and Tuner I 2C Interface Timing .......................................................................................... 2 List of Tables 14 15 15 16 17 19 20 25 58 58 59 60 61 62 63 Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 1 Introduction The TVP9900 is a cost-effective digital TV (DTV) front-end IC targeted for low-cost high-volume DTV receivers. The TVP9900 is a system-on-chip (SoC) device that integrates the main functions of a DTV front-end system, including a programmable gain amplifier (PGA), A/D converter, VSB demodulator, ATSC forward error correction (FEC), QAM demodulator, and ITU-T Annex B FEC. It provides rich peripheral support including AGC control, tuner control, CEA-909 antenna control, and host I2C interface. The TVP9900 supports processing of ATSC VSB or ITU-T Annex B QAM IF inputs. 1.1 • • • • • • • • • • • • • Features ATSC 8-VSB Demodulation and FEC ITU-J.83B Compliant 64/256 QAM Demodulation and FEC Direct 44-MHz IF Sampling Eliminates Need for External Downconverter Integrated IF PGA Integrated High-Speed 10-bit A/D Converter Integrated Digital Filter Relaxes External Tuner Filters Sigma-Delta Digital-to-Analog Converter (DAC) for AGC Control Adjacent Channel Filter NTSC Co-Channel Rejection Filter All Digital Timing Recovery Pilot Tracking Loop With Lock Status Indicator Signal Decision-Directed Carrier Phase Tracking Loop Field and Segment Synchronization With Sync Status Indicator Signal 1.2 • • • • • • • • • • • • Host Interrupt for Remote Monitoring of Signal Quality SNR Monitor BER Monitor Integrated De-Interleaver RAM Parallel/Serial MPEG Output Interface With Error Packet Indicator Direct Tuner Control Interface EIA/CEA-909 Antenna Control Interface Option for 4-MHz Clock Input Driven by MOP IC in Tuner, So No Quartz Crystal Required for Demodulator External DAC and VCXO for Clock Recovery Not Required Equalizer Covers Echo Profile Required by ATSC A.74 Guideline Superior Multipath Performance Demodulating for Brazil Ensembles A Through E Power-Down Mode 80-Pin TQFP Package Ordering Information TA 0°C to 70°C (1) • PACKAGED DEVICES (1) 80-Pin TQFP PowerPAD™ Package PACKAGE OPTION TVP9900PFP Tray TVP9900PFPR Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2007, Texas Instruments Incorporated TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 2 Block Diagram ATSC FEC AIFIN_P AIFIN_N AFE Output Formatter VSB/QAM Demodulator ITU -T J.83 Annex B FEC AGCOUT DCLK BYTE_START PACCLK DATAOUT[7:0] DERROR INTREQ VBUS Tuner Interface CEA -909 Interface GPIO [7:0] GPIO Interface ROM RAM Interrupt Ctrl PLL XTALIN XTALOUT CLKIN CLKSEL CLKOUT ANTCNTLIO MCU JTAG Host Interface I2CSDA I2CSCL PWRDOWN TUNSDA TUNSCL Figure 2-1. TVP9900 Block Diagram 8 Block Diagram Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 Terminal Assignments 3.1 Pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NSUB BGREFCAP BIASRES AVDD_REF_3_3 AGND_REF AGND DGND DVDD_1_5 GPIO0/ANTCNTLIN GPIO1 GPIO2 DGND DVDD_1_5 GPIO3 GPIO4 GPIO5/SYNCOUT IOVDD_3_3 IOGND GPIO6 GPIO7/INTREQ 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TVP9900 80-Pin TQFP (Top View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DATAOUT0 DATAOUT1 DVDD_1_5 DGND DATAOUT2 DATAOUT3 DATAOUT4 IOVDD_3_3 IOGND DATAOUT5 DATAOUT6 DATAOUT7/SERDATA0 DVDD_1_5 DGND PACCLK BYTESTART IOVDD_3_3 IOGND DCLK DGND RESETZ TMSEL0 TMSEL1 DGND DVDD_1_5 TMSEL2 TMSEL3 AGCOUT ANTCNTLIO TUNSDA TUNSCL IOGND IOVDD_3_3 I2CSDA I2CSCL DGND DVDD_1_5 I2CA0 PWRDWN DERROR 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AGND AVDD_3_3 AIFIN_P AIFIN_N AVDD_3_3 AGND AVDD_1_5 AGND AGND_PLL AVDD_PLL_1_5 XTALOUT XTALREF XTALIN CLKIN DIVINSEL CLKOUT DGND DVDD_1_5 IOGND IOVDD_3_3 Submit Documentation Feedback Terminal Assignments 9 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 3.2 Terminal Functions Table 3-1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION IF Interface AIFIN_P 3 I Analog positive differential IF input AIFIN_N 4 I Analog negative differential IF input DCLK 42 O MPEG-2 data clock output BYTE_START 45 O MPEG-2 byte start signal. An active-high output signal that indicates the first byte of a transport stream data packet. PACCLK 46 O MPEG-2 interface packet framing signal. An active-high output signal that remains high for the entire length of the valid data packet. DERROR 40 O MPEG-2 interface data error. An active-high output signal that indicates an error in the data output packet. Indicates an error in the input data. This pin should be tied low if not in use. DATAOUT7/SERDATA0 49 O 1. MPEG-2 parallel data output. Bit 7 is the first bit of the transport stream. 2. MPEG-2 serial data output 50, 51, 54, 55, 56, 59, 60 O MPEG-2 parallel data output bits 6-0 Transport Stream Interface DATAOUT[6:0] Clock Signals XTALIN 13 I Crystal input. Input to the on-chip oscillator from an external crystal. The required crystal frequency is 25 MHz. This input can also be driven by an external clock source instead of a crystal. When using an external clock source, a 4-MHz or 25-MHz clock must be used. NOTE: If an external clock source is used, the input can only be used with 1.5-V signal levels. XTALOUT 11 O Crystal output. Output from the on-chip oscillator to an external crystal. XTALREF 12 I External crystal reference. This pin is used for the external crystal capacitor ground reference. CLKIN 14 I Test clock input. For normal operation, this input should be tied low. DIVINSEL 15 I PLL VCO divider default input select. This input is used to select the default VCO divider value for the PLL. If a 25-MHz crystal or clock is used for XTALIN, DIVINSEL should be driven low. If a 4-MHz clock is used for XTALIN, DIVINSEL should be driven high. CLKOUT 16 O Test clock output. For normal operation, this output is not used. Miscellaneous Signals AGCOUT 28 O AGC control delta-sigma DAC output ANTCNTLIO 29 I/O Smart antenna control interface input/output TUNSDA 30 I/O Tuner I2C serial data input/output. NOTE: The output functions as an open drain. TUNSCL 31 I/O Tuner I2C serial clock. NOTE: The output functions as an open drain. GPIO7/INTREQ 61 I/O 1. General-purpose I/O 2. Interrupt request output GPIO6 62 I/O 1. General-purpose I/O 2. Reserved GPIO5/SYNCOUT 65 I/O 1. General-purpose I/O 2. Sync output 66, 67, 70 I/O General-purpose I/O GPIO1 71 O Dedicated to smart antenna support. Outputs direction of signal on pin 29 in smart antenna 1-pin mode. 0 = Signal input from antenna to TVP9900, pin 29 1 = Signal output from TVP9900 pin 29 to antenna GPIO0/ANTCNTLIN 72 I/O 1. General-purpose I/O 2. Antenna Control Input GPIO[4:2] 10 Terminal Assignments Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 Table 3-1. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION 21 I System reset. An active-low asynchronous input that initializes the device to the default state. PWRDOWN 39 I Power down terminal. An active-high signal puts the device in a low power state. TMSEL[3:0] 22, 23, 26, 27 I Test mode select. Tie low for normal operation. I2CSDA 34 I/O Host I2C serial data input/output. NOTE: The pin functions as an open-drain output. I2CSCL 35 I/O Host I2C serial clock. NOTE: The pin functions as an open-drain output. RESETZ Host Interface 38 I Host I2C device address select. Determines address for I2C (sampled during reset). A pullup or pulldown 10-kΩ resistor is needed to program the terminal to the desired address. 0 = Address is 0xB8h 1 = Address is 0xBAh DVDD_1_5 18, 25, 37, 48, 58, 68, 73 P Digital power supply. Connect to 1.5-V digital supply. DGND 17, 24, 36, 41, 47, 57, 69, 74 P Digital power supply return. Connect to digital ground. IOVDD_3_3 20, 33, 44, 53, 64 P IO power supply. Connect to 3.3-V digital supply. IOGND 19, 32, 43, 52, 63 P IO power supply return. Connect to digital ground. AVDD_3_3 2, 5 P Analog power supply. Connect to 3.3-V analog supply. AVDD_1_5 7 P Analog power supply. Connect to 1.5-V analog supply. 1, 6, 8, 75 P Analog power supply return. Connect to analog ground. AVDD_PLL_1_5 10 P PLL power supply. Connect to 1.5-V analog supply. AGND_PLL 9 P PLL power supply return. Connect to analog ground. NSUB 80 P Die substrate. Connect to PCB ground. AVDD_REF_3_3 77 P Analog reference power supply. Connect to 3.3-V analog supply. AGND_REF 76 P Analog reference ground. Connect to analog ground. BGREFCAP 79 O Band-gap reference capacitor connection BIASRES 78 O Analog bias register. Connect through a 24-kΩ resistor to PCB ground. I2CA0 Power Supplies AGND Submit Documentation Feedback Terminal Assignments 11 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 4 Functional Description 4.1 Analog Front End The TVP9900 receiver has an analog input channel that accepts one differential or single-ended 44-MHz center frequency IF input, which are ac coupled. The receiver supports a maximum input differential voltage range of 1 Vpp with PGA setting at unity gain. The programmable gain amplifier (PGA) and the AGC circuit work together and ensure that the input signal is amplified sufficiently to ensure the proper input range for the ADC. The ADC has 10 bits of resolution. The clock input for the ADC comes from the phase-locked loop (PLL). An external downconverter is not required to use this IF direct sampling method. The analog front end and adjacent digital filter can potentially relax the requirement for external analog filters, and only one external SAW filter is required. 4.2 VSB/QAM Demodulator The VSB/QAM demodulator is designed for 8-VSB demodulation compliant with ATSC, and 64/256 QAM demodulation compliant with ITU-T J83 Annex B. The VSB/QAM demodulator in the TVP9900 is composed of the following blocks: • Automatic gain control (AGC) • Adjacent channel filter • NTSC rejection filter • Timing recovery • Pilot tracking • Matched filter • Decision feedback equalizer • Carrier recovery The all-digital demodulator architecture does not require an external downconverter, AGC control DAC, clock recovery VCXO, or carrier recovery VCXO. This architecture makes a low-cost system implementation possible. 4.3 Forward Error Correction (FEC) FEC in the TVP9000 includes the following blocks: • QAM FEC – Trellis decoder – Synchronizer – De-randomizer – De-interleaver – Reed Solomon decoder – MPEG deframer • VSB FEC – Trellis decoder – Synchronizer – De-interleaver – Reed Solomon decoder – De-randomizer The Trellis decoder is designed for help protect against short-burst interference. The VSB synchronizer performs segment and frame synchronization and outputs the synchronization signal with data. An internal RAM is shared by both VSB and QAM modes, and additional external RAM is not required. 12 Functional Description Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 4.4 Output Formatter The TVP9900 transport stream interfaces directly to the back-end IC, which provides transport stream compliance with ISO/IEC 13818-1 in parallel or serial modes. The details of the transport stream interface are shown in Table 4-1. In serial mode, DATAOUT[7] is used as the serial data output, with the MSB output first. The maximum output rate is 42.1 Mbit/s in serial mode. The polarity of DCLK, BYTE_START, DERROR, and PACCLK is programmable. Table 4-1. MPEG-2 Transport Stream Interface TERMINAL TYPE DESCRIPTION DCLK O Parallel/serial clock output DATAOUT[7:0] O Parallel/serial data output DATAOUT7 is the first bit of the transport stream in parallel mode. DATAOUT7 is the serial data output in serial mode. BYTE_START O Packet sync, indicates the start byte of a transport packet PACCLK O Packet enable, indicates the valid packet data Figure 4-1 and Figure 4-2 show the parallel and serial transport stream timing diagrams in data-only mode. In data-only mode, 188 bytes of data is transferred from the transport stream interface continuously. PACCLK is always kept high. DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes Figure 4-1. Parallel Transport Stream Timing Diagram (Data Only) DCLK 1st byte DATAOUT[7:0] 7 6 5 4 3 2 1 0 7 6 1 0 7 6 5 4 3 2 1 0 7 6 BYTE_START PACCLK Data 188 bytes Figure 4-2. Serial Transport Stream Timing Diagram (Data Only) Figure 4-3 and Figure 4-4 show the parallel and serial transport stream timing diagrams in data and redundancy mode. In data and redundancy mode, 188 bytes of data is transferred from the transport stream interface with redundant data bytes. PACCLK only becomes high when the data is valid. Redundancy data is 20 bytes in the ATSC standard and 16 bytes in ITU-T J.83 Annex B. Submit Documentation Feedback Functional Description 13 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes Parity 16 or 20 bytes Figure 4-3. Parallel Transport Stream Timing Diagram (Data + Redundancy) DCLK 1st byte DATAOUT[7:0] 7 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 5 BYTE_START PACCLK Data 188 bytes Parity 16 or 20 bytes Figure 4-4. Serial Transport Stream Timing Diagram (Data + Redundancy) Table 4-2 shows the transport stream clock frequency in each mode. Table 4-2. MPEG-2 Transport Stream Output Clock Frequency 4.5 MODE BIT RATE (Mbps) 8VSB DATA ONLY DATA + REDUNDANCY SERIAL CLOCK (MHz) PARALLEL CLOCK (MHz) SERIAL CLOCK (MHz) PARALLEL CLOCK (MHz) 19.39266 19.39266 2.42408 21.45571 2.68196 64QAM 26.97035 26.97035 3.37129 29.26570 3.65821 256QAM 38.81070 38.81070 4.85133 42.11374 5.26422 I2C Host Interface Communication with the TVP9900 receiver is via an I2C host interface. The I2C standard consists of two signals, the serial input/output data (I2CSDA) line and the input/output clock line (I2CSCL), which carry information between the devices connected to the bus. A 1-bit control signal (I2CA0) is used for slave address selection. Although an I2C system can be multi-mastered, the TVP9900 can function as a slave device only. Since I2CSDA and I2CSCL are kept open-drain at logic high output level or when the bus is not driven, the user should connect I2CSDA and I2CSCL to IOVDD_3.3 via a pullup resistor on the board. At the trailing edge of reset, the status of the I2CA0 line is sampled to determine the device address used. Table 4-3 summarizes the terminal functions of the I2C-mode host interface. Table 4-4 and Table 4-5 show the device address selection options. 14 Functional Description Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 Table 4-3. I2C Terminal Description SIGNAL TYPE DESCRIPTION I2CA0 I Slave address selection I2CSCL I/O (open drain) Input/output clock line I2CSDA I/O (open drain) Input/output data line Table 4-4. I2C Host Interface Device Write Addresses I2CA0 WRITE ADDRESS 0 B8h 1 BAh Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL, except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition. Every byte placed on the SDA must be eight bits long. The number of bytes that can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master. I 2C Write Operation 4.5.1 Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP9900 receiver by generating a start condition (S), followed by the TVP9900 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP9900 receiver, the master presents the subaddress of the register or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP9900 receiver acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P). Step 1 0 I2C Start (master) S Step 2 7 6 5 4 3 2 1 0 I2C General address (master) 1 0 1 1 1 0 X 0 Step 3 2 I C Acknowledge (slave) Step 4 I2C Write register address (master) 7 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge (slave) A Step 6 I2C Write data (master) (1) 9 A 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Step 7 (1) 9 I2C Acknowledge (slave) A Step 8 0 I2C Stop (master) P Repeat steps 6 and 7 until all data have been written. Submit Documentation Feedback Functional Description 15 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 4.5.2 I2C Read Operation The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP9900 receiver by generating a start condition (S) followed by the TVP9900 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP9900 receiver, the master presents the subaddress of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). Table 4-5. I2C Host Interface Device Read Address I2CA0 READ ADDRESS 0 B8h 1 BAh The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP9900 receiver by generating a start condition, followed by the TVP9900 I2C address (as shown below for a read operation), in MSB-first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP9900 receiver, the I2C master receives one or more bytes of data from the TVP9900 receiver. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP9900 receiver to the master, the master generates a not acknowledge, followed by a stop. Read Phase 1 Step 1 0 I2C Start (master) S Step 2 7 6 5 4 3 2 1 0 1 0 1 1 1 0 X 0 2 I C General address (master) Step 3 9 I2C Acknowledge (slave) A Step 4 I2C Write register address (master) Step 5 2 I C Acknowledge (slave) 7 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Addr 9 A Step 6 0 I2C Stop (master) P Read Phase 2 Step 7 2 I C Start (master) Step 8 7 6 5 4 3 2 1 0 I2C General address (master) 1 0 1 1 1 0 X 0 Step 9 9 I2C Acknowledge (slave) A Step 10 I2C Read data (slave) (1) 16 0 S 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Step 11 (1) 9 I2C Not Acknowledge (master) A Step 12 0 I2C Stop (master) P Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received. Functional Description Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 4.6 Tuner Control Interface The TVP9900 has an I2C-compatible two-wire serial interface that can be used by the host processor for tuner control. This dedicated tuner interface can be used by the host processor to transfer data to/from the tuner in order to isolate the tuner from the main system I2C bus. As a result, noise coupling to the tuner from host processor I2C bus transfers should be minimized. The TVP9900 tuner control interface operates as an I2C bus master and supports both 100-kbps and 400-kbps data transfer rates. The mode and transfer rate is set in the Tuner Control Interface – Control and Status Register (5Eh), bit 0. The device does not support a multi-master bus environment (bus arbitration is not supported). To transfer data to/from the tuner, the host processor first writes the transaction to a set of registers in the TVP9900 via the host processor I2C interface. Then the TVP9900 internal MCU transfers the data to/from the tuner via the tuner control interface. TUNSCL and TUNSDA must be pulled up to the 3.3-V supply (IOVDD) and not to a 5-V supply. Figure 4-5 shows the block diagram of the tuner control interface system. MCU To Tuner Tuner Control Interface TUNSDA TUNSCL Host I2C Interface SDA SCL From Host Processor Figure 4-5. Tuner Control Interface System Table 4-6 lists the I2C registers and their functions used to control the tuner interface. Table 4-6. Tuner Control Interface Registers REGISTER 55h 56h to 5Dh 5Eh F9, FB, FD, FFh FUNCTION 2 Tuner I C slave address and R/W control Data registers 1 through 8 Byte Count, Transaction Start, and I2C Mode Software Interrupt Raw Status, Status, Mask, and Clear – Transaction Error and Done Status When the TVP9900 tuner I2C interface is used, rather than controlling the tuner over the host processor I2C bus interface, two status bits are provided in the TVP9900 to indicate a transaction error or the completion of a successful transaction. The TCIERROR bit in the TVP9900 Software Interrupt Status Register (FBh) gets set as a result of a transaction error. The TCIDONE bit in the same register gets set at the end of a normal transaction; it does not get set for an abnormal transaction. The TVP9900 can be configured so that setting the TCIERROR or TCODONE status bits can assert the INTREQ output of the TVP9900; this requires the mask bits to be configured correctly in the TVP9900 Software Interrupt Mask Register (FDh). Submit Documentation Feedback Functional Description 17 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 If the host INTREQ is not used, the TCIDONE and TCIERROR interrupts should be masked and the host should poll the TCIDONE status bit to determine when the transaction is complete, and the host should poll the TCIERROR status bit to determine when an error has occurred. Tuner data transfers occur utilizing the following illustrated formats. 4.6.1 Tuner Write Operation The following steps are required to initiate a write operation to the tuner. The host processor first writes the required transaction data to a set of registers in the TVP9900 via the host processor I2C interface. Step 1 Set tuner I2C slave address (bits 7:1) and read/write control (bit 0 = 0) Register 55h Step 2 Registers 56h to 5Dh Write data bytes to be sent to tuner; 56h is first byte sent Step 3 Set byte count (bits 7:5) and I2C mode (bit 0) Set bit 2 to 1 to start transaction to tuner Register 5Eh Step 4 Register FBh Check state of bits 1:0 or INTREQ pin to verify successful transaction After the transaction has been initiated, the TVP9900 internal MCU transfers the data to the tuner via the tuner control interface. Acting as the I2C master, the TVP9900 initiates a write operation to the tuner (as shown below), by generating a start condition, followed by the tuner I2C address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900 presents the subaddress of the register, if needed, followed by one or more bytes of data, MSB first. The tuner acknowledges each byte after completion of each transfer. The TVP9900 terminates the write operation by generating a stop condition. TVP9900/Tuner Write Operation SDA 4.6.2 Start Device Address W Ack Base Address Ack Data 1 Ack ... Data N Ack Stop Tuner Read Operation The following steps are required to initiate a read operation from the tuner. The host processor first writes the required transaction data to a set of registers in the TVP9900 via the host processor I2C interface, then reads the data bytes received from the tuner stored in TVP9900 registers. Step 1 Register 55h Set tuner I2C slave address (bits 7:1) and read/write control (bit 0 = 1) Step 2 Register 5Eh Set byte count (bits 7:5) and I2C mode (bit 0) Set bit 2 to 1 to start transaction to tuner Step 3 Register FBh Check state of bits 1:0 or INTREQ pin to verify successful transaction Step 4 Registers 56h to 5Dh Read data bytes from tuner; 56h is first byte received After the transaction has been initiated, the TVP9900 internal MCU transfers the data from the tuner via the tuner control interface. The read operation consists of two phases, as shown in the following sections. The first phase is the address phase. In this phase, the TVP9900 I2C master initiates a write operation to the tuner by generating a start condition, followed by the tuner I2C address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900 presents the subaddress of the register, if needed. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition. 18 Functional Description Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 The second phase is the data phase. In this phase, the TVP9900 I2C master initiates a read operation to the tuner by generating a start condition, followed by the tuner I2C address, in MSB-first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the tuner, the TVP9900 receives one or more bytes of data from the tuner. The TVP9900 acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the tuner to the TVP9900, the TVP9900 generates a not acknowledge, followed by a stop. TVP9900/Tuner Set Start Address, Then Read Operation 4.7 SDA Start Device Address W Ack Base Address Ack Stop SDA Start Device Address R Ack Data 1 Ack ... Data N Ack Stop Antenna Control Interface The TVP9900 has an antenna control interface compliant with EIA/CEA-909. The TVP9900 receives the antenna parameters from the host processor via I2C, and sends a modulated PWM signal to the antenna. The antenna parameters include antenna direction, antenna polarization, preamplifier gain and channel number. This interface can be used to automatically optimize the signal by adjusting the antenna configuration for the best possible reception. Figure 4-6 shows the block diagram of the antenna control interface system. Figure 4-6. Antenna Control Interface System Table 4-7 lists the I2C registers and their functions used with the antenna control interface. Table 4-7. Antenna Control Interface Registers REGISTER FUNCTION 4Fh GPIO Alternate Function Select 5Fh Antenna Control Interface – Control and Status 60h to 61h Antenna Control Interface – Transmit Data 62h to 63h Antenna Control Interface – Receive Data F9, FB, FD, FFh Software Interrupt Raw Status, Status, Mask, and Clear – Transaction Complete and Timeout Status The TVP9900 supports two modes of antenna control: Mode A for basic control (transmit transaction only) and Mode B for advanced control (transmit and receive transactions) as defined in the CEA-909 standard. For Mode B operation, the TVP9900 supports both 1-pin and 2-pin operation. In 1-pin mode, the data input and output are muxed into one pin (pin 29), and in 2-pin mode the input and output use separate pins (pin 29 for output, pin 72 for input.) The desired pin mode is selected by setting register 5Fh, bit 0. Submit Documentation Feedback Functional Description 19 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 Table 4-8 lists the TVP9900 pins and their functions used with the antenna control interface. Table 4-8. Antenna Control Interface Pins PIN NAME FUNCTION 29 ANTCNTLIO Antenna control interface input/output 71 GPIO1 Signal direction of pin 29 in 1-pin mode 72 GPIO0/ANTCNTLIN Antenna control input for 2-pin mode The GPIO1 pin provides dedicated smart antenna control support, and in 1-pin mode this pin outputs the direction of the signal on pin 29: GPIO1 = 0 indicates signal input from antenna to TVP9900 pin 29 GPIO1 = 1 indicates signal output from TVP9900 pin 29 to antenna Four status bit are provided in the TVP9900 to indicate the completion of a successful receive or transmit transaction, or if a transaction timeout has occurred. • The ACIRXCT bit in the TVP9900 Software Interrupt Status Register (FBh) gets set when the receive transaction from a Mode B antenna is complete. • The ACITXCT bit in the same register gets set when the transmit transaction to the antenna is complete. • The ACIRXTO bit in the same register gets set when an interface timeout has occurred due to no reply form the antenna following a transmit transaction, or an incomplete receive transaction from the antenna. • The RXERR bit in the Antenna Control Interface Control and Status Register (5Fh) is set if an incomplete receive transaction occurs. The TVP9900 can be configured so that setting the ACIRXCT, ACITXCT, or ACIRXTO status bits can assert the INTREQ output of the TVP9900; this requires the mask bits to be configured correctly in the TVP9900 Software Interrupt Mask Register (FDh). If the host INTREQ is not used, the ACIRXCT, ACITXCT, and ACIRXTO interrupts should be masked and the host should poll the ACIRXCT and ACITXCT status bits to determine when the transactions are complete, and the host should poll the ACIRXTO and RXERR status bits to determine when a receive timeout or error has occurred. Antenna control data transfers occur utilizing the following illustrated formats. 4.7.1 Antenna Interrogation/Initialization The following steps are required to interrogate and initialize a smart antenna. The host processor first writes the required transaction data to a set of registers in the TVP9900 via the host processor I2C interface. 1. The system host processor transmits to the antenna a basic Mode A 14-bit serial data stream with an RF channel number of zero. 2. The system tri-states the line and waits 100 ms for a reply message from the antenna controller. If no response is received, a timeout occurs, and the antenna controller is assumed to be a Mode A system. The system uses only transmit operations for antenna control. 3. If the antenna responds with a 10-bit program identifier, the antenna controller is assumed to be a Mode B system, and the system uses transmit and receive operations for antenna control. This initialization is optional. If the system has only Mode A enabled, with no Mode B support, this initialization step may be omitted. 20 Functional Description Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 4.7.2 Transmit Data to Antenna Operation The following steps are required to transmit data to the antenna. The host processor writes the required transaction data to a set of registers in the TVP9900, via the host processor I2C interface. Step 1 Register 5Fh Set TXRXSEL (bit 2 = 1) to select a transmit data transaction, and set MODE (bit 4 = 1) to enable auto receive mode Step 2 Registers 60h to 61h Load 14-bit data value to be transmitted to antenna Step 3 Register 5Fh Set TXSTART (bit 3) to 1 to start transmit transaction to tuner Step 4 Register FBh 4.7.3 Check state of bit 4 or INTREQ pin to verify successful transaction Receive Data from Antenna Operation After an antenna transmit transaction is executed, a Mode B antenna should respond with a 10-bit data value within 100 ms. If the receive data is not received within 100 ms, a receive timeout occurs. The following steps are required to receive data from the antenna. The host processor first writes the required transaction data to a set of registers in the TVP9900, via the host processor I2C interface, then reads the data bytes received from the antenna stored in TVP9900 registers. Step 1 Register 5Fh Set TXRXSEL (bit 2 = 0) to select a receive data transaction, and set MODE (bit 4 = 1) to enable auto receive mode Step 2 Register FBh Check state of bit 5 or INTREQ pin to verify successful transaction, or wait for timeout interrupt (bit 3) to occur Step 3 Registers 62h to 63h Read 10-bit data value received from antenna Step 4 Register 5Fh Read RXERR value (bit 5) The RXERR bit is set to 1 to indicate an error occurred when receiving data from a Mode B antenna. If a non-zero data value was received from the antenna and no error occurred, the data is valid and the antenna is a Mode B antenna. If the data value is zero and no error occurred, a receive transaction did not occur and it is assumed that the antenna is a Mode A antenna. 4.8 General-Purpose Input/Output (GPIO) The TVP9900 has eight GPIO pins, GPIO0–GPIO7. GPIO1 is a dedicated pin for Smart Antenna support. GPIO0, GPIO5, GPIO6, and GPIO7 are shared pins and can be programmed as the following dedicated functions. See register 4Fh description for details about selecting these alternate functions. All pins are configured as inputs at device power-up. • GPIO0 – Antenna control input • GPIO5 – Sync output • GPIO6 – Reserved • GPIO7 – Interrupt request output Submit Documentation Feedback Functional Description 21 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 4.9 Clock Circuits An internal PLL generates all clocks required in the chip. A 25-MHz clock is required to derive the PLL. Most tuner devices have a 4-MHz crystal oscillator that can be output to the demodulator as a clock source. In the TVP9900, a 4-MHz clock input also can be used as the clock source. A 4-MHz clock is input to the TVP9900 receiver on terminal 13 (XTALIN), or a crystal of 25-MHz fundamental resonant frequency may be connected across terminals 13 (XTALIN) and 11 (XTALOUT). Figure 4-7 shows the reference clock configuration of 25-MHz crystal oscillation. NOTE: The oscillator input, XTALIN, is not 3.3-V tolerant and only works at 1.5-V signal levels. TVP9900 25 MHz Crystal XTALIN XTALOUT XTALREF Figure 4-7. 25-MHz Crystal Oscillation Figure 4-8 shows the reference clock configuration of 4-MHz clock input. TVP9900 XTALIN 4 MHz Clock XTALOUT Figure 4-8. 4-MHz Clock Input 4.10 Power-Up Sequence No specific power-supply sequence is required, as long as all power supplies are ramped to valid operating levels within 500 ms of one another. Output or bidirectional buffers power-up with the output buffers in tri-state mode. 4.11 Reset The reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device at power-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of 1 ms after all power-supply voltages are stable at the recommended operating voltage. Internal circuits synchronize the power-on reset with internal clocks; therefore, the RESETZ signal must remain active low for a minimum of 1 μs after the crystal oscillator and clocks are stable. Reset may be asserted any time after power up and stable crystal oscillation and must remain asserted for at least 1 μs. A minimum of 200 μs must be allowed after reset before commencing I2C operations. 22 Functional Description Submit Documentation Feedback TVP9900 www.ti.com VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 4.12 Power Down There is no required power-down sequence for the TVP9900. 4.13 Power-Supply Voltage Requirements The digital core uses a 1.5-V power supply. The digital I/O cells use a 3.3-V power supply. Note that the exception is for the oscillator input, XTALIN, which is not 3.3-V tolerant and only works at 1.5-V signal levels. The analog circuitry uses both a 1.5-V and a 3.3-V power supply. Submit Documentation Feedback Functional Description 23 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 5 High-K PCB Design Recommendations In order to effectively transfer heat out of the package and to keep the die junction temperature below 105°C, the TVP9900 is packaged in the thermal PowerPAD™ package, which has an exposed metal pad on the bottom of the device. To effectively use this package, the following PCB design requirements must be followed. • An array of thermal vias should be placed in the board at the placement location of the TVP9900, as shown in Figure 5-1. • The ideal thermal land size is 10 mm × 10 mm, and the ideal thermal via pattern is a 6 × 6 array. • The vias should be connected to the PCB ground plane. • The exposed metal pad of the TVP9900 should be soldered to these vias. • The copper trace thickness should be 0.071 mm (2 oz), if possible. 1.4 mm 0.33 mm 10 mm 10 mm 10-mm × 10-mm thermal land size 6 × 6 array of vias 1.4-mm via spacing 0.33-mm via diameter Figure 5-1. Thermal Land Size and Via Array Each of these recommendations is important to maximize the heat-sinking characteristics of the PCB. Refer to the Texas Instruments application report, PowerPAD™ Thermally Enhanced Package (literature number SLMA002), for more detailed information. 24 High-K PCB Design Recommendations Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6 Host Processor I2C Register Summary 6.1 Overview The TVP9900 IC is controlled by a host processor by using a set of control and status registers. Access to these registers by the host processor is via an I2C serial interface. A summary of the I2C host interface registers is given in Table 6-1. Table 6-1. I2C Host Interface Registers ADDRESS DEFAULT R/W 00h Receiver Control Register 1 / Soft Reset 20h R/W 01h Receiver Control Register 2 11h R/W 02h Reserved 03h VSB Control Register 02h R/W 04h AGC Control Register 07h R/W 05h–1Ah REGISTER NAME Reserved 1Bh VSB FEC Time Counter Control Register 1 BCh R/W 1Ch VSB FEC Time Counter Control Register 2 64h R/W 1Dh VSB FEC Time Counter Control Register 3 00h R/W 1Eh QAM FEC Time Counter Control Register 1 00h R/W 1Fh QAM FEC Time Counter Control Register 2 08h R/W 20h QAM FEC Time Counter Control Register 3 00h R/W 21h VSB FEC Segment Error Count Threshold 1 05h R/W 22h VSB FEC Segment Error Count Threshold 2 00h R/W 23h–24h Reserved 25h Update Status Control Register N/A R/W 26h Receiver Status Register N/A R 27h AGC Status Register 1 – AGC LF Accumulator Output (7:0) N/A R 28h AGC Status Register 2 – AGC LF Accumulator Output (15:8) N/A R 29h AGC Status Register 3 – AGC LF Accumulator Output (19:16) N/A R 2Ah NTSC Rejection Filter Status Register N/A R 2Bh Timing Recovery Status Register 1 – DTR LF Accumulator Output (7:0) N/A R 2Ch Timing Recovery Status Register 2 – DTR LF Accumulator Output (15:8) N/A R 2Dh Timing Recovery Status Register 3 – DTR LF Accumulator Output (23:16) N/A R 2Eh Timing Recovery Status Register 4 – DTR LF Accumulator Output (31:24) N/A R 2Fh Timing Recovery Status Register 5 – DTR LF Accumulator Output (39:32) N/A R 30h Timing Recovery Status Register 6 – DTR LF Accumulator Output (43:40) N/A R 31h–33h Reserved 34h Pilot Tracking Status Register 1 – DPT LF Accumulator Output (7:0) N/A R 35h Pilot Tracking Status Register 2 – DPT LF Accumulator Output (15:8) N/A R 36h Pilot Tracking Status Register 3 – DPT LF Accumulator Output (19:16) N/A R 37h–38h Reserved 39h Carrier Recovery Status Register 1 – DCL Average Error (7:0) N/A R 3Ah Carrier Recovery Status Register 2 – DCL Average Error (15:8) N/A R 3Bh Carrier Recovery Status Register 3 – DCL Average Error (19:16) N/A R 3Ch Carrier Recovery Status Register 4 – QAM DCL LF Accumulator Output (7:0) N/A R 3Dh Carrier Recovery Status Register 5 – QAM DCL LF Accumulator Output (15:8) N/A R 3Eh Carrier Recovery Status Register 6 – QAM DCL LF Accumulator Output (19:16) N/A R N/A R 3Fh–40h 41h Reserved Forward Error Correction Status Register 1 Submit Documentation Feedback Host Processor I2C Register Summary 25 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 Table 6-1. I2C Host Interface Registers (continued) ADDRESS REGISTER NAME DEFAULT R/W Forward Error Correction Status Register 2 – FEC Segment Error Count (7:0) N/A R 44h Forward Error Correction Status Register 3 – FEC Segment Error Count (11:8) N/A R 45h Forward Error Correction Status Register 4 N/A R 42h Reserved 43h 46h–4Eh Reserved 4Fh GPIO Alternate Function Select Register 00h R/W 50h GPIO Output Data Register 00h R/W 51h GPIO Output Enable Register FFh R/W 52h GPIO Input Data Register 00h R 53h MPEG Interface Output Enable Register 1 00h R/W 54h MPEG Interface Output Enable Register 2 00h R/W 55h Tuner Control Interface – I2C Slave Device Address 00h R/W 56h Tuner Control Interface – Data Register 1 00h R/W 57h Tuner Control Interface – Data Register 2 00h R/W 58h Tuner Control Interface – Data Register 3 00h R/W 59h Tuner Control Interface – Data Register 4 00h R/W 5Ah Tuner Control Interface – Data Register 5 00h R/W 5Bh Tuner Control Interface – Data Register 6 00h R/W 5Ch Tuner Control Interface – Data Register 7 00h R/W 5Dh Tuner Control Interface – Data Register 8 00h R/W 5Eh Tuner Control Interface – Control and Status Register 00h R/W 5Fh Antenna Control Interface – Control and Status Register 00h R/W 60h Antenna Control Interface – Transmit Data Register 1 00h R/W 61h Antenna Control Interface – Transmit Data Register 2 00h R/W 62h Antenna Control Interface – Receive Data Register 1 00h R/W 63h Antenna Control Interface – Receive Data Register 2 00h R/W 64h–6Fh Reserved 70h Firmware ID – ROM Version 02h R 71h Firmware ID – RAM Major Version 00h R 72h Firmware ID – RAM Minor Version 00h R 73h–7Fh Reserved 80h Device ID LSB 00h R 81h Device ID MSB 99h R 00h R/W 00h R 00h R 00h R/W 00h W 82h–EDh EEh EFh–F8h Reserved Miscellaneous Control Register Reserved F9h Software Interrupt Raw Status Register FAh Reserved FBh Software Interrupt Status Register FCh Reserved FDh Software Interrupt Mask Register FEh Reserved FFh Software Interrupt Clear Register 6.2 I2C Register Definitions 26 Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.1 Receiver Control Register 1 / Soft Reset Any write to this register causes a soft reset, which puts the receiver back into signal acquisition, and enables any changes made to registers 01h to 22h. Recommend performing soft reset after channel change. Address 00h Default 20h Bit Mnemonic 7 6 5 4 3 2 RDNSEL MPEGSEL DCLKPS BYSTPS DERRPS PCLKPS DMDSEL R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 00 Type Default BIT MNEMONIC NAME 1 0 DESCRIPTION 7 RDNSEL MPEG interface redundancy select The MPEG interface redundancy select is used by the host processor to select the data with redundancy output mode. 0 = No redundancy (data only mode) selected (default) 1 = Data with redundancy mode selected 6 MPEGSEL MPEG interface serial output select The MPEG interface serial output select is used by the host processor to select the serial versus parallel output mode for the MPEG interface. 0 = 8-bit parallel data output mode selected (default) 1 = Serial data output mode selected 5 DCLKPS The MPEG interface data clock output polarity select is used by the host processor to select the polarity of the DCLK output pin. MPEG interface data 0 = All MPEG interface output signals transition with respect to the rising edge clock output polarity select of DCLK 1 = All MPEG interface output signals transition with respect to the falling edge of DCLK (default) 4 BYSTPS MPEG interface byte start output polarity select 3 DERRPS The MPEG interface data error output polarity select is used by the host MPEG interface data error processor to select the polarity of the DERROR output pin. output polarity select 0 = DERROR is active high (default) 1 = DERROR is active low 2 PCLKPS The MPEG interface packet clock output polarity select is used by the host MPEG interface packet processor to select the polarity of the PACCLK output pin. clock output polarity select 0 = PACCLK is active high (default) 1 = PACCLK is active low DMDSEL The VSB or QAM mode select bits are used by the host processor to select the demodulation type to be used by the TVP9900 receiver device. VSB or QAM 00 = 8 VSB mode selected (default) demodulation mode select 01 = Reserved 10 = 64 QAM mode selected 11 = 256 QAM mode selected 1:0 Submit Documentation Feedback The MPEG interface byte start output polarity select is used by the host processor to select the polarity of the BYTESTART output pin. 0 = BYTESTART is active high (default) 1 = BYTESTART is active low Host Processor I2C Register Summary 27 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.2 Receiver Control Register 2 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 01h Default 11h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved IQSWAP Reserved DNFCTRL DAFBYP Reserved Type R R R R/W R/W R/W R/W Default 0 0 0 1 00 0 1 BIT MNEMONIC 7:6 NAME DESCRIPTION — Reserved Reserved for future use 5 IQSWAP IQ swap Timing recovery spectral shift 0 = Shift spectrum positive frequency (default) 1 = Shift spectrum negative frequency. For QAM mode, this bit swaps I and Q. 4 — Reserved Reserved for future use. Always set to 1. DNFCTRL NTSC detection circuit control NTSC detection circuit control for VSB (always bypassed for QAM) 00 = Use detection circuit (default) 01 = Force bypass of NTSC filter 10 = Force insertion of NTSC filter 11 = Reserved 1 DAFBYP Adjacent channel filter bypass Adjacent channel filter bypass for VSB (always bypassed for QAM) 0 = Enable the adjacent channel filter (default) 1 = Bypass the adjacent channel filter 0 — Reserved Reserved for future use. Always set to 1. 3:2 6.2.3 VSB Control Register A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 03h Default 02h Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved RSTDIS Reserved Reserved Reserved Reserved Type R R R R/W R R R R Default 0 0 0 0 0 0 1 0 Mnemonic BIT 7:5 4 3:0 28 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use RSTDIS Auto restart disable Disable VSB automatic soft reset mode. 0 = Firmware automatically restarts acquisition when there are too many segment errors (default) 1 = Disable automatic restarts — Reserved Reserved for future use. Always set to 2h. Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.4 AGC Control Register A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 04h Default 07h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved DAGINV Type R R R R R R/W R Default 0 0 0 0 0 1 11 BIT MNEMONIC 7:3 2 1:0 6.2.5 NAME Reserved DESCRIPTION — Reserved Reserved for future use DAGINV AGC output signal invert select The automatic gain control output signal (AGCOUT) invert select bit is used by the host processor to change the polarity of the output signal. 0 = AGCOUT is non-inverted 1 = AGCOUT is inverted (default) — Reserved Reserved for future use. Always set to 3h. VSB FEC Time Counter Register 1 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 1Bh Default BCh Bit 7 6 5 Mnemonic 4 3 Type R/W Default 0xBC BIT 7:0 2 1 0 FCSFRSTIMECOUNT1 MNEMONIC FCSFRSTIMECOUNT1 Submit Documentation Feedback NAME VSB update interval count, bits (7:0) DESCRIPTION Update interval count value (RS blocks) for segment error count; bits (7:0) of 24-bit value. The remaining bits are stored in registers 1Ch and 1Dh. Host Processor I2C Register Summary 29 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.6 VSB FEC Time Counter Register 2 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 1Ch Default 64h Bit 7 6 5 Mnemonic 4 3 R/W Default 0x64 MNEMONIC 7:0 NAME VSB update interval count, bits (15:8) FCSFRSTIMECOUNT2 6.2.7 1 0 FCSFRSTIMECOUNT2 Type BIT 2 DESCRIPTION Update interval count value (RS blocks) for segment error count; bits (15:8) of 24-bit value VSB FEC Time Counter Register 3 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 1Dh Default 00h Bit 7 6 5 Mnemonic 4 3 Type R/W Default 0x00 BIT 7:0 30 2 1 0 FCSFRSTIMECOUNT3 MNEMONIC FCSFRSTIMECOUNT3 NAME VSB update interval count, bits (23:16) Host Processor I2C Register Summary DESCRIPTION Update interval count value (RS blocks) for segment error count; bits (23:16) of 24-bit value Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.8 QAM FEC Time Counter Register 1 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 1Eh Default 00h Bit 7 6 5 4 Mnemonic 3 R/W Default 0x08 MNEMONIC NAME 6.2.9 0 DESCRIPTION QAM update interval JCSJRSTIMECOUNT1 count, bits (7:0) 7:0 1 JCSJRSTIMECOUNT1 Type BIT 2 Update interval count value (RS blocks) for segment error count; bits (7:0) of 24-bit value. The remaining bits are stored in registers 1Fh and 20h. QAM FEC Time Counter Register 2 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 1Fh Default 08h Bit 7 6 5 4 Mnemonic 3 Type R/W Default 0x08 BIT MNEMONIC NAME 1 0 DESCRIPTION QAM update interval JCSJRSTIMECOUNT2 count, bits (15:8) 7:0 2 JCSJRSTIMECOUNT2 Update interval count value (RS blocks) for segment error count; bits (15:8) of 24-bit value 6.2.10 QAM FEC Time Counter Register 3 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 20h Default 00h Bit 7 6 5 Mnemonic 4 3 Type R/W Default 0x00 BIT 7:0 2 1 0 JCSJRSTIMECOUNT3 MNEMONIC NAME QAM update interval JCSJRSTIMECOUNT3 count, bits (23:16) Submit Documentation Feedback DESCRIPTION Update interval count value (RS blocks) for segment error count; bits (23:16) of 24-bit value Host Processor I2C Register Summary 31 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.11 VSB FEC Segment Error Count Threshold Register 1 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 21h Default 05h Bit 7 6 5 Mnemonic 4 3 Type R/W Default 0x05 BIT MNEMONIC 7:0 2 1 0 UNCORRINT1 UNCORRINT1 NAME DESCRIPTION Segment error count threshold, bits (7:0) Segment error count threshold; bits (7:0) of a 12-bit value. The remaining bits are stored in register 22h. 6.2.12 VSB FEC Segment Error Count Threshold Register 2 A soft reset is required to enable any changes made to this register. A soft reset is initiated by writing to register 00h. Address 22h Default 00h Bit 7 6 5 4 Reserved Reserved Reserved Reserved UNCORRINT2 Type R R R R R/W Default 0 0 0 0 0h Mnemonic BIT MNEMONIC 3 NAME 2 1 0 DESCRIPTION 7:4 Reserved Reserved Reserved for future use 3:0 UNCORRINT2 Segment error count threshold, bits (11:8) Segment error count threshold; bits (11:8) of a 12-bit value 6.2.13 Update Status Control Register Address 25h Default 00h Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved UPDATE Type R R R R R R R R/W Default 0 0 0 0 0 0 0 0 Mnemonic BIT 7:1 0 32 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use UPDATE Update status registers Update all status registers (26h to 45h) Host writes a 1 to this bit to update all the status registers. Host should then read this bit until it reads 0; the status update is then complete, and it is safe to read any/all of the status registers. Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.14 Receiver Status Register Address 26h Bit 7 Mnemonic 6 5 4 3 2 1 0 FLDSYNC Reserved Reserved Reserved ERRCNT Reserved SLCERR Type R R R R R R R Default 0 N/A N/A N/A N/A N/A N/A BIT 7:4 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use 3 ERRCNT Reed Solomon segment error count status Immediate RS segment error count threshold status bit 0 = RS segment error count is below threshold 1 = RS segment error count is above threshold 2 — Reserved Reserved for future use 1 SLCERR Slicer error status Immediate slicer error threshold status bit 0 = Slicer error is below threshold 1 = Slicer error is above threshold 0 FLDSYNC Field sync lock status Immediate field sync lock status bit 0 = Field sync is lost 1 = Field sync is locked (not lost) 6.2.15 AGC Status Register 1 Address Bit 27h 7 6 5 Mnemonic 4 1 0 R Default 7:0 2 DAGLFACC1STAT Type BIT 3 N/A MNEMONIC DAGLFACC1STAT NAME DESCRIPTION AGC accumulator output, bits (7:0) Bits (7:0) of the 20-bit AGC loop filter accumulator output. The remaining bits are stored in registers 28h and 29h. These register values are updated by writing a 1 to register 25h, bit 0. 6.2.16 AGC Status Register 2 Address Bit 28h 7 6 5 Mnemonic 2 1 0 R Default 7:0 3 DAGLFACC2STAT Type BIT 4 N/A MNEMONIC NAME AGC accumulator output, DAGLFACC2STAT bits (15:8) Submit Documentation Feedback DESCRIPTION Bits (15:8) of the 20-bit AGC loop filter accumulator output Host Processor I2C Register Summary 33 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.17 AGC Status Register 3 Address 29h Bit 7 6 5 4 Reserved Reserved Reserved Reserved Type R R R R R Default 0 0 0 0 N/A Mnemonic BIT MNEMONIC 3 2 1 0 DAGLFACC3STAT NAME DESCRIPTION 7:4 — Reserved Reserved for future use 3:0 DAGLFACC3STAT AGC accumulator output, bits (19:16) Bits (19:16) of the 20-bit AGC loop filter accumulator output 6.2.18 NTSC Rejection Filter Status Register Address 2Ah Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved DNFDETECT Type R R R R R R R R Default 0 0 0 0 0 0 0 N/A 1 0 Mnemonic BIT MNEMONIC 7:1 0 NAME DESCRIPTION — Reserved Reserved for future use DNFDETECT NTSC detection circuit status NTSC detection circuit status 0 = NTSC is NOT detected 1 = NTSC is detected 6.2.19 Timing Recovery Status Register 1 Address Bit 2Bh 7 6 5 Mnemonic 34 2 R Default 7:0 3 DTRLFACC1STAT Type BIT 4 N/A MNEMONIC DTRLFACC1STAT NAME Timing recovery accumulator output, bits (7:0) Host Processor I2C Register Summary DESCRIPTION Bits (7:0) of the 44-bit timing recovery loop filter accumulator output. The remaining bits are stored in registers 2Ch to 30h. These register values are updated by writing a 1 to register 25h, bit 0. Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.20 Timing Recovery Status Register 2 Address Bit 2Ch 7 6 5 4 Mnemonic Type 7:0 2 1 0 R Default BIT 3 DTRLFACC2STAT N/A MNEMONIC DTRLFACC2STAT NAME DESCRIPTION Timing recovery accumulator output, bits (15:8) Bits (15:8) of the 44-bit timing recovery loop filter accumulator output 6.2.21 Timing Recovery Status Register 3 Address Bit 2Dh 7 6 5 4 Mnemonic Type 7:0 2 1 0 R Default BIT 3 DTRLFACC3STAT N/A MNEMONIC DTRLFACC3STAT NAME DESCRIPTION Timing recovery accumulator output, bits (23:16) Bits (23:16) of the 44-bit timing recovery loop filter accumulator output 6.2.22 Timing Recovery Status Register 4 Address Bit 2Eh 7 6 5 4 Mnemonic Type 7:0 2 1 0 R Default BIT 3 DTRLFACC4STAT N/A MNEMONIC DTRLFACC4STAT NAME DESCRIPTION Timing recovery accumulator output, bits (31:24) Bits (31:24) of the 44-bit timing recovery loop filter accumulator output 6.2.23 Timing Recovery Status Register 5 Address Bit 2Fh 7 6 5 Mnemonic Type 7:0 3 2 1 0 R Default BIT 4 DTRLFACC5STAT N/A MNEMONIC DTRLFACC5STAT Submit Documentation Feedback NAME Timing recovery accumulator output, bits (39:32) DESCRIPTION Bits (39:32) of the 44-bit timing recovery loop filter accumulator output Host Processor I2C Register Summary 35 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.24 Timing Recovery Status Register 6 Address 30h Bit Mnemonic 7 6 5 4 3 2 1 Reserved Reserved Reserved Reserved Type R R R R R Default 0 0 0 0 N/A BIT MNEMONIC 7:4 3:0 0 DTRLFACC6STAT NAME DESCRIPTION — Reserved Reserved for future use DTRLFACC6STAT Timing recovery accumulator output, bits (43:40) Bits (43:40) of the 44-bit timing recovery loop filter accumulator output 6.2.25 Pilot Tracking Status Register 1 Address Bit 34h 7 6 5 Mnemonic 4 3 2 1 0 DPTLFACC1STAT Type R Default BIT N/A MNEMONIC 7:0 DPTLFACC1STAT NAME DESCRIPTION Pilot tracking accumulator output, bits (7:0) Bits (7:0) of the 20-bit pilot tracking loop filter accumulator output. The remaining bits are stored in registers 35h and 36h. These register values are updated by writing a 1 to register 25h, bit 0. 6.2.26 Pilot Tracking Status Register 2 Address Bit 35h 7 6 5 Mnemonic Type 7:0 36 3 2 1 0 R Default BIT 4 DPTLFACC2STAT N/A MNEMONIC NAME DPTLFACC2STAT Pilot tracking accumulator output, bits (15:8) Host Processor I2C Register Summary DESCRIPTION Bits (15:8) of the 20-bit pilot tracking loop filter accumulator output Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.27 Pilot Tracking Status Register 3 Address 36h Bit 7 6 5 4 Reserved Reserved Reserved Reserved Type R R R R R Default 0 0 0 0 N/A Mnemonic BIT MNEMONIC 3 2 1 0 DPTLFACC3STAT NAME DESCRIPTION 7:4 — Reserved Reserved for future use 3:0 DPTLFACC3STAT Pilot tracking accumulator output, bits (19:16) Bits (19:16) of the 20-bit pilot tracking loop filter accumulator output 6.2.28 Carrier Recovery Status Register 1 Address 39h Bit 7 6 5 4 Mnemonic Type 2 1 0 R Default N/A BIT 7:0 3 DCLAVGERR1STAT MNEMONIC DCLAVGERR1STAT NAME DESCRIPTION Bits (7:0) of the 20-bit DCL average error (derotator SNR) value. The remaining DCL average error, bits bits are stored in registers 3Ah and 3Bh. These register values are updated by (7:0) writing a 1 to register 25h, bit 0. 6.2.29 Carrier Recovery Status Register 2 Address 3Ah Bit 7 6 5 4 Mnemonic Type 2 1 0 R Default N/A BIT 7:0 3 DCLAVGERR2STAT MNEMONIC DCLAVGERR2STAT NAME DESCRIPTION DCL average error, bits (15:8) Bits (15:8) of the 20-bit DCL average error (derotator SNR) value 6.2.30 Carrier Recovery Status Register 3 Address 3Bh Bit 7 6 5 4 Reserved Reserved Reserved Reserved DCLAVGERR3STAT Type R R R R R Default 0 0 0 0 N/A Mnemonic BIT MNEMONIC 3 NAME 2 1 DESCRIPTION 7:4 — Reserved Reserved for future use 3:0 DCLAVGERR3STAT DCL average error, bits (19:16) Bits (19:16) of the 20-bit DCL average error (derotator SNR) value Submit Documentation Feedback 0 Host Processor I2C Register Summary 37 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.31 Carrier Recovery Status Register 4 Address 3Ch Bit 7 6 5 Mnemonic 4 3 2 1 0 DCLLFACC1STAT Type R Default N/A BIT MNEMONIC 7:0 DCLLFACC1STAT NAME DESCRIPTION QAM DCL loop filter accumulator output, bits (7:0) Bits (7:0) of the 20-bit DCL loop filter accumulator output for QAM. The remaining bits are stored in registers 3Dh and 3Eh. These register values are updated by writing a 1 to register 25h, bit 0. 6.2.32 Carrier Recovery Status Register 5 Address 3Dh Bit 7 6 5 Mnemonic 4 3 2 1 0 DCLLFACC2STAT Type R Default N/A BIT MNEMONIC 7:0 DCLLFACC2STAT NAME DESCRIPTION QAM DCL loop filter Bits (15:8) of the 20-bit DCL loop filter accumulator output for QAM. accumulator output, bits (15:8) 6.2.33 Carrier Recovery Status Register 6 Address 3Eh Bit 7 6 5 4 Reserved Reserved Reserved Reserved Type R R R R R Default 0 0 0 0 N/A Mnemonic BIT 38 MNEMONIC 3 NAME 7:4 — Reserved 3:0 QAM DCL loop filter DCLLFACC3STAT accumulator output, bits (19:16) Host Processor I2C Register Summary 2 1 0 DCLLFACC3STAT DESCRIPTION Reserved for future use Bits (19:16) of the 20-bit DCL loop filter accumulator output for QAM. Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.34 FEC Status Register 1 6.2.34.1 VSB Mode Address Bit 41h 7 6 5 4 Mnemonic Type 1 0 1 0 1 0 N/A MNEMONIC NAME 7:2 1:0 2 R Default BIT 3 FECSADDR1 FECSADDR1 DESCRIPTION Reserved Reserved for future use FEC synchronizer status FEC synchronizer status bits 00 = Searching for sync (data not valid) 01 = Locked sync (data valid) 10 = Reserved 11 = Sync lost (data not valid) 6.2.34.2 QAM Mode Address Bit 41h 7 6 5 4 Mnemonic Type N/A MNEMONIC 7:6 5:2 2 R Default BIT 3 FECSADDR1 FECSADDR1 1:0 NAME DESCRIPTION Trellis sync status Trellis sync status bits 00 = Sync locked, error under threshold 01 = Reserved 10 = Sync locked, error above threshold 11 = Hunting for sync Current deinterleaver control work value Current deinterleaver control work value FEC synchronizer status FEC synchronizer status bits 00 = Searching for sync (data not valid) 01 = Locked sync (data valid) 10 = Reserved 11 = Sync lost (data not valid) 6.2.35 FEC Status Register 2 Address Bit 43h 7 6 5 Mnemonic 2 R Default 7:0 3 FECSADDR2 Type BIT 4 N/A MNEMONIC FECSADDR2 Submit Documentation Feedback NAME DESCRIPTION FEC segment error count, bits (7:0) Bits (7:0) of the 12-bit FEC segment error count value. Bits (11:8) are stored in register 44h, bits (7:4). These register values are updated by writing a 1 to register 25h, bit 0. Host Processor I2C Register Summary 39 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.36 FEC Status Register 3 Address Bit 44h 7 6 5 4 Mnemonic 3 2 1 0 1 0 1 0 FECSADDR3 Type R Default BIT N/A MNEMONIC 7:4 FECSADDR3 3:0 NAME DESCRIPTION FEC segment error count, bits (11:8) Bits (11:8) of the 12-bit FEC segment error count value Reserved Reserved for future use 6.2.37 FEC Status Register 4 6.2.37.1 VSB Mode Address Bit 45h 7 6 5 4 Mnemonic 3 2 FECSADDR4 Type R Default BIT N/A MNEMONIC 7:0 FECSADDR4 NAME DESCRIPTION Reserved Reserved for future use 6.2.37.2 QAM Mode Address Bit 45h 7 6 5 Mnemonic N/A MNEMONIC 7:5 3:0 40 2 R Default 4 3 FECSADDR4 Type BIT 4 FECSADDR4 NAME DESCRIPTION Reserved Reserved for future use Deframer synchronization Deframer synchronization 0 = Sync not locked 1 = Sync locked Frame error maximum Maximum number of frame errors encountered Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.38 GPIO Alternate Function Select Register Address 4Fh Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 GPIO7FS GPIO6FS Reserved Reserved Reserved Reserved Reserved Reserved R/W R/W R R R R R R 0 0 0 0 0 0 0 0 Type Default BIT 7 6 5:2 MNEMONIC NAME DESCRIPTION The GPIO bit 7 function select bit is used by the host processor to select the alternate function of the GPIO7 device pin. 0 = Configures the GPIO7 pin as general-purpose I/O bit 7 (default). 1 = Configures the GPIO7 pin as the host processor INTREQ output. GPIO7FS GPIO bit 7 function select GPIO6FS The GPIO bit 6 and GPIO bit 5 function select bit is used by the host processor to select the alternate function for both the GPIO6 and GPIO5 GPIO bit 6 and GPIO bit 5 device pins. function select 0 = Configures the GPIO6 pin as general-purpose I/O bit 6 and GPIO5 pin as general-purpose I/O bit 5 (default). 1 = Configures the GPIO5 pin as the SYNCOUT output. GPIO6 is reserved. — Reserved Reserved for future use 1 — Reserved NOTE: The GPIO1 pin is dedicated to Smart Antenna support. This pin outputs the direction of the signal on pin 29 in Smart Antenna 1-pin mode (see register 5Fh, bit 0). If GPIO1 = 0, signal input from antenna to TVP9900 pin 29 If GPIO1 = 1, signal output from TVP9900 pin 29 to antenna 0 — Reserved NOTE: The GPIO0 pin has an alternate function, which is the Antenna Control Interface input (ANTCNTLIN) when 2-pin mode is selected for this interface. See the Antenna Control Interface Control and Status Register (5Fh), bit 0 (pin mode select), for information on how to select this alternate function. 6.2.39 GPIO Output Data Register Address 50h Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 GPDO7 GPDO6 GPDO5 GPDO4 GPDO3 GPDO2 Reserved GPDO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Type Default BIT MNEMONIC NAME DESCRIPTION 7 GPDO7 General-purpose data output bit 7 General-purpose data output bit 7 is used by the host processor to set the data value on the GPIO7 device pin. 6 GPDO6 General-purpose data output bit 6 General-purpose data output bit 6 is used by the host processor to set the data value on the GPIO6 device pin. 5 GPDO5 General-purpose data output bit 5 General-purpose data output bit 5 is used by the host processor to set the data value on the GPIO5 device pin. 4 GPDO4 General-purpose data output bit 4 General-purpose data output bit 4 is used by the host processor to set the data value on the GPIO4 device pin. 3 GPDO3 General-purpose data output bit 3 General-purpose data output bit 3 is used by the host processor to set the data value on the GPIO3 device pin. 2 GPDO2 General-purpose data output bit 2 General-purpose data output bit 2 is used by the host processor to set the data value on the GPIO2 device pin. 1 — Reserved Reserved for future use GPDO0 General-purpose data output bit 0 General-purpose data output bit 0 is used by the host processor to set the data value on the GPIO0 device pin. 0 Submit Documentation Feedback Host Processor I2C Register Summary 41 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.40 GPIO Output Enable Register Address 51h Default FFh Bit Mnemonic Type 7 6 5 4 3 2 1 0 GPIO7OE GPIO6OE GPIO5OE GPIO4OE GPIO3OE GPIO2OE Reserved GPIO0OE R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Default BIT NAME DESCRIPTION 7 GPIO7OE General-purpose I/O bit 7 output enable General-purpose I/O bit 7 output enable is used by the host processor to configure the GPIO7 device pin as either an input or output. 0 = Configures GPIO7 as an output 1 = Configures GPIO7 as an input (default) 6 GPIO6OE General-purpose I/O bit 6 output enable General-purpose I/O bit 6 output enable is used by the host processor to configure the GPIO6 device pin as either an input or output. 0 = Configures GPIO6 as an output 1 = Configures GPIO6 as an input (default) 5 GPIO5OE General-purpose I/O bit 5 output enable General-purpose I/O bit 5 output enable is used by the host processor to configure the GPIO5 device pin as either an input or output. 0 = Configures GPIO5 as an output 1 = Configures GPIO5 as an input (default) GPIO4OE General-purpose I/O bit 4 output enable General-purpose I/O bit 4 output enable is used by the host processor to configure the GPIO4 device pin as either an input or output. 0 = Configures GPIO4 as an output 1 = Configures GPIO4 as an input (default) GPIO3OE General-purpose I/O bit 3 output enable General-purpose I/O bit 3 output enable is used by the host processor to configure the GPIO3 device pin as either an input or output. 0 = Configures GPIO3 as an output 1 = Configures GPIO3 as an input (default) 2 GPIO2OE General-purpose I/O bit 2 output enable General-purpose I/O bit 2 output enable is used by the host processor to configure the GPIO2 device pin as either an input or output. 0 = Configures GPIO2 as an output 1 = Configures GPIO2 as an input (default) 1 — Reserved Reserved for future use 0 GPIO0OE General-purpose I/O bit 0 output enable General-purpose I/O bit 0 output enable is used by the host processor to configure the GPIO0 device pin as either an input or output. 0 = Configures GPIO0 as an output 1 = Configures GPIO0 as an input (default) 4 3 42 MNEMONIC Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.41 GPIO Input Data Register Address 52h Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 GPDI7 GPDI7 GPDI7 GPDI7 GPDI7 GPDI7 Reserved GPDI7 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 GPDI7 General-purpose data input bit 7 General-purpose data input bit 7 is used by the host processor to read the data value on the GPIO7 device pin. 6 GPDI6 General-purpose data input bit 6 General-purpose data input bit 6 is used by the host processor to read the data value on the GPIO6 device pin. 5 GPDI5 General-purpose data input bit 5 General-purpose data input bit 5 is used by the host processor to read the data value on the GPIO5 device pin. 4 GPDI4 General-purpose data input bit 4 General-purpose data input bit 4 is used by the host processor to read the data value on the GPIO4 device pin. 3 GPDI3 General-purpose data input bit 3 General-purpose data input bit 3 is used by the host processor to read the data value on the GPIO3 device pin. 2 GPDI2 General-purpose data input bit 2 General-purpose data input bit 2 is used by the host processor to read the data value on the GPIO2 device pin. 1 — Reserved Reserved for future use GPDI0 General-purpose data input bit 0 General-purpose data input bit 0 is used by the host processor to read the data value on the GPIO0 device pin. 0 Submit Documentation Feedback Host Processor I2C Register Summary 43 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.42 MPEG Interface Output Enable Register 1 Address 53h Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 DO7OE DO6OE DO5OE DO4OE DO3OE DO2OE DO1OE DO0OE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Type Default BIT 44 MNEMONIC NAME DESCRIPTION 7 DO7OE MPEG data output bit 7 output enable MPEG data output bit 7 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 6 DO6OE MPEG data output bit 6 output enable MPEG data output bit 6 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 5 DO5OE MPEG data output bit 5 output enable MPEG data output bit 5 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 4 DO4OE MPEG data output bit 4 output enable MPEG data output bit 4 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 3 DO3OE MPEG data output bit 3 output enable MPEG data output bit 3 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 2 DO2OE MPEG data output bit 2 output enable MPEG data output bit 2 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 1 DO1OE MPEG data output bit 1 output enable MPEG data output bit 1 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 0 DO0OE MPEG data output bit 0 output enable MPEG data output bit 0 output enable is used by the host processor to enable the output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.43 MPEG Interface Output Enable Register 2 Address 54h Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved SYNCSOE DCLKOE Type R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC 7:2 NAME DESCRIPTION — Reserved Reserved for future use 1 SYNCSOE MPEG sync signals output enable is used by the host processor to enable the MPEG interface sync signals, which are packet clock (PACCLK), byte start MPEG sync signals output (BYTESTART) and data error (DERROR). After power-on reset, the outputs enable are disabled. 0 = Outputs are disabled (default) 1 = Outputs are enabled 0 DCLKOE MPEG data clock output enable MPEG data clock output enable is used by the host processor to enable the clock output. After power-on reset, the output is disabled. 0 = Output is disabled (default) 1 = Output is enabled 6.2.44 Tuner Control Interface – I2C Slave Device Address Register The I2C slave device address register contains the 7-bit I2C slave device address and the read/write transaction control bit to be used for the tuner device. Address 55h Default 00h Bit Mnemonic Type Default BIT 7:1 0 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 RW R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 MNEMONIC NAME DESCRIPTION A(6:0) Slave device address The slave device address bits are set by the host processor with the 7-bit I2C slave address of the Tuner device to be accessed. RW Read/write control The read/write control bit value is set by the host processor to program the type of Tuner Control Interface I2C transaction to be done. 1 = Read transaction 0 = Write transaction (default) Submit Documentation Feedback Host Processor I2C Register Summary 45 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.45 Tuner Control Interface – Data Register 1 Through 8 Address 56h to 5Dh Default 00h Bit 7 Mnemonic Type 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 MNEMONIC 7:0 5 R/W Default BIT 6 D(7:0) NAME DESCRIPTION Data register 1 through data register 8 contain the data bytes to be sent to the tuner for a write transaction or the data bytes received from the tuner for a read transaction. The data byte contained in data register 1 (56h) shall be the first byte sent to or read from the tuner. Data (7:0) 6.2.46 Tuner Control Interface – Control and Status Register Address 5Eh Default 00h Bit Mnemonic Type 7 6 5 4 3 2 1 0 BCNT2 BCNT2 BCNT2 Reserved Reserved START Reserved MODE R/W R/W R/W R R R/W R R/W 0 0 0 0 0 0 0 0 Default BIT NAME DESCRIPTION 7:5 BCNT(2:0) Byte count The byte count is used by the host processor to set the number of data bytes to be transferred to/from the tuner device. The byte count should not include the tuner I2C slave address byte. 000b = 1 byte, 001b = 2 bytes, ..., 110b = 7 bytes, 111b = 8 bytes 4:3 — Reserved Reserved for future use 2 START Transaction start The transaction start bit is set to 1 by the host processor to indicate to the MCU to start the transaction to the tuner. The MCU clears this bit at the end of the transaction. 1 — Reserved Reserved for future use 0 46 MNEMONIC MODE 2 I C mode Host Processor I2C Register Summary The mode bit is used by the host processor to set the I2C transfer mode and rate. 0 = Standard mode and 100-kbps transfer rate (default) 1 = Fast mode and 400-kbps transfer rate Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.47 Antenna Control Interface – Control and Status Register Address 5Fh Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved RXERR MODE TXSTART TXRXSEL TXDINV PINSEL Type R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT 7:6 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use 5 RXERR Receive data error The receive data error bit is set to 1 by the MCU to indicate an error occurred when receiving data from a Mode B antenna. The MCU clears this bit at the beginning of the next transaction. 4 MODE Auto receive mode The auto receive mode bit is set to 1 by the host processor to enable the antenna control interface logic to automatically set-up the receive mode after a transmit data transaction. 3 TXSTART Transmit start This bit is set to 1 by the host processor to start the transmit data transaction to the antenna. The MCU clears this bit when the transaction is complete. 2 TXRXSEL Transmit/receive select This bit is used by the host processor to select the next type of transaction to be done by the antenna control interface. In manual mode, the host processor controls this bit. In auto receive mode, the host processor sets this bit to 1 for the transmit data transaction, and the MCU sets this bit to 0 after the completion of the transmit transaction to enable the receive transaction. 0 = Receive data transaction 1 = Transmit data transaction 1 TXDINV Transmit data polarity The transmit data polarity bit is set to 1 by the host processor to invert the transmit data output. 0 = Normal polarity in conformance with CEA909 1 = Invert the transmit data output Pin mode select The pin mode select bit is used by the host processor to select the antenna control interface pin configuration. Before the 2-pin mode is selected, the GPIO0 pin must be configured as an input in register 51h, bit 0. 0 = 2-pin mode (separate input and output pins are used, input = pin 72, output = pin 29) (default) 1 = 1-pin mode (one bidirectional pin is used, pin 29) 0 PINSEL 6.2.48 Antenna Control Interface – Transmit Data Register 1 Address 60h Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Type Default BIT 7:0 MNEMONIC TXD(7:0) Submit Documentation Feedback NAME Transmit data (7:0) DESCRIPTION The least significant 8 bits of the 14-bit data word to be transmitted to the antenna. Bits (13:8) are stored in register 61h, bits (5:0). The data word is set by the host processor. Host Processor I2C Register Summary 47 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.49 Antenna Control Interface – Transmit Data Register 2 Address 61h Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 Type R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:6 — Reserved Reserved for future use 5:0 TXD(13:8) Transmit data (13:8) The most significant 6 bits of the 14-bit data word to be transmitted to the antenna. The data word is set by the host processor. 6.2.50 Antenna Control Interface – Receive Data Register 1 Address 62h Default 00h Bit Mnemonic Type 7 6 5 4 3 2 1 0 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Default BIT MNEMONIC 7:0 RXD(7:0) NAME DESCRIPTION The least significant 8 bits of the 10-bit program code received from a Mode B antenna. Bits (9:8) are stored in register 63h, bits (1:0). Receive data (7:0) 6.2.51 Antenna Control Interface – Receive Data Register 2 Address 63h Default 00h Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved RXD9 RXD8 Type R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 Mnemonic BIT 48 MNEMONIC NAME DESCRIPTION 7:2 — Reserved Reserved for future use 1:0 RXD(9:8) Receive data (9:8) The most significant 2 bits of the 10-bit program code received from a Mode B antenna Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.52 Firmware ID – ROM Version Register Address 70h Default 02h Bit 7 6 5 4 Mnemonic 3 0 1 0 1 0 R Default 7:0 1 ROMVER Type BIT 2 0x02 MNEMONIC ROMVER NAME DESCRIPTION ROM version Version identification for ROM code 6.2.53 Firmware ID – RAM Major Version Register Address 71h Default 00h Bit 7 6 5 4 Mnemonic 3 Type R Default BIT 7:0 2 RAM1VER 0x00 MNEMONIC RAM1VER NAME DESCRIPTION Major RAM version Major version identification for RAM code 6.2.54 Firmware ID – RAM Minor Version Register Address 72h Default 00h Bit 7 6 5 Mnemonic 2 R Default 7:0 3 RAM2VER Type BIT 4 0x00 MNEMONIC RAM2VER Submit Documentation Feedback NAME Minor RAM version DESCRIPTION Minor version identification for RAM code Host Processor I2C Register Summary 49 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.55 Device ID LSB Register Address 80h Default 00h Bit 7 6 5 4 Mnemonic 3 2 1 0 1 0 DEVID1 Type R Default 0x00 BIT MNEMONIC 7:0 DEVID1 NAME DESCRIPTION Device ID LSB LSB of the device ID 6.2.56 Device ID MSB Register Address 81h Default 99h Bit 7 6 5 4 Mnemonic 3 2 DEVID2 Type R Default 0x99 BIT MNEMONIC 7:0 DEVID2 NAME DESCRIPTION Device ID MSB MSB of the device ID 6.2.57 Miscellaneous Control Register Address EEh Default 00h Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved INTRQPS MCUMDE MCURST Type R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 Mnemonic BIT 7:3 2 50 MNEMONIC — INTRQPS NAME DESCRIPTION Reserved Reserved for future use Interrupt request pin polarity select The interrupt request pin polarity select bit is used by the host processor to select either an active low or active-high INTREQ output. Note that when active low is selected, the output goes tri-state when inactive (not driven high). Hence a pullup resistor needs to be used on the PCB. This is done so interrupt request sources from multiple ICs can be wired together. 0 = INTREQ output pin is active low (default) 1 = INTREQ output pin is active high 1 MCUMDE MCU memory mode The MCU memory mode is used by the host processor to select ROM or RAM as the code memory for the internal TVP9900 MCU. 0 = MCU executes from ROM (default) 1 = MCU executes from RAM 0 MCURST MCU reset The MCU reset bit is used by the host processor to do a soft reset of the internal TVP9900 MCU. 0 = MCU not in reset mode (default) 1 = MCU in reset mode Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.58 Software Interrupt Raw Status Register The raw status bits in this register are cleared by the host processor by writing a 1 to the corresponding bit in the Software Interrupt Clear Register (FFh). The intended use of the raw status registers is for events to be monitored by the host processor via polling instead of interrupt driven. Address F9h Default 00h Bit 7 6 5 4 3 2 1 0 Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Mnemonic BIT 7:6 MNEMONIC — NAME DESCRIPTION Reserved Reserved for future use 5 ACIRXCT Antenna Control Interface receive transaction complete The Antenna Control Interface receive transaction complete raw status bit is set to 1 by the MCU when the receive transaction from a Mode B antenna is complete. This means an entire 10-bit data word was received. If an incomplete receive transaction (less than 10 bits) occurs, then this bit is not set; instead the ACIRXTO (bit 3) occurs. After the receive transaction is complete, the host processor should also check the receive data error status bit (RXERR) in the Antenna Control Interface Control and Status Register (5Fh) to ensure that an error was not detected while receiving the data. 4 ACITXCT Antenna Control Interface transmit transaction complete The Antenna Control Interface transmit transaction complete raw status bit is set to 1 by the MCU when the transmit transaction to the antenna is complete. 3 ACIRXTO Antenna Control Interface receive timeout The Antenna Control Interface receive timeout raw status bit is set to 1 by the MCU when the 100-ms timeout has occurred. If a 100-ms timeout occurs, then the antenna either did not reply to the transmit transaction (it is a mode A antenna) or an incomplete (less than 10-bits) receive transaction occurred. If an incomplete transaction occurred, then the receive error status bit (RXERR) in the Antenna Control Interface Control and Status Register (5Fh) is also set. 2 — Reserved Reserved for future use 1 TCIERROR Tuner Control Interface transaction error The Tuner Control Interface transaction error raw status bit is set to 1 by the MCU to indicate to the host processor that the tuner device did not respond to the I2C transaction or that a NO ACK was received from the tuner when an ACK was expected. TCIDONE Tuner Control Interface transaction done The Tuner Control Interface transaction done raw status bit is set to 1 by the MCU at the end of a normal transaction to indicate to the host processor that the tuner I2C transaction completed successfully. If an error occurs during a transaction to the tuner, the MCU does not set this bit to 1. 0 Submit Documentation Feedback Host Processor I2C Register Summary 51 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.59 Software Interrupt Status Register The status bits in this register are the result of the logical AND of the corresponding raw status bits and mask bits. A status bit is also automatically cleared when the corresponding raw status bit is cleared. Unmasked status bits in this register assert the host processor interrupt request output pin, INTREQ, of the TVP9900 when the status bit is set to 1. All unmasked hardware and software status bits are ORed together to drive the INTREQ output pin. Address FBh Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT 7:6 52 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use 5 ACIRXCT Antenna Control Interface receive transaction complete The Antenna Control Interface receive complete status bit is set to 1 (if unmasked) when the receive transaction from a Mode B antenna is complete and the bit is unmasked. 4 ACITXCT Antenna Control Interface transmit transaction complete The Antenna Control Interface transmit complete status bit is set to 1 (if unmasked) when the transmit transaction to the antenna is complete and the bit is unmasked. 3 ACIRXTO Antenna Control Interface receive timeout The Antenna Control Interface receive timeout status bit is set to 1 (if unmasked) when the 100-ms timeout has occurred and the bit is unmasked. 2 — Reserved Reserved for future use 1 TCIERROR Tuner Control Interface transaction error The Tuner Control Interface transaction error status bit is set to 1 (if unmasked) to indicate to the host processor that the tuner device did not respond to the I2C transaction or that a NO ACK was received from the tuner when an ACK was expected. 0 TCIDONE Tuner Control Interface transaction done The Tuner Control Interface transaction done status bit is set to 1 (if unmasked) at the end of a normal transaction to indicate to the host processor that the tuner I2C transaction completed successfully. If an error occurs during a transaction to the tuner, the MCU does not set this bit to 1. Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.60 Software Interrupt Mask Register The interrupt mask registers are used by the host processor to mask unused interrupt sources. When an interrupt status bit is masked, the event results in the raw status bit being set but does not result in the status bit being set or the assertion of the interrupt request output pin, INTREQ. Address FDh Default 00h Bit Mnemonic Type 7 6 5 4 3 2 1 0 Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Default BIT 7:6 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use ACIRXCT Antenna Control Interface receive transaction complete interrupt mask This bit is used by the host processor to enable the Antenna Control Interface receive transaction complete interrupt. 0 = Interrupt disabled (default) 1 = Interrupt enabled ACITXCT Antenna Control Interface transmit transaction complete interrupt mask This bit is used by the host processor to enable the Antenna Control Interface transmit transaction complete interrupt. 0 = Interrupt disabled (default) 1 = Interrupt enabled 3 ACIRXTO Antenna Control Interface receive timeout interrupt mask This bit is used by the host processor to enable the Antenna Control Interface receive timeout interrupt. 0 = Interrupt disabled (default) 1 = Interrupt enabled 2 — Reserved Reserved for future use 1 TCIERROR Tuner Control Interface transaction error interrupt mask This bit is used by the host processor to enable the Tuner Control Interface transaction error interrupt. 0 = Interrupt disabled (default) 1 = Interrupt enabled 0 TCIDONE Tuner Control Interface transaction done interrupt mask This bit is used by the host processor to enable the Tuner Control Interface transaction done interrupt. 0 = Interrupt disabled (default) 1 = Interrupt enabled 5 4 Submit Documentation Feedback Host Processor I2C Register Summary 53 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 6.2.61 Software Interrupt Clear Register The interrupt clear registers are used by the host processor to clear the interrupt raw status and status bits. To clear an interrupt, a 1 must be written to the corresponding bit in this register. The interrupt clear bits are automatically reset to 0 by the TVP9900 hardware. When all unmasked interrupts are cleared, the INTREQ device output pin is inactive. Address FFh Default 00h Bit Mnemonic 7 6 5 4 3 2 1 0 Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type W W W W W W W W Default 0 0 0 0 0 0 0 0 BIT 7:6 54 MNEMONIC NAME DESCRIPTION — Reserved Reserved for future use 5 ACIRXCT Antenna Control Interface receive transaction complete interrupt clear This bit should be set to 1 by the host processor to clear the Antenna Control Interface receive transaction complete raw status bit, which also clears the status bit and interrupt if unmasked. 4 ACITXCT Antenna Control Interface transmit transaction complete interrupt clear This bit should be set to 1 by the host processor to clear the Antenna Control Interface transmit transaction complete raw status bit, which also clears the status bit and interrupt if unmasked. 3 ACIRXTO Antenna Control Interface receive timeout interrupt clear This bit should be set to 1 by the host processor to clear the Antenna Control Interface receive timeout raw status bit, which also clears the status bit and interrupt if unmasked. 2 — Reserved Reserved for future use 1 TCIERROR Tuner Control Interface transaction error interrupt clear This bit should be set to 1 by the host processor to clear the Tuner Control Interface transaction error raw status bit, which also clears the status bit and interrupt if unmasked. 0 TCIDONE Tuner Control Interface transaction done interrupt clear This bit should be set to 1 by the host processor to clear the Tuner Control Interface transaction done raw status bit, which also clears the status bit and interrupt if unmasked. Host Processor I2C Register Summary Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the TVP9900 device. All electrical and timing characteristics in this specification shall be valid over the recommended operating conditions, unless otherwise noted. 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) DVDD_1_5 Supply voltage range 1.5-V digital core supply –0.5 V to 2.1 V IOVDD_3_3 Supply voltage range 3.3-V I/O cell supply –0.5 V to 4.2 V AVDD_1_5 Supply voltage range 1.5-V analog core supply –0.5 V to 2.1 V AVDD_3_3 Supply voltage range 3.3-V analog core supply –0.5 V to 4.2 V AVDD_REF_3_3 Supply voltage range 3.3-V reference supply –0.5 V to 4.2 V AVDD_PLL_1_5 Supply voltage range 1.5-V PLL supply XTALIN, oscillator input VI Input voltage range Fail-safe LVCMOS Differential IF inputs: AIFIN_P, AIFIN_N XTALOUT, oscillator output VO Output voltage range IIK Input clamp current VI < 0 or VI > VCC IOK Output clamp current VO < 0 or VO > VCC TA Operating free-air temperature range Tstg Storage temperature range (1) Fail-safe LVCMOS –0.5 V to 2.1 V –0.5 V to AVDD_PLL_1_5 + 0.5 V –0.5 V to IOVDD_3_3 + 0.5 V –0.5 V to AVDD_3_3 + 0.5 V –0.5 V to AVDD_PLL_1_5 + 0.5 V –0.5 V to IOVDD_3_3 + 0.5 V ±20 mA ±20 mA 0°C to 70°C –65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Electrical Specifications 55 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.2 Recommended Operating Conditions MIN NOM MAX UNIT 1.35 1.5 1.65 V 3 3.3 3.6 V 1.5-V analog core supply voltage 1.35 1.5 1.65 V 3.3-V analog core supply voltage 3 3.3 3.6 V 1.35 1.5 1.65 V 3 3.3 3.6 V DVDD_1_5 1.5-V digital core supply voltage IOVDD_3_3 3.3-V I/O cell supply voltage AVDD_1_5 AVDD_3_3 AVDD_PLL_1_5 1.5-V PLL supply voltage AVDD_REF_3_3 3.3-V reference supply voltage XTALIN 0 AVDD_PLL_1_5 LVCMOS 0 IOVDD_3_3 XTALOUT 0 AVDD_PLL_1_5 LVCMOS 0 IOVDD_3_3 0.7(AVDD_PLL_1_5) AVDD_PLL_1_5 0.7(IOVDD_3_3) IOVDD3_3 XTALIN 0 0.3(AVDD_PLL_1_5) LVCMOS 0 0.3(IOVDD_3_3) VI Input voltage VO Output voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current LVCMOS IOL Low-level output current LVCMOS XTALIN LVCMOS XTALIN 25 CLKIN 25 fclock Clock input frequency tt (1) Input transition, rise and fall time, 10% to 90% 0 TA Operating free-air temperature 0 TJ Operating junction temperature 0 (1) 7.3 V V V V –8 mA 8 mA MHz 25 ns 25 70 °C 25 105 °C MAX UNIT Specified by design DC Electrical Characteristics over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER VOH High-level output voltage LVCMOS IOH = –8 mA VOL Low-level output voltage LVCMOS IOL = 8 mA IIL Low-level input current IIH MIN TYP 0.8(IOVDD_3_3) V 0.22(IOVDD_3_3) V VI = VIL (min) ±1 μA High-level input current VI = VIH (max) ±1 μA IOZ High-impedance output current Specified by design ±20 μA IDVDD_1_5 1.5-V digital core supply current (1) 630 mA IIOVDD_3_3 3.3-V I/O cell supply current (1) 3 mA IAVDD_1_5 1.5-V analog core supply current (1) 0.2 mA IAVDD_3_3 3.3-V analog core supply current (1) 45 mA IAVDD_PLL_1_5 1.5-V analog PLL supply current (1) 5 mA IAVDD_REF_3_3 3.3-V analog reference supply current (1) 22 mA 8-VSB mode with parallel MPEG output (1) 1.2 W Power-down mode PD Power dissipation 0.45 mW Ci Input capacitance 8 pF Output capacitance 8 pF Co (1) 56 For typical values: nominal voltages, TA = 25°C Electrical Specifications Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.4 Analog Input Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VI Differential input voltage RI Input resistance CI Differential input capacitance TEST CONDITIONS MIN TYP Ccoupling = 0.1 μF MAX UNIT 1 Vp-p 2.4 Specified by design kΩ 10 pF Minimum input gain control -6 dB Maximum input gain control 6 dB Submit Documentation Feedback Electrical Specifications 57 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5 Timing Characteristics over recommended operating conditions (unless otherwise noted), specified by design 7.5.1 Crystal and Input Clock The TVP9900 can be used with an external crystal with a frequency of 25 MHz or with an external clock source with a frequency of 4 MHz or 25 MHz. The on-chip oscillator in the TVP9900 is designed to work with an external crystal with a frequency range of 15 MHz to 35 MHz. Therefore, if a clock frequency of 4 MHz is required, an external clock source, not an external crystal, must be used. When an external clock source is used, the on-chip oscillator simply functions as an input buffer. Table 7-1. Crystal and Input Clock Timing PARAMETER MIN TYP MAX UNIT fXTALIN Frequency, XTALIN (external crystal or clock source) 25 MHz tcyc1 Cycle time, XTALIN (external crystal or clock source) (1) 40 ns fXTALIN Frequency, XTALIN (external clock source only) 4 MHz tcyc1 Cycle time, XTALIN (external clock source only) (1) 250 Frequency stability (1) –50 ns 50 ppm Worst-case duty cycle is 45/55. XTALIN tcyc1 Figure 7-1. Crystal or Clock Timing Waveform 7.5.2 Device Reset The power-on reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device at power-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of 1 ms after all power-supply voltages are stable at the recommended operating voltage. Internal circuits synchronize the power-on reset with internal clocks; therefore, the RESETZ signal must remain active low for a minimum of 1 μs after the crystal oscillator and clocks are stable. Table 7-2. Device Reset Timing PARAMETER tw1(L) MIN Pulse duration, RESETZ low after all power supplies are stable at the recommended operating voltage and the crystal oscillator is stable 1 TYP MAX UNIT ms VDD (all supplies) tW1(L) RESESTZ Figure 7-2. Device Reset Signal Timing Waveforms 58 Electrical Specifications Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5.3 MPEG Interface 7.5.3.1 Parallel Mode (Data Only) The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-3 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output signals transitioning with respect to the falling edge of DCLK. In this mode, PACCLK is always active. If an error occurs, the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes. Table 7-3. Parallel Mode (Data Only) Timing CL = 30 pF PARAMETER MIN TYP 8 VSB mode 2.42408 64 QAM mode 3.37129 256 QAM mode 4.85133 MAX UNIT fDCLK Frequency, DCLK MHz dcyc Duty cycle, DCLK tpd1 Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid –2 3 ns tpd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high –2 3 ns tpd3 Propagation delay time, DCLK falling (or rising) edge to BYTE_START low –2 3 ns tpd4 Propagation delay time, DCLK falling (or rising) edge to DERROR high –2 3 ns tpd5 Propagation delay time, DCLK falling (or rising) edge to DERROR low –2 3 ns 50 % DCLK tpd1 DATAOUT [7:0] Byte 0 tpd2 Byte 1 Byte 186 Byte 187 Byte 0 tpd3 BYTE_START PACCLK tpd4 tpd5 DERROR Figure 7-3. MPEG Interface – Parallel Mode (Data Only) Timing Waveforms Submit Documentation Feedback Electrical Specifications 59 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5.3.2 Serial Mode (Data Only) The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-4 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output signals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cycles corresponding to the eight bits of the first byte of data. In this mode, PACCLK is always active. If an error occurs, the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes. Table 7-4. Serial Mode (Data Only) Timing CL = 30 pF PARAMETER fDCLK MIN Frequency, DCLK TYP 8 VSB mode 19.39266 64 QAM mode 26.97035 256 QAM mode 38.81070 MAX UNIT MHz dcyc Duty cycle, DCLK tpd1 Propagation delay time, DCLK falling (or rising) edge to SERDATAO valid –2 50 3 ns % tpd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high –2 3 ns tpd3 Propagation delay time, DCLK falling (or rising) edge to BYTE_START low –2 3 ns tpd4 Propagation delay time, DCLK falling (or rising) edge to DERROR high –2 3 ns tpd5 Propagation delay time, DCLK falling (or rising) edge to DERROR low –2 3 ns DCLK tpd1 SERDATAO D7 tpd2 D0 D7 D0 D7 tpd3 BYTE_START PACCLK tpd4 tpd5 DERROR Figure 7-4. MPEG Interface – Serial Mode (Data Only) Timing Waveforms 60 Electrical Specifications Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5.3.3 Parallel Mode (Data With Redundancy) The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-5 are shown with BYTE_START, PACCLK and DERROR as active-high signals and with the output signals transitioning with respect to the falling edge of DCLK. PACCLK is only active during the time period that the 188 bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the entire packet. Table 7-5. Parallel Mode (Data With Redundancy) Timing CL = 30 pF PARAMETER fDCLK Frequency, DCLK MIN TYP 8 VSB mode 2.68196 64 QAM mode 3.65821 256 QAM mode 5.26422 MAX UNIT MHz dcyc Duty cycle, DCLK tpd1 Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid –2 50 3 ns % tpd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high –2 3 ns tpd3 Propagation delay time, DCLK falling or rising edge to BYTE_START low –2 3 ns tpd4 Propagation delay time, DCLK falling (or rising) edge to PACCLK high –2 3 ns tpd5 Propagation delay time, DCLK falling (or rising) edge to PACCLK low –2 3 ns tpd6 Propagation delay time, DCLK falling (or rising) edge to DERROR high –2 3 ns tpd7 Propagation delay time, DCLK falling (or rising) edge to DERROR low –2 3 ns DCLK tpd1 DATAOUT [7:0] Byte 0 tpd2 Byte 1 Byte 187 Byte 0 tpd3 BYTE_START tpd4 tpd5 PACCLK tpd6 tpd7 DERROR Figure 7-5. MPEG Interface – Parallel Mode (Data With Redundancy) Timing Waveforms Submit Documentation Feedback Electrical Specifications 61 TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5.3.4 Serial Mode (Data With Redundancy) The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-6 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output signals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cycles corresponding to the eight bits of the first byte of data. PACCLK is only active during the time period that the 188 bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the entire packet. Table 7-6. Serial Mode (Data With Redundancy) Timing CL = 30 pF PARAMETER fDCLK MIN Frequency, DCLK TYP 8 VSB mode 2.42408 64 QAM mode 3.37129 256 QAM mode 4.85133 MAX UNIT MHz dcyc Duty cycle, DCLK tpd1 Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid 50 3 ns % tpd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high 3 ns tpd3 Propagation delay time, DCLK falling (or rising) edge to BYTE_START low 3 ns tpd4 Propagation delay time, DCLK falling (or rising) edge to DERROR high 3 ns tpd5 Propagation delay time, DCLK falling (or rising) edge to DERROR low 3 ns DCLK tpd1 SERDATAO D7 tpd2 D7 D0 D0 D7 tpd3 BYTE_START tpd4 tpd5 PACCLK tpd6 tpd7 DERROR Figure 7-6. MPEG Interface – Serial Mode (Data With Redundancy) Timing Waveforms 62 Electrical Specifications Submit Documentation Feedback TVP9900 VSB/QAM Receiver www.ti.com SLEA064A – MARCH 2007 – REVISED JULY 2007 7.5.4 Host and Tuner I2C Interface Host processor communication with the TVP9900 device is done via an I2C slave interface. The TVP9900 also has an I2C master interface that is used by the TVP9900 to communicate with the system tuner. Both of these I2C interfaces are designed to work for both standard and fast modes of operation. The timing parameters and the timing waveforms below pertain to both I2C interfaces. Table 7-7. Host and Tuner I 2C Interface Timing STANDARD MODE PARAMETER FAST MODE MIN MAX 100 UNIT MIN MAX 0 400 fSCL Frequency, SCL 0 tW(H) Pulse duration, SCL high 4 tW(L) Pulse duration, SCL low tr Rise time, SCL and SDA 1000 300 ns tf Fall time, SCL and SDA 300 300 ns tsu1 Setup time, SDA to SCL th1 Hold time, SCL to SDA (1) tbuf 4.7 kHz μs 0.6 μs 1.3 250 100 0 0 ns Bus free time between stop and start condition 4.7 1.3 μs tsu2 Setup time, SCL to start condition 4.7 0.6 μs th2 Hold time, start condition to SCL 4 0.6 μs tsu3 Setup time, SCL to stop condition 4 0.6 CL Load capacitance for each bus line (1) 400 ns μs 400 pF The TVP9900 internally provides a minimum hold time of 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. tw(H) tw(L) tr tf SCL tsu1 th1 SDA Figure 7-7. I2C SCL and SDA Timing Waveforms SCL tsu2 tsu3 th2 tbuf SDA Start Condition Stop Condition Figure 7-8. I2C Start and Stop Conditions Timing Waveforms Submit Documentation Feedback Electrical Specifications 63 A B C 18pF C40 18pF C39 TUNER_IF_OUT2 TUNER_IF_OUT1 R7 X1 25MHz R6 0 0 CLKIN_4_25MHz R9 DGND XTALREF XTALOUT A3.3V AGCOUT CLKIN_SEL ON: XTAL_25MHz (default) OFF: CLKIN_4MHz JP1 R8 DNP 0 XTALIN D3.3V JP1: CLKIN_SEL 10K DGND XTALOUT XTALREF XTALIN APLL_1.5V A1.5V AIFIN_P AIFIN_N DNP R8 for 25MHz Input from crystal (default) DNP R6 and R7 for 4MHz Input from Tuner Place R6, R7 and R8 close to Pins 11 and 13 0.1uF 0.1uF C3 C2 Put AC Coupling Close to TVP9900 AGCOUT DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C21 0.01uF 1.5K R12 nRESET AGND AVDD _3_3 AIFIN_P AIFIN_N AVDD _3_3 AGND AVDD _1_5 AGND AGND_PLL AVDD_PLL_1_5 XTALOUT XTALREF XTALIN CLKIN DIVINSEL CLKOUT DGND DVDD_1_5 IOGND IOVDD_3_3 DGND DGND A_REF_3.3V C1 0.1uF DGND PWRPAD D 2 R1 24K 0.1% TVP9900 D3.3V R10 JP2 I2CA0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PWRDOWN LOW (ON): Address = 0xB8h (default) HIGH (OFF): Address = 0xBAh D1.5V DATAOUT4 DATAOUT5 DATAOUT6 DATAOUT0 DATAOUT1 DATAOUT2 DATAOUT3 DGND D3.3V DEM_SCL_3_3V DEM_SDA_3_3V TUNSCL TUNSDA ANTCNTL RPACK4-33 R4 RPACK4-33 R3 RPACK4-33 R5 LOW (ON): Normal Operation (default) HIGH (OFF): PowerDown Mode JP3: POWERDOWN (Active High) PWRDOWN JP3 10K R11 DGND ANTCNTL DEM_SCL_3_3V DEM_SDA_3_3V JP2: TVP9900 I2C Addr Selection DGND 10K U1 D3.3V DATAOUT0 DATAOUT1 DVDD_1_5 DGND DATAOUT2 DATAOUT3 DATAOUT4 IOVDD_3_3 IOGND DATAOUT5 DATAOUT6 DATAOUT7/SERDATA0 DVDD_1_5 DGND PACCLK BYTESTART IOVDD_3_3 IOGND DCLK DGND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NSUB BGREFCAP BIASRES AVDD_RE F_3_3 AGND_REF AGND DGND DVDD_1_5 GPIO0/ANTCNTLIN GPIO1 GPIO2 DGND DVDD_1_5 GPIO3 GPIO4 GPIO5/SYNCOUT IOVDD_3_3 IOGND GPIO6/LOCK GPIO7/INTREQ BYTE_VALID PACK_SYNC DCLK D_ERROR DATAOUT7_S0 DATAOUT[6..0] B Size Date: File: C34 0.1uF C16 0.01uF C28 0.1uF C10 0.01uF C22 0.1uF C23 0.1uF C35 0.1uF C17 0.01uF C29 0.1uF C11 0.01uF C13 0.01uF C20 0.01uF Revision DGND C38 0.1uF D1.5V C37 0.1uF Sheet of Drawn By: C36 0.1uF C18 0.01uF C19 0.01uF C31 0.1uF DGND C30 0.1uF D3.3V C12 0.01uF DGND C25 0.1uF DGND C8 0.01uF A_REF_3.3V C7 0.01uF APLL_1.5V C24 0.1uF 17-Jul-2006 C:\TVP9900\TVP9900 App Circuit.ddb Number TVP9900.Sch C33 0.1uF C15 0.01uF C27 0.1uF DGND C9 0.01uF D3.3V DGND C32 0.1uF DGND C6 0.01uF C5 0.01uF A1.5V C14 0.01uF D1.5V Title DATAOUT[6..0] DGND C4 0.01uF A3.3V C26 0.1uF A B C D Application Circuit RESETZ TMSEL0 TMSEL1 DGND DVDD_1_5 TMSEL2 TMSEL3 AGCOUT ANTCNTLIO TUNSDA TUNSCL IOGND IOVDD_3_3 I2CSDA I2CSCL DGND DVDD_1_5 I2CA0 PWRDOWN DERROR GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5_SYNC GPIO6_LOCK GPIO7_INTREQ 64 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5_SYNC GPIO6_LOCK GPIO7_INTREQ Application Circuit 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R2 RPACK8-10K 8 1 D3.3V TVP9900 VSB/QAM Receiver SLEA064A – MARCH 2007 – REVISED JULY 2007 www.ti.com Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TVP9900PFP NRND HTQFP PFP 80 TBD Call TI Call TI 0 to 70 TVP9900 TVP9900PFPR NRND HTQFP PFP 80 TBD Call TI Call TI 0 to 70 TVP9900 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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