TX517
SLOS725A – SEPTEMBER 2011 – REVISED JANUARY 2012
www.ti.com
Dual Channel, High-Voltage – Multi-Level Output Fully Integrated Ultrasound Transmitter
Check for Samples: TX517
FEATURES
DESCRIPTION
•
The TX517 is a fully integrated, dual channel, high
voltage Transmitter. It is specifically designed for
demanding medical Ultrasound applications that
require a Multi-level high-voltage pulse pattern. The
output stages are designed to deliver typically ±2.5A
peak output currents, with 200Vpp swings.
1
•
•
•
•
•
•
Output Voltage:
– Up to 200Vpp in Differential Mode
Peak Output Current: ±2.5A
Multi-Level Output
– Differential : 17 Levels
– Single Ended : 5 Levels
Integrated:
– Level Translator
– Driver
– High Voltage Output Stages
– CW output
TX Output Update Rate
– Up to 100MSPS
Minimal External Components
Small Package: BGA 13x13mm
The TX517 is a complete transmitter solution with
low-voltage input logic, level translators, gate drivers
and P-channel and N-Channel MOSFETs for each
channel.
The TX517 also incorporates a CW output stage.
The TX517 is available in a BGA package that is
Lead-Free (RoHS compliant) and Green. It is
specified for operation from 0°C to 85°C.
17 Level Pulser Chip:
The chip consists of two 5-level channels to form a
single 17-level transmitter cell when used in
conjunction with a transformer. It is designed to drive
the transducer not only at various output levels, but
also to modulate the width of the output pulses to
obtain the added flexibility of pulse-width-modulation
spectral shaping.
APPLICATIONS
•
•
Medical Ultrasound
High Voltage Signal Generator
BIAS
VAA
VDD VEE HV0 n LV0n
INP0A
INP1A
INP2A
INN0A
INN1A
INN2A
VCWn
VCWA
HV1A
CWINA
P0
P2
CH_A
Input
Logic,
Level
Translator
HV2 n LV2n HV1 n LV1n
HV2A
HV0A
P1
P1
P2
N2
N1
Channel A
OUTA
N0
PCLKIN
N1
N2
LV0A
LV2A
LV1A
GNDCWA
EN\
TX517
CWINA
PDM\
CWINB
HV2B
HV0B
VCWB
HV1B
P0
INN0B
INN1B
INN2B
Input
Logic,
Level
Translator
P1
P2
N2
N1
Channel B
OUTB
CWINB
N0
GNDCW
N1
N2
LV0B
GND
P1
P2
CH_B
INP0B
INP1B
INP2B
LV2B
LV1B
GNDCWB
GNDCWA
GNDCWB
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TX517
SLOS725A – SEPTEMBER 2011 – REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKING
TRANSPORT MEDIA, QUANTITY
ECO STATUS (2)
TX517IZCQ
BGA-144
TX517
Tray
Pb-Free, Green
(1)
(2)
NOTE: These Packages conform to Lead-Free and Green Manufacturing Specifications
Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree
GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1%of total product weight.
N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree.
Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total
product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
DEVICE INFORMATION
BGA-144 PINS
TOP VIEW
2
1
2
3
4
5
6
7
8
9
10
11
12
A
HV2B
GND
HV1B
HV0B
VCWB
EN\
VAAB
NC
NC
INP1B
INN1B
INP2B
A
B
NC
LV1B
LV1B
LV1B
LV1B
LV1B
GND
NC
NC
GND
VAAC
INN2B
B
C
OUTB
LV1B
LV1B
LV1B
LV1B
LV1B
CWINB
VEE
VEE
VEE
VEE
INN0B
C
D
NC
LV1B
LV1B
LV1B
LV1B
LV1B
GNDCWB
VEE
VEE
VEE
VEE
INP0B
D
E
LV2B
LV1B
LV1B
LV1B
LV1B
LV1B
VDDB
VEE
VEE
VEE
VEE
PCLKIN
E
F
LV1B
LV1B
LV1B
LV1B
LV1B
LV1B
LV0B
VEE
VEE
VEE
VEE
GND
F
G
LV1A
LV1A
LV1A
LV1A
LV1A
LV1A
LV0A
VEE
VEE
VEE
VEE
VDD
G
H
LV2A
LV1A
LV1A
LV1A
LV1A
LV1A
VDDA
VEE
VEE
VEE
VEE
CWINA
H
J
NC
LV1A
LV1A
LV1A
LV1A
LV1A
GNDCWA
VEE
VEE
VEE
VEE
INP0A
J
K
OUTA
LV1A
LV1A
LV1A
LV1A
LV1A
GND
VEE
VEE
VEE
VEE
INN0A
K
L
NC
LV1A
LV1A
LV1A
LV1A
LV1A
GND
NC
NC
GND
VAAD
INN2A
L
M
HV2A
GND
HV1A
HV0A
VCWA
PDM\
VAAA
BIAS
NC
INP1A
INN1A
INP2A
M
1
2
3
4
5
6
7
8
9
10
11
12
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TX517
TX517
SLOS725A – SEPTEMBER 2011 – REVISED JANUARY 2012
www.ti.com
PIN FUNCTIONS
PIN NAME
DESCRIPTION
SUPPLIES
VAAx
Input Logic Supply (+2.5V)
VDD
+5V Driver Supply
VEE
–5V Driver Supply
HV0A, HV0B
Positive Supply of Low-voltage FET Output stage; Channel A and B
LV0A, LV0B
Negative Supply of Low-voltage FET Output stage; Channel A and B
HV2A, HV2B
Positive Supply of Intermediate voltage FET Output stage; this stage includes an internal de-glitcher
circuit.Channel A and B
LV2A, LV2B
Negative Supply of Intermediate voltage FET Output stage; this stage includes an internal de-glitcher
circuit.Channel A and B
HV1A, HV1B
Positive Supply of High-voltage FET Output stage; Channel A and B
LV1A, LV1B
Negative Supply of High-voltage FET Output stage; Channel A and B
VCWA, VCWB
Supply connections for CW FET output stage; Channel A and B
GND
Ground connection; Driver
GNDCWA, GNDCWB
Ground connection for CW FET output stage of Channel A and B
BIAS
Connect to VAA (+2.5V); used for internal biasing; high-impedance input
INPUTS
INP0A, INP0B
Logic input signal for the Low-voltage P-FET stage of channel A and B; Low = ON, High = OFF. Controls
HV0A, HV0B. High impedance input.
INN0A, INN0B
Logic input signal for the Low-voltage N-FET stage of channel A and B; Low = OFF, High = ON. Controls
LV0A, LV0B. High impedance input.
INP2A, INP2B
Logic input signal for the Intermediate voltage P-FET stage of channel A and B; Low = ON, High = OFF.
Controls HV2A, HV2B. High impedance input.
INN2A, INN2B
Logic input signal for the Intermediate Voltage N-FET stage of channel A and B; Low = OFF, High = ON.
Controls LV2A, LV2B. High impedance input.
INP1A, INP1B
Logic input signal for the High-voltage P-FET stage of channel A and B; Low = ON, High = OFF. Controls
HV1A, HV1B. High impedance input.
INN1A, INN1B
Logic input signal for the High-voltage N-FET stage of channel A and B; Low = OFF, High = ON. Controls
LV1A, LV1B. High impedance input.
CWINA
CW gate input signal for A output. An input ‘1’ means that current sinks from OUTA. An input ‘0’ means that
current sources from OUTA. This pin directly accesses the output A CW FET gates.
CWINB
CW gate input signal for B output. An input ‘1’ means that current sinks from OUTB. An input ‘0’ means that
current sources from OUTB. This pin directly accesses the output B CW FET gates.
EN
Logic Input for non-CW path; use the Enable-pin to select between input data being latched or transparent
operation. Low = input data will be retimed by the internal (T&H) at the rate of the applied clock at PCLKIN.
High = use this mode when operating the TX517 without a clock. When High (1) the input data will bypass the
(T&H). This pin is a common control for Channel A and B. High impedance input.
PDM
Power-down control input non-CW path; Low = power-down, High = normal operation. The PDM-pin controls
the voltage translation circuits which draw some quiescent power. This pin is a common control for Channel A
and B. High impedance input.
PCLKIN
Clock input for usage in latch (T&H) mode. When clock signal is high, the (T&H) circuit is in track mode. When
clock signal is low, the (T&H) is in hold mode. This pin is a common clock input for both Channel A and B. High
impedance input.
OUTPUTS
OUTA
Output Channel A
OUTB
Output Channel B
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TX517
3
TX517
SLOS725A – SEPTEMBER 2011 – REVISED JANUARY 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground potential (GND = 0V); over operating free-air temperature (unless otherwise noted)
VDS
VDS
(1)
VALUE
UNIT
High-Voltage, Positive Supply HV1,2 referred to OUTA/B, see also Max. delta voltage
–0.3 to +80
V
High-Voltage, Positive Supply HV0 referred to OUTA/B, see also Max. delta voltage
–0.3 to +6
V
High-Voltage VCWA/B supply referred to GNDCWA/B
–0.3 to +16
V
High-Voltage, Negative Supply LV1,2 referred to OUTA/B, see also Max. delta voltage
–40 to +0.3
V
High-Voltage, Negative Supply LV0 referred to OUTA/B, see also Max. delta voltage
–6 to +0.3
V
Max. delta voltage: HV1-LV1 and HV2 – LV2
110
V
Max. delta voltage: HV0 – LV0
12
V
VDD
Driver Supply, positive
-0.3 to +6
V
VEE
Driver Supply, negative
–6 to +0.3
V
VAA
Logic Supply Voltage
–0.3 to +6
V
Logic Inputs (INPx, INNx, EN, PDM, PCLKIN, U)
–0.3 to +6
V
CW inputs (CWINA, CWINB)
–0.3 to +11
V
Peak Solder Temperature (2)
260
°C
150
°C
Maximum junction temperature, any condition (3)
TJ
125
°C
–65 to 150
°C
HBM
500
V
CDM
750
V
MM
200
V
TJ
Maximum junction temperature, continuous operation, long term reliability
Tstg
Storage temperature range
ESD ratings
(1)
(2)
(3)
(4)
(4)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
Device complies with JSTD-020D.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
THERMAL INFORMATION
THERMAL METRIC (1)
TX517
BGA (144) (ZCQ) PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
3.8
θJB
Junction-to-board thermal resistance
11.3
ψJT
Junction-to-top characterization parameter
0.2
Power
Rating (2) (3)
(TJ = 125ºC)
TA = 25°C
3.57
TA = 85°C
1.47
(1)
(2)
(3)
4
UNITS
28
°C/W
W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
This data was taken with the JEDEC High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase and
long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and reliability.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TX517
TX517
SLOS725A – SEPTEMBER 2011 – REVISED JANUARY 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
VAA
2.38
2.5
3.3
UNIT
V
VDD
4.75
5.0
5.25
V
VEE
–5.25
–5.0
–4.75
V
HV0A, HV0B
0
1.9
5
V
LV0A, LV0B
–5
–1.9
0
V
HV2A, HV2B
0
32
70
V
–30
–11.9
0
V
>HV0 and >HV2
61
70
V
–30
–20.9
