TX810
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SLLS996A – SEPTEMBER 2009 – REVISED APRIL 2010
8-Channel, Programmable T/R Switch for Ultrasound
Check for Samples: TX810
FEATURES
DESCRIPTION
•
•
The TX810 provides an integrated solution for a wide
range of ultrasound applications. It is an 8 channel,
current programmable, transmit/receive switch in a
small 6mm × 6mm package.
1
2
•
•
•
Compact T/R Switch for Ultrasound
Flexible Programmability
– 8 Bias Current Settings
– 8 Power/Performance Combinations
– Easy Power-Up/Down control
Fast Wake Up Time
Dual Supply Operation
Optimized Insertion Loss
The internal diodes limit the output voltage when high
voltage transmitter signals are applied to the input.
While the insertion loss of TX810 is minimized during
receive mode.
Unlike conventional T/R switches, the TX810 contains
a 3-bit interface used to program bias current from
7mA to 0mA for different performance and power
requirements. When the TX810 bias current is set as
0mA (i.e., high-impedance mode), the device is
configured
as
power-down
mode.
In
the
high-impedance mode, TX810 does not add
additional load to high-voltage transmitters. In
addition, the device can wake up from power-down
mode in less than 1µs. With these advanced
programmability features, significant power saving
can be achieved in systems.
APPLICATIONS
•
•
Medical Ultrasound
Industrial Ultrasound
VP
1 Channel
of TX810
HV TX
LV RX
VN
Figure 1. Block Diagram of TX810
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TX810
SLLS996A – SEPTEMBER 2009 – REVISED APRIL 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGED DEVICES
TX810IRHHT
OPERATING TEMPERATURE
RANGE
Tape and Reel, 250
S-PVQFN-N36
TX810IRHHR
(1)
TRANSPORT MEDIA,
QUANTITY
PACKAGE TYPE
0~70°C
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply Voltage, VD
-0.3 ~ +6
V
Supply Voltage, VP
-0.3 ~ +6
V
Supply Voltage, VN
-6 ~ +0.3
V
Supply Voltage, VB
-0.3 ~ +6
V
±100
V
Input AC voltage, INn
Input at Vsub
Output current, IO
Maximum junction temperature, continuous operation, long term reliability (2) TJ
Storage temperature range, Tstg
ESD ratings
(1)
(2)
-6 ~ +0.3
V
15
mA
125°C
-55°C to 150°C
HBM
500
V
CDM
750
V
MM
200
V
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
THERMAL INFORMATION
THERMAL METRIC (1)
(OLFM Airflow Assumed)
TX810
RHH
UNITS
36 PINS
qJA
Junction-to-ambient thermal resistance (2)
qJC(top)
Junction-to-case(top) thermal resistance
qJB
Junction-to-board thermal resistance
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
(1)
(2)
(3)
(4)
(5)
(6)
2
29.7
(3)
27
(4)
7.2
(5)
°C/W
0.1
(6)
7.2
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
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DEVICE INFORMATION
PIN FUNCTIONS
PIN
DESCRIPTION
NUMBER
NAME
1, 3, 7, 9, 10, 12, 34,
36
INn
16, 18, 19, 21, 25, 27,
28, 30
OUTn
33
VD
Logic Supply Voltage; +2.5 V to +5 V; bypass to ground with 0.1 µF and 10 µF capacitors
31
VP
Positive Supply Voltage; +5 V; bypass to ground with 0.1 µF and 10 µF capacitors
15
VN
Negative Supply Voltage; –5 V; bypass to ground with 0.1 µF and 10 µF capacitors
13
VB
Bias voltage; connect to 0 V (GND) for ±5 V operation
2, 8, 11, 14, 17, 20, 26,
29, 32, 35
GND
24
B1
Bit 1; Current program bit
23
B2
Bit 2; Current program bit
22
B3
Bit 3; Current program bit
4, 5, 6
NC
No internal connection.
0
Vsub
Inputs for Channel n
Outputs for Channel n
Ground
PowerPAD™ of the package. –5 V to 0 V for ±5 V operation. The thermal pad is needed for thermal
dissipation.
IN7
GND
IN8
VD
GND
VP
OUT8
GND
OUT7
PQFN (RHH) Package
6 × 6mm, 0.5mm Pitch
(Top View)
36
35
34
33
32
31
30
29
28
IN6
1
27
OUT6
GND
2
26
GND
IN5
3
25
OUT5
NC
4
24
B1
NC
5
23
B2
NC
6
22
B3
IN4
7
21
OUT4
GND 8
20
GND
19
OUT3
TX810
PowerPAD™
10
11
12
13
14
15
16
17
18
IN2
GND
IN1
VB
GND
VN
OUT1
GND
OUT2
IN3 9
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ELECTRICAL CHARACTERISTICS
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, Vsub= -5V, RLOAD = 400Ω; f = 5MHz, B3B2B1 = 111, VIN =
0.25VPP, unless otherwise noted. Test Level: A: Final tester limits; B: bench evaluation/simulation; C: Simulation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level
V
B
50
µA
A
0
V
B
V
B
DC POWER SPECIFICATIONS
Positive Supply VP
5
Negative Supply VN
-5
Quiescent current, VP, VN
No Signal
Substrate Voltage, VSUB
PowerPAD™
Digital Supply, VD
VN
2.5
5
Quiescent current, VD
No Signal
µA
A
Bias current, VP, VN path
B3B2B1 = 001
1.25
1
0.75
50
mA/CH
A
Bias current, VP, VN path
B3B2B1 = 111
5.95
7
8.05
mA/CH
A
Leakage Current
Any output; B3B2B1 = 000; No
Input
0.5
µA
A
2
VD
V
A
20
µA
A
0
0.4
V
A
20
µA
A
pF
C
LOGIC INPUTS
Logic High Input Voltage; VIH
Logic High Input Current; IIH
Logic Low Input Voltage; VIL
Logic Low Input Current; IIL Input
Capacitance, CIN
5
POWER DISSIPATION
All channels
Power-Down Dissipation
B3B2B1 = 000; no signal
Total Power Dissipation
200
µW
A
B3B2B1 = 001; no signal
80
92
mW
A
B3B2B1 = 111; no signal
560
644
mW
A
90
V
A
AC SPECIFICATIONS
Input Amplitude, VIN
Insertion loss, IL
1 µs positive and negative pulse
applied seperately at
PRF = 10 kHz
-90
CW mode (continuous wave)
-10
10
V
B
B3B2B1 = 111
-0.9
-1.8
dB
A
B3B2B1 = 100
-1.1
-1.8
dB
A
B3B2B1 = 001
-1.3
-2
dB
A
B3B2B1 = 111, RLOAD = 50Ω
-4.1
dB
B
-7
dB
B
Channel to channel IL matching
B3B2B1 = 001, RLOAD = 50Ω
B3B2B1 = 111
0.06
dB
B
Insertion Loss, IL
B3B2B1 = 111, at 20MHz
-0.9
dB
B
B3B2B1 = 111, RLOAD = 50 Ω
30
Ω
B
B3B2B1 = 001, RLOAD = 50 Ω
62
Ω
B
B3B2B1 = 111
44
Ω
B
B3B2B1 = 001
67
Ω
B
B3B2B1 = 111
140
MHz
B
B3B2B1 = 100
115
MHz
B
B3B2B1 = 001
65
MHz
B
B3B2B1 = 111, VIN = 0.5VPP
5MHz
-74
dBc
B
B3B2B1 = 100, VIN = 0.5VPP
5MHz
-74
dBc
B
B3B2B1 = 001, VIN = 0.5VPP
5MHz
-73
dBc
B
Equivalent Resistance, RON
-3dB Bandwidth, BW
2nd Harmonic Distortion, HD2, 5MHz
4
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ELECTRICAL CHARACTERISTICS (continued)
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, Vsub= -5V, RLOAD = 400Ω; f = 5MHz, B3B2B1 = 111, VIN =
0.25VPP, unless otherwise noted. Test Level: A: Final tester limits; B: bench evaluation/simulation; C: Simulation
PARAMETER
TEST CONDITIONS
2nd Harmonic Distortion, HD2, 10MHz
Cross-talk, Xtalk
3rd order Intermodulation, IMD3
(1)
Power Supply Modulation Ratio, PSMR
(2)
Power Supply Rejection Ratio, PSRR
Input Referred Noise, IRN
Recovery Time 140 VPP IN, VOUT < 20mVPP
Turn-on Delay Time
Turn-off Delay Time
(3)
, tEN_ON
(3)
, tEN_OFF
Bias Current Switching Time
Propagation Delay Time
(3)
, tDELAY
Clamp Voltage, excludes overshoot
(1)
(2)
(3)
MIN
TYP
MAX
UNIT
Test
Level
B3B2B1 = 111, VIN = 0.5 VPP
10MHz
-78
dBc
B
B3B2B1 = 100, VIN = 0.5 VPP
10MHz
-77
dBc
B
B3B2B1 = 001, VIN = 0.5 VPP
10MHz
-74
dBc
B
B3B2B1 = 111 at 10MHz
-70
dBc
B
B3B2B1 = 100 at 10MHz
-69
dBc
B
B3B2B1 = 001 at 10MHz
-61
dBc
B
B3B2B1 = 111
-68
dBc
B
B3B2B1 = 100
-65
dBc
B
B3B2B1 = 001
-50
dBc
B
B3B2B1 = 111
-76
dBc
B
B3B2B1 = 100
-76
dBc
B
B3B2B1 = 001
-76
dBc
B
B3B2B1 = 111, 1KHz and 1MHz
-64
dBc
B
B3B2B1 = 111
0.91
nV/rtHz
B
B3B2B1 = 100
1.05
nV/rtHz
B
B3B2B1 = 001
1.12
nV/rtHz
B
B3B2B1 = 111
1
µs
B
B3B2B1 = 100
0.5
µs
B
B3B2B1 = 001
0.3
µs
B
B3B2B1 = 000→111
0.6
µs
B
B3B2B1 = 000→100
0.5
µs
B
B3B2B1 = 000→001
0.5
µs
B
B3B2B1 = 111→000
2.4
µs
B
B3B2B1 = 100→000
2.7
µs
B
B3B2B1 = 001→000
2.2
µs
B
B3B2B1 = 001→111
0.7
µs
B
B3B2B1 = 111
1.3
ns
B
B3B2B1 = 100
1.6
ns
B
B3B2B1 = 001
1.7
ns
B
B3B2B1 = 111
1.9
VPP
B
B3B2B1 = 001
1.7
VPP
B
B3B2B1 = 000
1.4
VPP
B
5MHz 1VPP, and 5.01MHz 0.5VPP input.
PSMR is defined as the ratio between carrier 5MHz and side band signals with 1KHz and 1MHz 50mVPP Noise applied on supply pins.
See the timing diagram show in Figure 2.
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INPUT
tEN_ON
tEN_OFF
tDELAY
B3/B2/B1
OUTPUT
Figure 2. Timing Diagram
TYPICAL CHARACTERISTICS
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, VSUB = -5V, RIN = 75Ω, RLOAD = 400Ω;
f = 5MHz, B3B2B1=111, VIN = 0.25VPP, unless otherwise noted.
A typical bench setup is shown in Figure 3.
VP
1 Channel
of TX810
Signal
Source
Test
Equipment
RIN
RLOAD
VN
Figure 3. Typical Test Setup
Bias = 7 mA
300
Unit Amount
80
1.5
Output Amplitude − V
350
100
2
1890 Units,
Bias = 7 mA,
RIN = N/A
250
200
150
100
Input
60
1
40
Output
0.5
20
0
0
-20
-0.5
-40
-1
-60
-1.5
50
-0.85
-0.86
-0.87
-0.88
-0.89
-0.9
-0.91
-0.92
-0.93
-0.94
-0.95
0
Input Amplitude − V
400
-80
-2
-0.5
-100
0
0.5
1
1.5
2
2.5
3
t − Time − ms
Insertion Loss − dB
AC coupling is used between High voltage pulser and TX810. The
input signal is a combination of 0.25Vpp signal followed by a 1-cycle
140Vpp pulse
Figure 4. Insertion Loss Distribution
6
Figure 5. Recovery Time With Small Input Signal
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TYPICAL CHARACTERISTICS (continued)
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, VSUB = -5V, RIN = 75Ω, RLOAD = 400Ω;
f = 5MHz, B3B2B1=111, VIN = 0.25VPP, unless otherwise noted.
100
0.05
Bias = 7 mA,
RLOAD = 50 W
-60
80
-62
60
0.02
40
Input
20
0.01
0
0
-20
-0.01
Output
-0.02
-40
-64
Crosstalk − dBc
0.03
Input Amplitude − V
Output Amplitude − V
0.04
-66
5MHz
-68
-70
10MHz
-60
-0.03
-72
-80
-0.04
-0.05
-5
0
5
10
15
20
-100
30
25
-74
2
1
3
t − Time − ms
4
5
7
6
Bias Current − mA
AC coupling is used between High voltage pulser and TX810. The
input signal is a 1-cycle 140Vpp pulse
Figure 6. Recovery Time Without Signal
Figure 7. Cross-talk vs. Bias Currents vs. Frequency
-60
1.4
-66
-68
-70
5MHz
-72
1.2
Input Referred Noise − nV/√Hz
VIN = 500 mVPP
-64
-74
-76
10MHz
-78
10MHz
1
1MHz
0.8
5MHz
0.6
0.4
0.2
-80
0
1
2
3
4
5
6
7
2
1
3
Bias Current − mA
Figure 8. HD2 vs. Bias Current vs. Frequency
0.3
7
5
0
2
1
-0.1
0
4
0.1
Amplitude − V
3
5
0.2
Trigger Amplitude − V
4
0.1
6
Trigger
Trigger
0.2
Output Amplitude − V
6
5
Figure 9. Input Referred Noise vs. Bias Current vs. Frequency
6
0.3
4
Bias Current − mA
3
0
2
-0.1
1
TX810 Output
-0.2
-0.2
TX810 Output
-2
0
0.5
1
1.5
2
2.5
3
0
-1
-0.3
3.5
4
Trigger Amplitude − V
2nd Harmonic Distortion − dBc
-62
-0.3
-1
0
1
2
3
4
5
6
7
8
t − Time − ms
t − Time − ms
Figure 10. Power On Response Time (0mA to 7mA)
Figure 11. Power Down Response Time (7mA to 0mA)
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TYPICAL CHARACTERISTICS (continued)
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, VSUB = -5V, RIN = 75Ω, RLOAD = 400Ω;
f = 5MHz, B3B2B1=111, VIN = 0.25VPP, unless otherwise noted.
5
0.2
Trigger
0.15
4
0.1
Amplitude − V
0.05
3
0
-0.5
2
-0.1
1
-0.15
TX810 Output
-0.2
0
-0.25
-0.3
-1
0
0.5
1
1.5
2
2.5
3
3.5
4
t − Time − ms
Figure 12. Bias Current Adjustment Response Time (1mA to 7mA)
8
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THEORY OF OPERATION
A typical ultrasound block diagram is shown in Figure 13.
Figure 13. Ultrasound System Block Diagram
A transducer is excited by high voltage pulsers. It converts the electrical energy to mechanical energy. After each
excitation, the transducer sends out ultrasonic wave to medium. Partial ultrasonic wave gets reflected by
inhomogeneous medium and received by the transducer again, i.e. echo signal. Thus, the transducer is a duplex
device on which both high voltage and low voltage signals exist. The transducer can not be connected to
amplifier stages directly; otherwise, the high voltage signal can permanently destroy amplifiers. The TX810, i.e.
T/R switches, is sitting between integrated HV pulser and low noise amplifier (LNA). The main function of TX810
is to isolate the LNA from high-voltage transmitter. TX810 limits the high voltage pulse and let echo signals
reaching amplifier. Therefore, an ideal T/R switch should completely block high voltage signals and maintain all
information from echoes.
The detail architecture of the TX810 is listed in Figure 14.
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VP
D1
D0
D3
D2
D4
D6
D5
1 Channel
of TX810
HV TX
LV RX
D0~D6 is determined by
B1~B3 pins
RLOAD
L
VB
D0
D1
D3
D2
D4
D6
D5
VN
Figure 14. TX810 Block Diagram
TX810 includes four parts: Diode Bridge, bias network, clamp diodes, and logic controller. A decoder is used to
convert 3-bit logic (B1 to B3) input to 7 control signals (D0 to D6) for 7 MOSFET switches. +2.5V to +5V logic
input is level shifted internally to drive the switches. The bias current of the bridge diode is adjusted
proportionally by these switches. When all switches are on, the bias current is 7mA. Each bit difference will
adjust the bias current approximately 1mA. When all switches are off, the TX810 enters the power down mode.
Comparing to discrete T/R switches, TX810 can be shut down and turned on quickly as shown in the typical
characteristics plots. Considering the low duty cycle of ultrasound imaging, significant power saving can be
achieved.
All 6 diodes are high-voltage Schottky diodes to achieve fast recovery time. Following the bridge, a pair of
back-to-back diode limits the output voltage of TX810 to about 2Vpp. Different power/performance combination
can be selected by users. The TX810 is specified to operate at ±5V and VB is biased at 0V. The characteristics
of the T/R switch are mainly determined by bias currents. Lower power can be achieved with lower supply
voltages. Also, Table 1 shows the relationship among bias current, insertion loss, input noise, power
consumption and equivalent resistance.
Table 1. Bias current vs Performance
Test Conditions: VP = 5V, VN = -5V; VB = 0V; RLOAD = 50Ω
10
B3
B2
B1
I (mA)
IL (dB)
IRN (nV/rtHz)
RON (Ω)
0
0
0
0
N/A
N/A
High Impedance
0
0
0
1
1
-7
1.12
62
10
0
1
0
2
-5.6
1.10
45
20
0
1
1
3
-5
1.09
39
30
1
0
0
4
-4.6
1.05
35
40
1
0
1
5
-4.4
0.99
33
50
1
1
0
6
-4.2
0.95
31
60
1
1
1
7
-4.1
0.91
30
70
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APPLICATION INFORMATION
Similar to discrete T/R switch solutions, external components can be used to optimize system performance.
Inductor L and resistor RLOAD before the low voltage receiver amplifier (LVRx) can improve overload recovery
time and reduce reflection. The L acts as a high pass filter thus overshoot or recovery response spikes can be
suppressed to minimal. The L and RLOAD terminate the entire signal path and can reduce reflection; therefore
axial resolution in ultrasound image might be improved. However, the combined impedance of L and RLOAD may
affect the system sensitivity. The insertion loss of T/R switch is determined by the input impedance of receiver
amplifier and RON of the TX810. L also creates a DC path for any offset caused by mismatching.The inductor can
be as low as 10s µH to suppress low frequency signals from transmitter, transducer, multiplexer, and TX810. The
optimization of L and RLOAD is always an important topic for system designers. AC coupling are typically used
between transmitter and T/R switch or T/R switch and amplifier. Thus amplifiers with DC biased inputs will not
interference with T/R switch.
One challenge for integrating multiple channel circuits on a small package is how to reduce cross talk. In
ultrasound systems, acoustic cross talk from adjacent transducer elements is a dominant source. The cross talk
from transducer elements is in a range of -30 to -35dBc for array transducers. Circuit cross talk is usually at least
20dB better than the transducer cross talk. The special considerations were implemented in both TX810 design
and layout. The cross talk among TX810 channels is reduced to below -60 dBc as show in the specification
table.
In ultrasound Doppler applications, modulation effect in system can influence image quality and sensitivity.
Ultrasound system is a complex mixed-signal system with all kinds of digital and analog circuits. Digital signals
and clock signals can contaminate analog signals on system level or on chip level. Nonlinear components, such
as transistors and diodes, can modulate noise and contaminate signals. In Doppler applications, the Doppler
signal frequency could range from 20Hz to >50KHz. Meanwhile, multiple system clocks are also in this range,
such as frame clock, image line clock, and etc. These noise signals could enter chip through ground and power
supply pins. It is important to study the power supply modulation ratio (PSMR) at chip level. Noise signal with
certain frequency and amplitude can be applied on supply pins. Side band signals could be found if modulation
effect exists. The PSMR is expressed as an amplitude ratio between carrier and side band signals. Beside
PSMR, 3rd order intermodulation ratio (IMD3) is a standard specification for mixed-signal ICs. Users can use
IMD3 to estimate the potential artifact Doppler mirror signals. Both specs can be found in the specification table.
The schematic of the basic connection for TX810 is shown in Figure 15. Optional inductors and resistors can be
used at TX810 outputs depending on transducer characteristics as discussed above. Standard decoupling
capacitors 0.1µF should be placed close to power supply pins. The pin out of TX810 is optimized for PCB layout.
All signals are going from left to right straightly.
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TX810
11
TX810
SLLS996A – SEPTEMBER 2009 – REVISED APRIL 2010
www.ti.com
TX CH8
3.3V
RX CH8
5V
0.1uF
0.1uF
Optional
0.1uF
0.1uF
Optional
0.1uF
0.1uF
Optional
TX CH7
0.1uF
OUT7
GND
VP
OUT8
VD
GND
IN8
IN7
TX CH6
GND
RX CH7
IN6
OUT6
GND
GND
OUT5
IN5
NC
NC
NC
0.1uF
TX CH3
B2
B3
IN4
OUT4
GND
GND
IN3
OUT3
VN
VB
GND
IN1
IN2
GND
0.1uF
B1
Pull Down
20K×3
Optional
B2
B3
RX CH4
0.1uF
Optional
0.1uF
Optional
0.1uF
Optional
0.1uF
Optional
RX CH3
OUT2
TX CH4
RX CH5
B1
GND
0.1uF
TX810
PowerPAD
Vsub
(-5V)
OUT1
TX CH5
RX CH6
TX CH2
RX CH2
0.1uF
5V
TX CH1
0.1uF
RX CH1
Figure 15. Schematic of TX810
SPACER
REVISION HISTORY
Changes from Original (September 2009) to Revision A
•
12
Page
Changed From: Product Preview To: Production. The Product Preview was a two page data sheet containing the
front page and the pin out section ........................................................................................................................................ 1
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TX810
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TX810IRHHT
ACTIVE
VQFN
RHH
36
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TX810
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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