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TXS0102
SCES640I – JANUARY 2007 – REVISED OCTOBER 2018
TXS0102 2-Bit Bidirectional Voltage-Level Translator for Open-Drain and Push-Pull
Applications
1 Features
3 Description
•
•
This two-bit non-inverting translator is a bidirectional
voltage-level translator and can be used to establish
digital switching compatibility between mixed-voltage
systems. It uses two separate configurable powersupply rails, with the A ports supporting operating
voltages from 1.65 V to 3.6 V while it tracks the VCCA
supply, and the B ports supporting operating voltages
from 2.3 V to 5.5 V while it tracks the VCCB supply.
This allows the support of both lower and higher logic
signal levels while providing bidirectional translation
capabilities between any of the 1.8-V, 2.5-V, 3.3-V,
and 5-V voltage nodes.
1
•
•
•
•
•
•
•
No Direction-Control Signal Needed
Maximum Data Rates
– 24 Mbps (Push Pull)
– 2 Mbps (Open Drain)
Available in the Texas Instruments NanoStar™
Package
1.65 V to 3.6 V on A Port and 2.3 V to 5.5 V on B
Port (VCCA ≤ VCCB)
VCC Isolation Feature: If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance State
No Power-Supply Sequencing Required: Either
VCCA or VCCB Can Be Ramped First
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– A Port:
– 2500-V Human-Body Model (A114-B)
– 250-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
– B Port:
– 8-kV Human-Body Model (A114-B)
– 250-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
2 Applications
•
•
•
When the output-enable (OE) input is low, all I/Os are
placed in the high-impedance state, which
significantly reduces the power-supply quiescent
current consumption.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TXS0102DCT
SSOP (8)
2.95 mm × 2.80 mm
TXS0102DCU
VSSOP (8)
2.30 mm × 2.00 mm
TXS0102DQE
X2SON (8)
1.40 mm × 1.00 mm
TXS0102DQM
X2SON (8)
1.80 mm × 1.20 mm
TXS0102YZP
DSBGA (8)
1.90 mm × 0.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
I2C / SMBus
UART
GPIO
Typical Application Block Diagram for TXS0102
VCCA
Processor
VCCB
Peripheral
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXS0102
SCES640I – JANUARY 2007 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements: VCCA = 1.8 V ±0.15 V............ 7
Timing Requirements: VCCA = 2.5 V ± 0.2 V ............ 7
Timing Requirements: VCCA = 3.3 V ± 0.3 V ............ 7
Switching Characteristics: VCCA = 1.8 V ± 0.15 V .... 8
Switching Characteristics: VCCA = 2.5 V ± 0.2 V .... 9
Switching Characteristics: VCCA = 3.3 V ± 0.3 V .. 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2018) to Revision I
•
Updated the VIH A-port I/O VCCA value in the Recommended Operating Conditions table From: "1.65 V to 3.6 V", To:
"1.65 V to 1.95 V" .................................................................................................................................................................. 5
Changes from Revision G (January 2018) to Revision H
•
Page
Page
Updated TXS0102 Layout Example diagram ...................................................................................................................... 19
Changes from Revision F (August 2014) to Revision G
Page
•
Changed part number in title of front page graphic from TXS010x to TXS0102 .................................................................. 1
•
Changed value from 8 V to 8000 V in ESD Ratings table...................................................................................................... 4
•
Changed unit from kV to V in ESD Ratings table................................................................................................................... 4
•
Added typical value column in Electrical Characteristics table ............................................................................................. 6
•
Changed part number in title of Figure 10 from TXS01xx to TXS0102................................................................................ 15
•
Added title to TXS0102 Layout Example diagram .............................................................................................................. 19
2
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SCES640I – JANUARY 2007 – REVISED OCTOBER 2018
5 Pin Configuration and Functions
DCT or DCU Package
8-Pin SSOP and VSSOP
Top View
B2
1
8
B1
GND
2
7
VCCB
VCCA
3
6
OE
A2
4
5
A1
DQE or DQM Package
8-Pin X2SON
Top View
VCCA
A1
A2
GND
1
8
2
7
3
6
4
5
VCCB
B1
B2
OE
YZP Package
8-Pin DSBGA
Bottom View
A2
D1
4 5
D2
A1
VCCA
C1
3 6
C2
OE
GND
B1
2 7
B2
VCCB
B2
A1
1 8
A2
B1
Pin Functions
PIN
NAME
TYPE (1)
NO.
DESCRIPTION
DCT, DCU
DQE, DQM
YZP
B2
1
6
A1
I/O
Input/output B. Referenced to VCCB.
GND
2
4
B1
—
Ground
VCCA
3
1
C1
P
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB
A2
4
3
D1
I/O
Input/output A. Referenced to VCCA.
A1
5
2
D2
I/O
Input/output A. Referenced to VCCA.
OE
6
5
C2
I
Output enable (active High). Pull OE low to place all outputs in 3-state
mode. Referenced to VCCA.
VCCB
7
8
B2
P
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V
B1
8
7
A2
I/O
(1)
Input/output B. Referenced to VCCB.
I = input, O = output, I/O = input and output, P = power
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SCES640I – JANUARY 2007 – REVISED OCTOBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage range, VCCA
Supply voltage range, VCCB
Input voltage range, VI (2)
Voltage range applied to any output in the high-impedance or power-off state, VO (2)
Voltage range applied to any output in the high or low state, VO (2) (3)
MIN
MAX
–0.5
4.6
V
V
–0.5
6.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
UNIT
V
V
V
Input clamp current, IIK
VI < 0
–50
mA
Output clamp current, IOK
VO < 0
–50
mA
±50
mA
±100
mA
150
°C
150
°C
Continuous output current, IO
Continuous current through VCCA, VCCB, or GND
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 ESD Ratings
V(ESD)
(1)
(2)
4
Electrostatic
discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins, A Port (1)
±2500
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins, B Port (1)
±8000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
V
250-V Machine Model (A115-A), all pins
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCES640I – JANUARY 2007 – REVISED OCTOBER 2018
6.3 Recommended Operating Conditions
VCCI is the supply voltage associated with the input port. VCCO is the supply voltage associated with the output port.
VCCA
Supply voltage
VCCB
Supply voltage
MIN
MAX
1.65
3.6
V
2.3
5.5
V
VCCA = 1.65 V to 1.95 V
VCCB = 2.3 V to 5.5 V
VCCI – 0.2
VCCI
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
VCCI – 0.4
VCCI
B-port I/Os
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
VCCI – 0.4
VCCI
V
OE input
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
VCCA × 0.65
5.5
V
A-port I/Os
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
0
0.15
V
B-port I/Os
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
0
0.15
V
OE input
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
0
VCCA × 0.35
V
A-port I/Os
push-pull driving
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
10
ns/V
B-port I/Os
push-pull driving
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
10
ns/V
Control input
VCCA = 1.65 V to 3.6 V
VCCB = 2.3 V to 5.5 V
10
ns/V
85
°C
(1)
A-port I/Os
High-level
input voltage
VIH
VIL (2)
Δt/Δv
TA
(1)
(2)
Low-level
input voltage
Input transition
rise or fall rate
UNIT
V
Operating free-air temperature
–40
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
The maximum VIL value is provided to ensure that a valid VOL is maintained. The VOL value is VIL plus the voltage drop across the passgate transistor.
6.4 Thermal Information
TXS0102
THERMAL METRIC
(1)
DCT
DCU
DQE
DQM
YZP
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
182.6
199.1
199.3
239.3
105.8
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
113.3
72.4
26.4
106.7
1.6
°C/W
RθJB
Junction-to-board thermal
resistance
94.9
77.8
78.6
130.4
10.8
°C/W
ψJT
Junction-to-top characterization
parameter
39.4
6.2
5.9
8.2
3.1
°C/W
ψJB
Junction-to-board characterization
parameter
93.9
77.4
78.0
130.2
10.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
VOHA
Port A output
high voltage
IOH = –20 µA
VIB ≥ VCCB – 0.4 V
1.65 V to 3.6 V 2.3 V to 5.5 V
VOLA
Port A output
low voltage
IOL = 1 mA
VIB ≤ 0.15 V
1.65 V to 3.6 V 2.3 V to 5.5 V
VOHB
Port B output
high voltage
1.65 V to 3.6 V 2.3 V to 5.5 V
VOLB
Port B output
low voltage
1.65 V to 3.6 V 2.3 V to 5.5 V
II
Input leakage
current
Ioff
Partial power
down current
IOZ
High-impedance
state output
A or B port
current
ICCA
VCCA supply
current
ICCB
VCCB supply
current
TA = 25°C
MIN
MIN
TYP MAX
VCCA × 0.67
VCCB × 0.67
OE
1.65 V to 3.6 V 2.3 V to 5.5 V
±1
±2
A port
0V
0 V to 5.5 V
±1
±2
B port
0 V to 3.6 V
0V
±1
±2
±1
±2
VI = VO = open
IO = 0
VI = VO = open
IO = 0
V
V
0.4
1.65 V to 3.6 V 2.3 V to 5.5 V
UNIT
V
0.4
1.65 V to VCCB 2.3 V to 5.5 V
2.4
3.6 V
0V
2.2
0V
5.5 V
–1
1.65 V to VCCB 2.3 V to 5.5 V
12
3.6 V
0V
–1
0V
5.5 V
V
µA
µA
µA
1
Combined
supply current
VI = VCCI or GND
IO = 0
1.65 V to VCCB 2.3 V to 5.5 V
CI
Input
capacitance
OE
3.3 V
3.3 V
2.5
Input-to-output
internal
capacitance
A or B port
3.3 V
3.3 V
10
Cio
6
TA = –40°C to +85°C
TYP MAX
ICCA
+
ICCB
(1)
(2)
(3)
(2) (3)
A port
5
6
B port
6
7.5
14.4
µA
3.5
pF
pF
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
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6.6 Timing Requirements: VCCA = 1.8 V ±0.15 V
VCCB = 2.5 V ± 0.2 V
MIN
Data rate
tw
Pulse duration
VCC = 3.3 V ± 0.3 V
MAX
Push-pull driving
Open-drain driving
(data inputs)
VCC = 5 V ± 0.5 V
MAX
MIN
MAX
21
22
24
2
2
2
Open-drain driving
Push-pull driving
(data inputs)
MIN
47
45
41
500
500
UNIT
Mbps
ns
500
6.7 Timing Requirements: VCCA = 2.5 V ± 0.2 V
VCCB = 2.5 V ± 0.2 V
MIN
Data rate
tw
Pulse duration
MAX
Push-pull driving
Open-drain driving
Push-pull driving
(data inputs)
Open-drain driving
(data inputs)
VCC = 3.3 V ± 0.3 V
MIN
VCC = 5 V ± 0.5 V
MAX
MIN
MAX
20
22
24
2
2
2
50
45
41
500
500
UNIT
Mbps
ns
500
6.8 Timing Requirements: VCCA = 3.3 V ± 0.3 V
VCC = 3.3 V ± 0.3 V
MIN
Data rate
tw
Pulse duration
Push-pull driving
VCC = 5 V ± 0.5 V
MAX
Open-drain driving
(data inputs)
MAX
23
24
2
2
Open-drain driving
Push-pull driving
(data inputs)
MIN
43
41
500
500
UNIT
Mbps
ns
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6.9 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tPHL
TEST CONDITIONS
VCCB = 2.5 V ±0.2 V
MIN
MAX
MIN
MAX
MIN
UNIT
Propagation
delay time
low-to-high
output
A-to-B
Propagation
delay time
high-to-low
output
B-to-A
Propagation
delay time
low-to-high
output
B-to-A
ten
Enable time
OE-to-A or B
200
200
200
ns
tdis
Disable time
OE-to-A or B
50
40
35
ns
trA
Input rise
time
A port
rise time
Push-pull driving
3.2
9.5
2.3
9.3
2
7.6
Open-drain driving
38
165
30
132
22
95
Input rise
time
B port
rise time
Push-pull driving
4
10.8
2.7
9.1
2.7
7.6
34
145
23
106
10
58
Input fall time
A port
fall time
Push-pull driving
2
5.9
1.9
6
1.7
13.3
Open-drain driving
4.4
6.9
4.3
6.4
4.2
6.1
Input fall time
B port
fall time
Push-pull driving
2.9
13.8
2.8
16.2
2.8
16.2
Open-drain driving
6.9
13.8
7.5
16.2
7
16.2
tPHL
tPLH
trB
tfA
tfB
tSK(O) Skew (time),
output
Maximum
data rate
8
2.3
Push-pull driving
Open-drain driving
45
Open-drain driving
1.9
Open-drain driving
36
5.3
45
175
2.6
208
1.1
4.4
27
0.7
140
1.2
198
ns
4
ns
0.5
27
0.7
102
0.7
21
22
24
2
2
2
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ns
4.7
4.5
36
10
7.5
4.5
5.3
Channel -to- channel skew
Push-pull driving
260
9.6
6.8
7.1
4.4
Push-pull driving
Open-drain driving
2.4
6.8
Push-pull driving
Open-drain driving
8.8
5.4
MAX
A-to-B
Open-drain driving
5.3
VCCB = 3.3 V ±0.2 V
Propagation
delay time
high-to-low
output
tPLH
Push-pull driving
VCCB = 3.3 V ±0.2 V
ns
ns
ns
ns
ns
ns
Mbps
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6.10 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCCB = 2.5 V ±0.2 V
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
UNIT
A-to-B
tPLH
Propagation
delay time
low-to-high
output
A-to-B
tPHL
Propagation
delay time
high-to-low
output
B-to-A
tPLH
Propagation
delay time
low-to-high
output
B-to-A
ten
Enable time
OE-to-A or B
200
200
200
ns
tdis
Disable time
OE-to-A or B
50
40
35
ns
trA
Input rise
time
A port rise time
trB
Input rise
time
B port rise time
tfA
Input fall time A port fall time
tfB
Input fall time B port fall time
tSK(O)
Skew (time),
output
1.7
Push-pull driving
Open-drain
driving
Push-pull driving
Push-pull driving
36
4.7
170
2.1
206
2.6
4.2
27
140
190
1.2
4
27
103
7.4
2.6
6.6
1.8
5.6
3
149
28
121
24
89
Push-pull driving
3.2
8.3
2.9
7.2
2.4
6.1
Open-drain
driving
35
151
24
112
12
64
Push-pull driving
1.9
5.7
1.9
5.5
1.8
5.3
Open-drain
driving
4.4
6.9
4.3
6.2
4.2
5.8
Push-pull driving
2.2
7.8
2.4
6.7
2.6
6.6
Open-drain
driving
5.1
8.8
5.4
9.4
5.4
10.4
Channel-to-channel skew
0.7
Push-pull driving
Open-drain
driving
0.7
0.7
20
22
24
2
2
2
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ns
ns
1
2.8
Open-drain
driving
ns
4.3
1.6
37
5.8
4.4
3.6
2.5
44
Push-pull driving
250
6
3.8
4.1
3
1.8
Open-drain
driving
2
3.5
43
Open-drain
driving
6.3
3.7
MAX
Propagation
delay time
high-to-low
output
Open-drain
driving
3.2
VCCB = 5 V ± 0.5 V
tPHL
Maximum
data rate
Push-pull driving
VCCB = 3.3 V ±0.3 V
ns
ns
ns
ns
ns
ns
Mbps
9
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6.11 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCB = 3.3 V ±0.2 V
MIN
Push-pull driving
VCCB = 5 V ± 0.5 V
MAX
MIN
UNIT
tPHL
Propagation
delay time
high-to-low
output
A-to-B
tPLH
Propagation
delay time
low-to-high
output
A-to-B
tPHL
Propagation
delay time
high-to-low
output
B-to-A
tPLH
Propagation
delay time
low-to-high
output
B-to-A
ten
Enable time
OE-to-A or B
200
200
ns
tdis
Disable time
OE-to-A or B
40
35
ns
trA
Input rise
time
A port rise time
trB
Input rise
time
B port rise time
tfA
Input fall time A port fall time
tfB
Input fall time B port fall time
tSK(O)
Skew (time),
output
1.3
Push-pull driving
Open-drain driving
Open-drain driving
36
1.4
204
1
124
28
139
165
1
97
3
105
2.3
5.6
1.9
4.8
Open-drain driving
25
116
19
85
Push-pull driving
2.5
6.4
2.1
7.4
Open-drain driving
26
116
14
72
2
5.4
1.9
5
Open-drain driving
4.3
6.1
4.2
5.7
Push-pull driving
2.3
7.4
2.4
7.6
5
7.6
4.8
8.3
Open-drain driving
Channel-to-channel skew
0.7
Push-pull driving
Open-drain driving
0.7
23
24
2
2
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ns
ns
2.6
Push-pull driving
Push-pull driving
ns
3.3
2.5
3
4.6
4.4
2.5
Push-pull driving
Open-drain driving
4.2
3.1
4.2
Push-pull driving
Maximum
data rate
10
Open-drain driving
2.4
MAX
ns
ns
ns
ns
ns
ns
Mbps
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6.12 Typical Characteristics
Figure 1. Low-Level Output Voltage (VOL(Bx)) vs Low-Level
Current (IOL(Bx))
Figure 2. Low-Level Output Voltage (VOL(Bx)) vs Low-Level
Current (IOL(Bx))
Figure 3. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx))
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7 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• PRR 10 MHz
• ZO = 50 W
• dv/dt ≥ 1 V/ns
NOTE
All parameters and waveforms are not applicable to all devices.
VCCI
VCCO
DUT
IN
OUT
1M
15 pF
Figure 4. Data Rate, Pulse Duration, Propagation Delay, Output Rise
And Fall Time Measurement Using A Push-Pull Driver
VCCI
VCCO
DUT
IN
OUT
1M
15 pF
Figure 5. Data Rate, Pulse Duration, Propagation Delay, Output Rise
And Fall Time Measurement Using An Open-Drain Driver
2 x VCCO
S1
50 k
Open
From Output
Under Test
15 pF
50 k
Figure 6. Load Circuit For Enable / Disable Time Measurement
Table 1. Switch Configuration For Enable / Disable Timing
TEST
tPZL
(1)
, tPLZ
S1
(2)
2 × VCCO
tPHZ (2), tPZH (1)
(1)
(2)
12
Open
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
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tw
VCCI
Input
VCCI / 2
VCCI / 2
0V
(1)
All input pulses are measured one at a time, with one transition per measurement.
Figure 7. Voltage Waveforms Pulse Duration
VCCI
VCCI / 2
VCCI / 2
Input
0V
TPLH
TPHL
0.9
VCCO / 2
Output
VOH
VCCO
VCCO / 2
VCCO
0.1
VOL
tr
A.
tf
All input pulses are measured one at a time, with one transition per measurement.
Figure 8. Voltage Waveforms Propagation Delay Times
Output
Control
(low-level
enabling)
VCCA
VCCA / 2
VCCA / 2
0V
tPLZ
Output
Waveform 1(1)
S1 at x VCCO
tPZL
VCCO
VCCO / 2
0.1
VCCO
tPHZ
tPZH
Output
Waveform 2(2)
S1 at GND
VOL
0.9
VOH
VCCO
VCCO / 2
0V
(1)
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
(2)
Waveform 2 is for an output with internal conditions such that the ouput is high, except when disabled by the output
control.
Figure 9. Voltage Waveforms Enable And Disable Times
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8 Detailed Description
8.1 Overview
The TXS0102 device is a directionless voltage-level translator specifically designed for translating logic voltage
levels. The A port is able to accept I/O voltages ranging from 1.65 V to 3.6 V, while the B port can accept I/O
voltages from 2.3 V to 5.5 V. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to
improve the overall data rate. 10-kΩ pullup resistors, commonly used in open-drain applications, have been
conveniently integrated so that an external resistor is not needed. While this device is designed for open-drain
applications, the device can also translate push-pull CMOS logic outputs.
8.2 Functional Block Diagram
VCCA
VCCB
OE
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
10 NŸ
10 NŸ
A1
B1
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
10 NŸ
A2
14
10 NŸ
B2
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8.3 Feature Description
8.3.1 Architecture
The TXS0102 architecture (see Figure 10) is an auto-direction-sensing based translator that does not require a
direction-control signal to control the direction of data flow from A to B or from B to A.
VCCA
VCCB
T1
One
Oneshot
shot
One
Oneshot
shot
R1
10k
T2
R2
10k
Gate Bias
A
B
N2
Figure 10. Architecture of a TXS0102 Cell
These two bidirectional channels independently determine the direction of data flow without a direction-control
signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is how this autodirection feature is realized.
The TXS0102 device is part of TI's "Switch" type voltage translator family and employs two key circuits to enable
this voltage translation:
1) An N-channel pass-gate transistor topology that ties the A-port to the B-port
and
2) Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
For bidirectional voltage translation, pull-up resistors are included on the device for dc current sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at approximately one threshold voltage (VT) above
the VCC level of the low-voltage side. Data can flow in either direction without guidance from a control signal.
The O.S. rising-edge rate accelerator circuitry speeds up the output slew rate by monitoring the input edge for
transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S.
circuits turn on the PMOS transistors (T1, T2) to increase the current drive capability of the driver for
approximately 30 ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high
ac drive by bypassing the internal 10-kΩ pull-up resistors during the low-to-high transition to speed up the signal.
The output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase. To
minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn off
before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width
number provided in the Timing Requirements section of this data sheet.
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Feature Description (continued)
8.3.2 Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or pushpull) drivers that are interfaced to the TXS0102 I/O pins. Since the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup
resistors.
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving
TXS0102 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for
tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.
8.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXS0102 device output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level
affects.
8.3.4 Enable and Disable
The TXS0102 device has an OE input that is used to disable the device by setting OE low, which places all I/Os
in the Hi-Z state. The disable time (tdis) indicates the delay between the time when OE goes low and when the
outputs are disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the oneshot circuitry to become operational after OE is taken high.
8.3.5 Pullup or Pulldown Resistors on I/O Lines
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup
resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O
to VCCA or VCCB (in parallel with the internal 10-kΩ resistors). Adding lower value pull-up resistors will effect VOL
levels, however. The internal pull-ups of the TXS0102 are disabled when the OE pin is low.
8.4 Device Functional Modes
The device has two functional modes, enabled and disabled. To disable the device set the OE input low, which
places all I/Os in a high impedance state. Setting the OE input high will enable the device.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXS0102 device can be used to bridge the digital-switching compatibility gap between two voltage nodes to
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point
topology for interfacing devices or systems operating at different interface voltages with one another. Its primary
target application use is for interfacing with open-drain drivers on the data I/Os such as I2C or 1-wire, where the
data is bidirectional and no control signal is available. The device can also be used in applications where a pushpull driver is connected to the data I/Os, but the TXB0102 might be a better option for such push-pull
applications.
9.2 Typical Application
Figure 11. Typical Application Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3. And make sure the VCCA ≤ VCCB.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.65 to 3.6 V
Output voltage range
2.3 to 5.5 V
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9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
- Use the supply voltage of the device that is driving the TXS0102 device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the
value must be less than the VIL of the input port.
• Output voltage range
- Use the supply voltage of the device that the TXS0102 device is driving to determine the output voltage
range.
- The TXS0102 device has 10-kΩ internal pullup resistors. External pullup resistors can be added to
reduce the total RC of a signal trace if necessary.
• An external pull down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH
as a result of an external pull down resistor.
VOH = VCCx × RPD / (RPD + 10 kΩ)
Where:
• VCCx is the supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor
9.2.3 Application Curves
Figure 12. Level-Translation of a 2.5-MHz Signal
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10 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. The sequencing of each power supply will not damage
the device during the power up operation, so either power supply can be ramped up first. The output-enable (OE)
input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the
high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the
OE input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and VCCB are
fully ramped and stable. The minimum value of the pulldown resistor to ground is determined by the currentsourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, the following common printed-circuit board layout guidelines are
recommended:
• Bypass capacitors should be used on power supplies and should be placed as close as possible to the
VCCA, VCCB pin, and GND pin.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less
than the one-shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at
the source driver.
11.2 Layout Example
LEGEND
Polygonal
VIA to Power Plane
Copper Pour
VIA to GND Plane (Inner Layer)
TXS0102DCTR
1
B2
B1
8
VCCB
7
OE
6
A1
5
To System
0.1 …F
Bypass
Capacitor
2
GND
0.1 µF
3 VCCA
4
A2
To System
Bypass
Capacitor
Keep OE low until VCCA
and VCCB are powered
up
To Controller
To Controller
Figure 13. TXS0102 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, A Guide to Voltage Translation With TXS-Type Translators application note
• Texas Instruments, Factors Affecting VOL for TXS and LSF Auto-bidirectional Translation Devices application
note
• Texas Instruments, Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators application
note
• Texas Instruments, Effects of pullup and pulldown resistors on TXS and TXB devices application note
• Texas Instruments, Introduction to logic application note
• Texas Instruments, TI Logic and Linear Products Guide selection and solution guides
• Texas Instruments, Washing Machine Solutions Guide selection and solution guides
• Texas Instruments, TI Smartphone Solutions Guide selection and solution guides
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TXS0102DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFE
(R, Z)
TXS0102DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFE
(R, Z)
TXS0102DCTT
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFE
(R, Z)
TXS0102DCTTE4
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFE
(R, Z)
TXS0102DCTTG4
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFE
(R, Z)
TXS0102DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(FE, NFEQ, NFER)
NZ
TXS0102DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFER
TXS0102DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(FE, NFEQ, NFER)
NZ
TXS0102DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NFER
TXS0102DQER
ACTIVE
X2SON
DQE
8
5000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
2H
TXS0102DQMR
ACTIVE
X2SON
DQM
8
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
2H
(2H7, 2HR)
(2HG, 2HH)
TXS0102YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
Level-1-260C-UNLIM
-40 to 85
(2H, 2HN)
SNAGCU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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