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TXS0104E
SCES651F – JUNE 2006 – REVISED DECEMBER 2014
TXS0104E 4-Bit Bidirectional Voltage-Level Translator For Open-Drain and Push-Pull
Applications
1 Features
3 Description
•
•
This 4-bit non-inverting translator uses two separate
configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.65 V to 3.6 V. VCCA must be less than
or equal to VCCB. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 2.3 V to
5.5 V. This allows for low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V,
and 5-V voltage nodes.
1
•
•
•
•
•
•
No Direction-Control Signal Needed
Max Data Rates
– 24 Mbps (Push Pull)
– 2 Mbps (Open Drain)
Available in the Texas Instruments NanoFree™
Package
1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B
port (VCCA ≤ VCCB)
No Power-Supply Sequencing Required – VCCA or
VCCB Can Be Ramped First
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– A Port
– 2000-V Human-Body Model (A114-B)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
– B Port
– 15-kV Human-Body Model (A114-B)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
IEC 61000-4-2 ESD (B Port)
– ±8-kV Contact Discharge
– ±10-kV Air-Gap Discharge
2 Applications
Handset
Smartphone
Tablet
Desktop PC
The TXS0104E is designed so that the OE input
circuit is supplied by VCCA.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Device Information(1)
PART NUMBER
TXS0104E
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
BGA (12)
2.00 mm × 2.50 mm
VQFN (14)
3.50 mm × 3.50 mm
DSBGA (12)
1.90 mm × 1.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Transfer Characteristics of an N-Channel
Transistor
Output Voltage (V)
•
•
•
•
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance state.
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VGATE
4.3VV
VGATE ==4.3
VGATE
3.5VV
VGATE ==3.5
VGATE ==2.8
VGATE
2.8VV
VGATE ==2.5
VGATE
2.5VV
VGATE ==2.2
VGATE
2.2VV
0
1
2
3
Input Voltage (V)
4
5
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXS0104E
SCES651F – JUNE 2006 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
5
Absolute Maximum Ratings ..................................... 5
Handling Ratings ...................................................... 5
Recommended Operating Conditions ...................... 6
Thermal Information: GXU, ZXU, and YZT............... 6
Thermal Information: D, PW, and RGY .................... 6
Electrical Characteristics .......................................... 7
Timing Requirements: VCCA = 1.8 V ± 0.15 V .......... 8
Timing Requirements: VCCA = 2.5 V ± 0.2 V ............ 8
Timing Requirements: VCCA = 3.3 V ± 0.3 V ............ 8
Switching Characteristics: VCCA = 1.8 V ± 0.15 V .. 9
Switching Characteristics: VCCA = 2.5 V ± 0.2 V .. 10
Switching Characteristics: VCCA = 3.3 V ± 0.3 V .. 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 13
7.1 Load Circuits ........................................................... 13
7.2 Voltage Waveforms................................................. 14
8
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Trademarks ........................................................... 20
12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2013) to Revision F
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Deleted the Package thermal impedance information from the Absolute max ratings table into the Thermal
Information table. Moved the Tstg row into the new Handling Ratings table. ......................................................................... 5
•
Changed the last 2 rows of MIN MAX (24 MAX and 2 MAX) to the MIN columns, in the first switching characteristics
table ....................................................................................................................................................................................... 9
Changes from Revision D (May 2008) to Revision E
•
2
Page
Deleted the ordering table ..................................................................................................................................................... 1
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SCES651F – JUNE 2006 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
YZT Package
12-Pin DSBGA
Top View
GXU and ZXU Package
12-Pin MICROSTAR JUNIOR
Top View
A
3 2 1
B C
D
C
B
A
4
3
2
1
D and PW Package
14-Pin SOIC
Top View
VCCB
1
14
2
13
3
12
4
11
5
10
6
8
OE
9
7
GND
A1
A2
A3
A4
NC
VCCA
RGY Package
14-Pin VQFN
Top View
B1
B2
B3
B4
NC
VCCA
1
14
VCCB
A1
2
13
B1
A2
3
12
B2
A3
4
11
B3
A4
5
10
B4
NC
GND
6
9
7
8
NC
OE
NOTE: NC - No internal connection
NOTE: NC - No internal connection
Pin Functions: D, PW, or RGY
PIN
TYPE
DESCRIPTION
NAME
NO.
A1
2
I/O
Input/output A1. Referenced to VCCA.
A2
3
I/O
Input/output A2. Referenced to VCCA.
A3
4
I/O
Input/output A3. Referenced to VCCA.
A4
5
I/O
Input/output A4. Referenced to VCCA.
B1
13
I/O
Input/output B1. Referenced to VCCB.
B2
12
I/O
Input/output B2. Referenced to VCCB.
B3
11
I/O
Input/output B3. Referenced to VCCB.
B4
10
I/O
Input/output B4. Referenced to VCCB.
GND
7
S
NC
6
N/A
No connection. Not internally connected.
NC
9
N/A
No connection. Not internally connected.
OE
8
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
VCCA
1
S
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB.
VCCB
14
S
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V.
Thermal
Pad
–
–
For the RGY package, the exposed center thermal pad must be connected to ground
Ground
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SCES651F – JUNE 2006 – REVISED DECEMBER 2014
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Pin Functions: BGA
PIN
TYPE
DESCRIPTION
NAME
NO.
A1
A1
I/O
Input/output A1. Referenced to VCCA.
A2
A2
I/O
Input/output A2. Referenced to VCCA.
A3
A3
I/O
Input/output A3. Referenced to VCCA.
A4
A4
I/O
Input/output A4. Referenced to VCCA.
B1
C1
I/O
Input/output B1. Referenced to VCCB.
B2
C2
I/O
Input/output B2. Referenced to VCCB.
B3
C3
I/O
Input/output B3. Referenced to VCCB.
B4
C4
I/O
Input/output B4. Referenced to VCCB.
GND
B4
S
NC
–
N/A
No connection. Not internally connected.
NC
–
N/A
No connection. Not internally connected.
OE
B3
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
VCCA
B2
S
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB.
VCCB
B1
S
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V.
Ground
Pin Functions: DSBGA
PIN
4
TYPE
DESCRIPTION
NAME
NO.
A1
A3
I/O
Input/output A1. Referenced to VCCA.
A2
B3
I/O
Input/output A2. Referenced to VCCA.
A3
C3
I/O
Input/output A3. Referenced to VCCA.
A4
D3
I/O
Input/output A4. Referenced to VCCA.
B1
A1
I/O
Input/output B1. Referenced to VCCB.
B2
B1
I/O
Input/output B2. Referenced to VCCB.
B3
C1
I/O
Input/output B3. Referenced to VCCB.
B4
D1
I/O
Input/output B4. Referenced to VCCB.
GND
D2
S
NC
–
N/A
No connection. Not internally connected.
NC
–
N/A
No connection. Not internally connected.
OE
C2
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
VCCA
B2
S
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB.
VCCB
A2
S
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V.
Ground
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SCES651F – JUNE 2006 – REVISED DECEMBER 2014
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
MIN
MAX
–0.5
4.6
–0.5
6.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
Supply voltage range
UNIT
V
VI
Input voltage range (2)
VO
Voltage range applied to any output
in the high-impedance or power-off state (2)
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
–50
50
mA
Continuous current through each VCCA, VCCB, or GND
–100
100
mA
(1)
(2)
(3)
(3)
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic
discharge
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins (1)
A Port
2000
V
B Port
15
kV
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
A Port
Machine model (MM)
A Port
1000
B Port
V
200
B Port
(1)
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions (1) (2)
VCCA
VCCA
VCCB
MIN
MAX
1.65
3.6
2.3
5.5
VCCI – 0.2
VCCI
VCCI – 0.4
VCCI
VCCI – 0.4
VCCI
VCCA × 0.65
5.5
0
0.15
Supply voltage (3)
1.65 V to 1.95 V
A-port I/Os
High-level input
voltage
VIH
VCCB
2.3 V to 3.6 V
B-port I/Os
OE input
2.3 V to 5.5 V
1.65 V to 3.6 V
2.3 V to 5.5 V
1.65 V to 3.6 V
2.3 V to 5.5 V
A-port I/Os
Low-level input
voltage
VIL
B-port I/Os
OE input
0
0.15
0
VCCA × 0.35
A-port I/Os, push-pull
driving
Δt/Δv
Input transition
rise or fall rate
TA
Operating free-air temperature
B-port I/Os, push-pull
driving
V
V
V
10
1.65 V to 3.6 V
2.3 V to 5.5 V
10
Control input
(1)
(2)
(3)
UNIT
ns/V
10
–40
85
°C
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
6.4 Thermal Information: GXU, ZXU, and YZT
TXS0104E
THERMAL METRIC (1)
GXU/ZXU (12) (2)
YZT (12)
89.2
RθJA
Junction-to-ambient thermal resistance
132.0
RθJC(top)
Junction-to-case (top) thermal resistance
98.4
0.9
RθJB
Junction-to-board thermal resistance
68.7
14.4
ψJT
Junction-to-top characterization parameter
3.1
3.0
ψJB
Junction-to-board characterization parameter
68.2
14.4
(1)
(2)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Thermal Information: D, PW, and RGY
TXS0104E
THERMAL METRIC (1)
D(14) (1)
PW(14) (2)
RGY(14) (3)
RθJA
Junction-to-ambient thermal resistance
90.4
120.1
56.1
RθJC(top)
Junction-to-case (top) thermal resistance
50.1
49.4
68.8
RθJB
Junction-to-board thermal resistance
45.0
61.8
32.1
ψJT
Junction-to-top characterization parameter
14.4
6.2
3.1
ψJB
Junction-to-board characterization parameter
44.7
61.2
32.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
12.8
(1)
(2)
(3)
6
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
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6.6 Electrical Characteristics
(1) (2) (3)
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
VCCA
VCCB
VOHA
IOH = –20 μA,
VIB ≥ VCCB – 0.4 V
1.65 V to 3.6 V
2.3 V to 5.5 V
VOLA
IOL = 1 mA,
VIB ≤ 0.15 V
1.65 V to 3.6 V
2.3 V to 5.5 V
VOHB
IOH = –20 μA,
VIA ≥ VCCA – 0.2 V
1.65 V to 3.6 V
2.3 V to 5.5 V
VOLB
IOL = 1 mA,
VIA ≤ 0.15 V
1.65 V to 3.6 V
2.3 V to 5.5 V
TA = 25°C
MIN
TYP
TA = 25°C to 85°C
MAX
MIN
MAX
VCCA × 0.8
UNIT
V
0.4
VCCB × 0.8
V
V
0.4
V
II
OE
VI = VCCI or GND
1.65 V to 3.6 V
2.3 V to 5.5 V
–1
1
–2
2
μA
IOZ
A or B port
OE = VIL
1.65 V to 3.6 V
2.3 V to 5.5 V
–1
1
–2
2
μA
1.65 V to VCCB
2.3 V to 5.5 V
2.4
3.6 V
0
2.2
0
5.5 V
–1
1.65 V to VCCB
2.3 V to 5.5 V
12
3.6 V
0
–1
0
5.5 V
1
1.65 V to VCCB
2.3 V to 5.5 V
3.3 V
3.3 V
VI = VO = Open,
IO = 0
ICCA
VI = VO = Open,
IO = 0
ICCB
VI = VO = Open,
IO = 0
ICCA + ICCB
CI
Cio
(1)
(2)
(3)
OE
A port
B port
3.3 V
3.3 V
μA
μA
14.4
μA
2.5
3.5
pF
5
6.5
12
16.5
pF
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
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6.7 Timing Requirements: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse duration
VCCB = 3.3 V
± 0.3 V
MAX
Push-pull driving
Open-drain driving
Data inputs
MAX
MIN
UNIT
MAX
24
24
24
2
2
2
Open-drain driving
Push-pull driving
MIN
VCCB = 5 V
± 0.5 V
41
41
41
500
500
500
Mbps
ns
6.8 Timing Requirements: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse duration
MAX
Push-pull driving
Open-drain driving
Push-pull driving
Open-drain driving
Data inputs
VCCB = 3.3 V
± 0.3 V
MIN
VCCB = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
24
24
24
2
2
2
41
41
41
500
500
500
Mbps
ns
6.9 Timing Requirements: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
MIN
Data rate
tw
8
Pulse duration
Push-pull driving
Open-drain driving
Push-pull driving
Open-drain driving
Data inputs
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VCCB = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
24
24
2
2
41
41
500
500
Mbps
ns
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6.10 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCCB = 2.5 V
± 0.2 V
MIN
Push-pull driving
tPHL
A
B
tPLH
Open-drain
driving
B
A
tPLH
Open-drain
driving
45
ten
OE
A or B
tdis
OE
A or B
trA
A-port rise time
trB
B-port rise time
tfA
A-port fall time
Channel-to-channel skew
6.8
36
5.3
175
4.4
27
140
198
4
0.5
27
200
50
40
200
ns
35
ns
9.3
2
7.6
Open-drain
driving
38
165
30
132
22
95
4
10.8
2.7
9.1
2.7
7.6
34
145
23
106
10
58
2
5.9
1.9
6
1.7
13.3
Open-drain
driving
4.4
6.9
4.3
6.4
4.2
6.1
Push-pull driving
2.9
7.6
2.8
7.5
2.8
8.8
Open-drain
driving
6.9
13.8
7.5
16.2
7
16.2
Open-drain
driving
1
1
24
24
24
2
2
2
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ns
102
2.3
1
ns
4.7
1.2
4.5
36
10
7
4.5
1.1
5.3
45
208
UNIT
5.8
3
9.5
Push-pull driving
Max data rate
260
9.6
3.2
Push-pull driving
tSK(O)
4.7
2.9
Push-pull driving
Open-drain
driving
B-port fall time
8.8
200
Push-pull driving
tfB
MIN MAX
4.4
1.9
Push-pull driving
Open-drain
driving
MIN MAX
6.8
Push-pull driving
tPHL
VCCB = 5 V
± 0.5 V
4.6
2.9
Push-pull driving
Open-drain
driving
MAX
VCCB = 3.3 V
± 0.3 V
ns
ns
ns
ns
Mbps
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6.11 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 2.5 V
± 0.2 V
MIN
Push-pull driving
tPHL
A
B
tPLH
Open-drain driving
A
ten
OE
A or B
tdis
OE
A or B
tPLH
Open-drain driving
43
trA
A-port rise time
trB
B-port rise time
tfA
A-port fall time
tfB
B-port fall time
tSK(O)
Channel-to-channel skew
Max data rate
6.3
250
1.8
4.7
170
6
36
206
3.4
2.1
4.2
27
37
140
1.2
190
4
0.7
27
200
50
40
200
ns
35
ns
2.8
7.4
2.6
6.6
1.8
5.6
Open-drain driving
34
149
28
121
24
89
Push-pull driving
3.2
8.3
2.9
7.2
2.4
6.1
Open-drain driving
35
151
24
112
12
64
Push-pull driving
1.9
5.7
1.9
5.5
1.8
5.3
Open-drain driving
4.4
6.9
4.3
6.2
4.2
5.8
Push-pull driving
2.2
7.8
2.4
6.7
2.6
6.6
Open-drain driving
5.1
8.8
5.4
9.4
5.4
10.4
Push-pull driving
Open-drain driving
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1
1
24
24
24
2
2
2
ns
103
Push-pull driving
1
ns
4.3
1.6
200
5.8
4.4
3.6
2.6
UNIT
MIN MAX
4.1
2.5
44
MAX
VCCB = 5 V
± 0.5 V
3.3
2
3
Push-pull driving
Open-drain driving
MIN
3.5
Push-pull driving
B
MAX
VCCB = 3.3 V
± 0.3 V
3.2
1.7
Push-pull driving
Open-drain driving
tPHL
10
TEST
CONDITIONS
ns
ns
ns
ns
ns
Mbps
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6.12 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCCB = 3.3 V
± 0.3 V
MIN
Push-pull driving
tPHL
A
B
tPLH
Open-drain driving
B
A
ten
OE
A or B
tdis
OE
A or B
tPLH
Open-drain driving
36
trA
A-port rise time
trB
B-port rise time
tfA
A-port fall time
tfB
B-port fall time
tSK(O)
Channel-to-channel skew
Max data rate
204
1
124
28
139
1
165
97
2.6
3
200
40
200
ns
35
ns
2.3
5.6
1.9
4.8
Open-drain driving
25
116
19
85
Push-pull driving
2.5
6.4
2.1
7.4
Open-drain driving
26
116
14
72
2
5.4
1.9
5
Open-drain driving
4.3
6.1
4.2
5.7
Push-pull driving
2.3
7.4
2.4
7.6
5
7.6
4.8
8.3
Open-drain driving
1
Push-pull driving
Open-drain driving
1
24
24
2
2
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ns
105
Push-pull driving
Push-pull driving
ns
3.3
2.5
3
4.6
4.4
2.5
Push-pull driving
Open-drain driving
3.1
1.4
4.2
Push-pull driving
tPHL
4.2
UNIT
MIN MAX
2.4
1.3
Push-pull driving
Open-drain driving
MAX
VCCB = 5 V
± 0.5 V
ns
ns
ns
ns
ns
Mbps
11
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700
700
600
600
Low-Level Output Voltage (mV)
Low-Level Output Voltage (mV)
6.13 Typical Characteristics
500
400
300
200
VCCB = 2.7 V
VCCB = 3.3 V
VCCB = 5 V
100
500
400
300
200
100
VCCB = 3.3 V
VCCB = 5 V
0
0
0
2
4
VCCA = 1.8 V
6
8
10
12
14
Low-Level Current (mA)
16
18
20
0
2
4
D001
VIL(A) = 150 mV
6
8
10
12
14
Low-Level Current (mA)
VCCA = 2.7 V
Figure 1. Low-Level Output Voltage (VOL(Ax))
vs Low-Level Current (IOL(Ax))
16
18
20
D003
VIL(A) = 150 mV
Figure 2. Low-Level Output Voltage (VOL(Ax))
vs Low-Level Current (IOL(Ax))
Low-Level Output Voltage (mV)
700
600
500
400
300
200
100
VCCB = 3.3 V
0
0
2
4
6
8
10
12
14
Low-Level Current (mA)
VCCA = 3.3 V
16
18
20
D002
VIL(A) = 150 mV
Figure 3. Low-Level Output Voltage (VOL(Ax)) vs Low-Level Current (IOL(Ax))
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7 Parameter Measurement Information
7.1 Load Circuits
VCCI
VCCI
VCCO
VCCO
DUT
DUT
IN
IN
OUT
15 pF
OUT
15 pF
1 M
Figure 4. Data Rate, Pulse Duration, Propagation
Delay, Output Rise-Time and Fall-Time
Measurement Using a Push-Pull Driver
1 M
Figure 5. Data Rate, Pulse Duration, Propagation
Delay, Output Rise-Time and Fall-Time
Measurement Using an Open-Drain Driver
2 × VCCO
50 k
From Output
Under Test
15 pF
S1
Open
50 k
TEST
S1
tPZL / tPLZ
(tdis)
2 × VCCO
tPHZ / tPZH
(ten)
Open
Figure 6. Load Circuit for Enable-Time and Disable-Time Measurement
1.
2.
3.
4.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
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7.2 Voltage Waveforms
tw
VCCI
Input
VCCI
VCCI / 2
VCCI / 2
0V
Input
VCCI / 2
VCCI / 2
tPLH
0V
tPHL
VCCO / 2
Output
0.1 × VCCO
tr
Figure 7. Pulse Duration
0.9 × VCCO
VOH
VCCO / 2
VOL
tf
Figure 8. Propagation Delay Times
VCCA
VCCA / 2
OE input
VCCA / 2
0V
tPLZ
tPZL
VOH
Output
Waveform 1
S1 at 2 × VCCO
VCCO / 2
VOH × 0.1
(see Note 2)
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note 2)
VOL
VOH × 0.9
VOH
VCCO / 2
0V
Figure 9. Enable and Disable Times
space
space
1. CL includes probe and jig capacitance.
2. Waveform 1 in Figure 9 is for an output with internal such that the output is high, except when OE is high
(see Figure 6). Waveform 2 in Figure 9 is for an output with conditions such that the output is low, except
when OE is high.
3. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω,
dv/dt ≥ 1 V/ns.
4. The outputs are measured one at a time, with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis.
6. tPZL and tPZH are the same as ten.
7. tPLH and tPHL are the same as tpd.
8. VCCI is the VCC associated with the input port.
9. VCCO is the VCC associated with the output port.
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8 Detailed Description
8.1 Overview
The TXS0104E device is a directionless voltage-level translator specifically designed for translating logic voltage
levels. The A port is able to accept I/O voltages ranging from 1.65 V to 3.6 V, while the B port can accept I/O
voltages from 2.3 V to 5.5 V. The device is a pass gate architecture with edge rate accelerators (one shots) to
improve the overall data rate. 10-kΩ pullup resistors, commonly used in open drain applications, have been
conveniently integrated so that an external resistor is not needed. While this device is designed for open drain
applications, the device can also translate push-pull CMOS logic outputs.
8.2 Functional Block Diagram
VccB
VccA
OE
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
10 kO
10 kO
A1
B1
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
10 kO
10 kO
A2
B2
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
10 kO
10 kO
A3
B3
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
10 kO
10 kO
A4
B4
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8.3 Feature Description
8.3.1 Architecture
The TXS0104E architecture (see Figure 10) does not require a direction-control signal in order to control the
direction of data flow from A to B or from B to A.
VCCB
VCCA
T1
One-shot
One-shot
10 kΩ
T2
10 kΩ
Gate Bias
A
B
Figure 10. Architecture of a TXS01xx Cell
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup
resistor to VCCB. The output one-shots detect rising edges on the A or B ports. During a rising edge, the one-shot
turns on the PMOS transistors (T1, T2) for a short duration which speeds up the low-to-high transition.
8.3.2 Input Driver Requirements
The fall time (tfA, tfB) of a signal depends on the output impedance of the external device driving the data I/Os of
the TXS0104E device. Similarly, the tPHL and maximum data rates also depend on the output impedance of the
external driver. The values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output
impedance of the external driver is less than 50 Ω.
8.3.3 Power Up
During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not
damage the device, so any power supply can be ramped up first.
8.3.4 Enable and Disable
The TXS0104E device has an OE input that disables the device by setting OE low, which places all I/Os in the
high-impedance state. The disable time (tdis) indicates the delay between the time when the OE pin goes low and
when the outputs actually enter the high-impedance state. The enable time (ten) indicates the amount of time the
user must allow for the one-shot circuitry to become operational after the OE pin is taken high.
8.3.5 Pullup and Pulldown Resistors on I/O Lines
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup
resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O
to VCCA or VCCB (in parallel with the internal 10-kΩ resistors).
8.4 Device Functional Modes
The TXS0104E device has two functional modes, enabled and disabled. To disable the device set the OE input
low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device.
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXS0104E device can be used in level-translation applications for interfacing devices or systems operating
at different interface voltages with one another. The TXS0104E device is ideal for use in applications where an
open-drain driver is connected to the data I/Os. The TXS0104E device can also be used in applications where a
push-pull driver is connected to the data I/Os, but the TXB0104 device might be a better option for such pushpull applications.
9.2 Typical Application
1.8 V
3.3 V
0.1 µF
VCCA
0.1 µF
VCCB
OE
1.8-V
System
Controller
3.3-V
System
TXS0104
A1
A2
A3
A4
Data
GND
B1
B2
B3
B4
Data
Figure 11. Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.65 to 3.6 V
Output voltage range
2.3 to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
•
Input voltage range
– Use the supply voltage of the device that is driving the TXS0104E device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value
must be less than the VIL of the input port.
Output voltage range
– Use the supply voltage of the device that the TXS0104E device is driving to determine the output voltage
range.
–
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The TXS0104E device has 10-kΩ internal pullup resistors. External pullup resistors can be added to
reduce the total RC of a signal trace if necessary.
•
An external pull down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a
result of an external pull down resistor.
VOH = VCCx × RPD / (RPD + 10 kΩ)
(1)
where
VCCx is the supply voltage on either VCCA or VCCB
RPD is the value of the external pull down resistor
9.2.3 Application Curve
2 V/div
5V
2V
100 ns/div
VCCA = 1.8 V
VCCB = 5 V
Figure 12. Level-Translation of a 2.5-MHz Signal
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10 Power Supply Recommendations
The TXS0104E device uses two separate configurable power-supply rails, VCCA and VCCB. VCCB accepts any
supply voltage from 2.3 V to 5.5 V and VCCA accepts any supply voltage from 1.65 V to 3.6 V as long as Vs is
less than or equal to VCCB. The A port and B port are designed to track VCCA and VCCB respectively allowing for
low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The TXS0104E device does not require power sequencing between VCCA and VCCB during power-up so the
power-supply rails can be ramped in any order. A VCCA value greater than or equal to VCCB (VCCA ≥ VCCB) does
not damage the device, but during operation, VCCA must be less than or equal to VCCB (VCCA ≤ VCCB) at all times.
The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power
up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled
until VCCA and VCCB are fully ramped and stable. The minimum value of the pulldown resistor to ground is
determined by the current-sourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
To
•
•
•
•
ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the
source driver.
Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements
11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCCA
VCCB
Bypass Capacitors
Pads on signal paths for
potential rise and fall time
adjustments
To Controller
To System
1
VCCA
VCCB 14
2
A1
B1
13
3
A2
B2
12
4
A3
B3
11
To Controller
5
A4
B4
10
To System
To Controller
6
NC
NC
9
To System
7
GND
OE
8
To Controller
To System
Keep OE low until VCCA and
VCCB are powered up
Figure 13. TXS0104E Layout Example
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12 Device and Documentation Support
12.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TXS0104ED
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXS0104E
TXS0104EDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXS0104E
TXS0104EDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXS0104E
TXS0104EDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXS0104E
TXS0104EPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YF04E
TXS0104EPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YF04E
TXS0104ERGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YF04E
TXS0104ERGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YF04E
TXS0104EYZTR
ACTIVE
DSBGA
YZT
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(2HN ~ 2N ~ 2N7)
TXS0104EZXUR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZXU
12
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
YF04E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TXS0104E :
• Automotive: TXS0104E-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Nov-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TXS0104EDR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
D
14
2500
330.0
16.4
6.5
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.0
2.1
8.0
16.0
Q1
TXS0104EPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TXS0104ERGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
TXS0104EYZTR
DSBGA
YZT
12
3000
180.0
8.4
1.49
1.99
0.75
4.0
8.0
Q2
TXS0104EZXUR
BGA MI
CROSTA
R JUNI
OR
ZXU
12
2500
330.0
8.4
2.3
2.8
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Nov-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXS0104EDR
SOIC
D
14
2500
367.0
367.0
38.0
TXS0104EPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TXS0104ERGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
TXS0104EYZTR
DSBGA
YZT
12
3000
182.0
182.0
20.0
TXS0104EZXUR
BGA MICROSTAR
JUNIOR
ZXU
12
2500
336.6
336.6
28.6
Pack Materials-Page 2
D: Max = 1.89 mm, Min = 1.83 mm
E: Max = 1.39 mm, Min = 1.33 mm
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