TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER AND LDO
VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING
FEATURES
1
•
Level Translator
– VCCA Range of 1.1 V to 3.6 V
– Fast Propagation Delay (4 ns Max When
Translating Between 1.8 V and 2.9 V)
Low-Dropout (LDO) Regulator
– 200-mA LDO Regulator With Enable
– 2.9-V Output Voltage
– 3.05-V to 5.5-V Input Voltage Range
– Very Low Dropout: 200 mV at 200 mA
•
•
•
ESD Protection Exceeds JESD 22 (A Port)
– 2000-V Human-Body Model (A114-B)
– 1000-V Charged-Device Model (C101)
±8-kV Contact Discharge IEC 61000-4-2 ESD
(B Port)
YFP PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
1
1 2 3 4
A
B
C
D
E
2
3
4
A
DAT2A
VCCA
WP/CD
DAT2B
B
DAT3A
VBATT
VCCB O/P
DAT3B
C
CMDA
GND
GND
CMDB
D
DAT0A
CLKA
CLKB
DAT0B
E
DAT1A
CLK-f
EN
DAT1B
DESCRIPTION/ORDERING INFORMATION
The TXS0206-29 is a complete solution for interfacing microprocessors with MultiMediaCards (MMCs), secure
digital (SD) cards, and Memory Stick™ cards. It is comprised of a high-speed level translator, a low-dropout
(LDO) voltage regulator, IEC level ESD protection, and EMI filtering circuitry.
The voltage-level translator has two supply voltage pins. VCCA can be operated over the full range of 1.1 V to
3.6 V. VCCB is set at 2.9 V and is supplied by an internal LDO. The integrated LDO accepts input voltages from
3.05V to as high as 5.5 V and outputs 2.9 V, 200 mA to the B-side circuitry and to the external memory card. The
TXS0206-29 enables system designers to easily interface low-voltage microprocessors to memory cards
operating at 2.9 V.
Memory card standards recommend high-ESD protection for devices that connect directly to the external memory
card. To meet this need, the TXS0206-29 incorporates ±8-kV Contact Discharge protection on the card side.
Since memory cards are widely used in mobile phones, PDAs, digital cameras, personal media players,
camcorders, set-top boxes, etc. Low static power consumption and small package size make the TXS0206-29 an
ideal choice for these applications. The TXS0206-29 is offered in a 20-bump wafer chip scale package (WCSP).
This package has dimensions of 1.96 mm × 1.56 mm, with a 0.4-mm ball pitch for effective board-space savings
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE
WCSP – YFP (Pb-free)
(2)
Tape and reel
ORDERABLE PART NUMBER
TXS0206-29YFPR
TOP-SIDE MARKING (3)
___3V2
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
The actual top-side marking has three preceding characters to denote year, month, and sequence code.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
REFERENCE DESIGN
VCCA
VCCB
VCCB
C3
0.1 μF
U1A
C4
0.1 μF
C1
0.1 μF
J1
U2
VDDA
A2
VCCA
DAT0
D1
DAT0A
DAT1
E1
DAT1A
DAT2
DAT3
CMD
CLK
CLKin
GND
WP/CD
A1
VCCB O/P
D4 DAT0B
DAT0B
DAT1B E4 DAT1B
DAT2B A4 DAT2B
DAT3B B4 DAT3B
DAT2A
B1
DAT3A
C1
CMDA
D2
CLKA
E2
CLK-f
C2
DAT2B
DAT3B
CMDB
B3
CLKB
DAT0B
DAT1B
C4 CMDB
CMDB
D3 CLKB
CLKB
CD
GND
C3
GND
Processor
SD/SDIO MMC
WP/CD
A3
WP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
DAT2
DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
WP/CD (Physical)
CD (Physical)
GND
GND
WP (Physical)
54794-0978
SD/SDIO
CardConnector
TXS0206-29
WP/CD
Figure 1. Interfacing With SD/SDIO Card
ESD – ±8-kV Contact Discharge
ESD – 2 kV
1.8 V
CPU
A Side
B Side
2.9 V
CLK
CLK
Feedback CLK
CMD
CMD
Data 0–3
Data 0–3
EN
WP, CD
Level-Shifter
Integrated
ASIP
EMI Filter
Antenna
Pins 10, 11
MMC,
SD Card, or
MS Card
WP, CD 1.8-V Pullup
Integrated PSU
2.9 V, 200 mA
WP, CD
Integrated Pullup/Pulldown Resistors
Figure 2. Typical Application Circuit
2
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Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
Table 1. LOGIC TABLE
EN
LDO
TRANSLATOR I/Os
L
Disabled
Disabled, pulled to VCCA, VCCB O/P through R1 and R2
at 70kΩ pullup resistors respectively
H
Active
Active
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NO.
NAME
A1
DAT2A
I/O
A2
VCCA
Power
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A3
WP/CD
Output
Connected to write protect on the mechanical connector. The WP pin has an internal 100-kΩ pullup
resistor to VCCA.
A4
DAT2B
I/O
Data bit 2 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
B1
DAT3A
I/O
Data bit 3 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).
B2
VBATT
Input
B3
VCCB O/P
Output
B4
DAT3B
I/O
Data bit 3 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
C1
CMDA
I/O
Command bit connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note
A).
C2,
C3
GND
C4
CMDB
D1
D2
Data bit 2 connected to host. Referenced to VCCA. Includes R1 pullup resistor to VCCA (see Note A).
LDO input voltage from Battery-Supply
LDO output voltage and B-port supply voltage. VCCBO/P powers all B-port I/Os.
Ground
I/O
Command bit connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
DAT0A
I/O
Data bit 0 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).
CLKA
Input
D3
CLKB
Output
D4
DAT0B
I/O
Data bit 0 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
E1
DAT1A
I/O
Data bit 1 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).
E2
CLK-f
Output
E3
EN
Input
Enable/disable control. Pull EN low to place all outputs in Hi-Z state and to disable the LDO.
Referenced to VCCA.
E4
DAT1B
I/O
Data bit 1 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
Clock signal connected to host. Referenced to VCCA.
Clock signal connected to memory card. Referenced to VCCBO/P.
Clock feedback to host for resynchronizing data to a processor. Leave unconnected if not used.
Copyright © 2009, Texas Instruments Incorporated
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TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
VCCA
VCCB
EN
(see Note B)
CLKA
CLKB
CLK-f
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
CMDA
CMDB
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
DAT0A
DAT0B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
DAT1A
DAT1B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
R2
(see Note A)
One-Shot
R1
(see Note A)
Translator
One-Shot
DAT2A
DAT2B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
DAT3A
DAT3B
Gate Control
One-Shot
Translator
One-Shot
VCCA
100 kW
WP/CD
A.
R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port as follows:
R1 and R2 = 40 kΩ when a logic level low is applied to the A port or B port.
R1 and R2 = 4 kΩ when a logic level high is applied to the A port or B port.
R1 and R2 = 70 kΩ when the port is deselected (or in High-Z or 3-state).
B.
EN controls all output buffers. When EN = low, all outputs are Hi-Z.
Figure 3. Logic Diagram
4
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Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
VCCB
R7
R8
R9
R10 R11
HOST
CARD
R1
CLKB
CLK
R2
CMD
CMDB
R3
Data0
DAT0B
R4
DAT1B
Data1
R5
DAT2B
Data2
R6
Data3
DAT3B
GND
GND
RESISTORS
BIDIRECTIONAL ZENER DIODES
R1, R2, R3, R4, R5, R6
40 Ω
Vbr min
14 V at 1 mA
Tolerance
±20%
Line capacitance
10-kΩ value. The impact of adding too heavy a pulldown resistor (i.e.
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