TXS02326A
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SCES830A – MAY 2012 – REVISED AUGUST 2013
DUAL-SUPPLY 2:1 SIM CARD MULTIPLEXER/TRANSLATOR
WITH AUTOMATIC DETECTION AND SLOT DEDICATED DUAL LDO
Check for Samples: TXS02326A
FEATURES
1
•
•
•
RGE PACKAGE
(TOP VIEW)
SDA
SCK
CLK
VDDIO
GND
OE
•
Level Translator
– VDDIO Range of 1.7-V to 3.3-V
Low-Dropout (LDO) Regulator
– 50-mA LDO Regulator With Enable
– 1.8-V or 2.95-V Selectable Output Voltage
– 2.3-V to 5.5-V Input Voltage Range
– Very Low Dropout: 100 mV (Max) at 50 mA
Control and Communication Through I2C
Interface With Baseband Processor
ESD Protection Exceeds JESD 22
– 2500-V Human-Body Model (A114-B)
– 6000-V Human-Body Model (A114-B) on
VSIM1, SIM1CLK, SIM1I/O, SIM1RST, VSIM2,
SIM2CLK, SIM2I/O, SIM2RST
– 1000-V Charged-Device Model (C101)
Package
– 24-Pin QFN (4 mm x 4 mm)
IRQ
RSTX
SDN
BSI
SIM2CLK
SIM2I/O
1
24 23 22 21 20 19
18
2
17
3
4
Exposed
Thermal Pad
16
15
5
14
6
13
7 8 9 10 11 12
SIMI/O
SIMCLK
SIMRST
NC
SIM1CLK
SIM1I/O
SIM2RST
VSIM2
VBAT
GND
VSIM1
SIM1RST
•
Note: The Exposed Thermal Pad must be
connect to Ground.
DESCRIPTION/ORDERING INFORMATION
The TXS02326A is a complete dual-supply standby Smart Identity Module (SIM) card solution for interfacing
wireless baseband processors with two individual SIM subscriber cards to store data for mobile handset
applications. It is a custom device which is used to extend a single SIM/UICC interface to support two
SIMs/UICCs.
The device complies with ISO/IEC Smart-Card Interface requirements as well as GSM and 3G mobile standards.
It includes a high-speed level translator capable of supporting Class-B (2.95-V) and Class-C (1.8-V) interfaces;
two low-dropout (LDO) voltage regulators with output voltages that are selectable between 2.95-V Class-B and
1.8-V Class-C interfaces; an integrated "fast-mode" 400 kb/s "slave" I2C control register interface, for
configuration purposes; and a 32-kHz clock input, for internal timing generation. The TXS02326A also includes a
shutdown input and a comparator input that detects battery pack removal to safely power-down the two SIM
cards. The shutdown input and comparator input are equipped with two programmable debounce counter (i.e.
BSI input and SDN input) circuits realized by an 8 bit counter.
The voltage-level translator has two supply voltage pins. VDDIO sets the reference for the baseband interface
and can be operated from 1.7-V to 3.3-V. VSIM1 and VSIM2 are programmed to either 1.8-V or 2.95-V, each
supplied by an independent internal LDO regulator. The integrated LDO accepts input battery voltages from 2.3V to 5.5-V and outputs up to 50 mA to the B-side circuitry and external Class-B or Class-C SIM card.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TXS02326A
SCES830A – MAY 2012 – REVISED AUGUST 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
VBAT
SCK
SDA
I2C
Control
Logic
LDO
VSIM1
SIM1RST
SIMRST
SIM1CLK
SIMCLK
Translator
VCC
GND
Reset
VPP
CLK
I/O
NC
NC
SIM1I/O
SIMI/O
Baseband
3-V or 1.8-V
SIM Card
VDDIO
VCC
RSTX
LDO
IRQ
VSIM2
SIM2RST
CLK
3-V or 1.8-V
SIM Card
VCC
GND
Reset
VPP
CLK
I/O
NC
NC
SIM2CLK
BSI
Translator
OE
SIM2I/O
GND
SDN
TXS02326A
Figure 1. Interfacing With SIM Card
2
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TERMINAL FUNCTIONS
NAME
TYPE (1)
POWER
DOMAIN
1
IRQ
I/O
VDDIO
Interrupt to baseband. This signal is used to set the I2C address.
2
RSTX
I
VDDIO
Active-low reset input from baseband
3
SDN
I
VDDIO
Power down SIM2; for example, from switch
NO.
(1)
DESCRIPTION
4
BSI
I
VDDIO
Analog signal from battery. This input accepts input voltages up to 3 V.
5
SIM2CLK
O
VSIM2
SIM2 clock
6
SIM2I/O
I/O
VSIM2
SIM2 data
7
SIM2RST
O
VSIM2
SIM2 reset
8
VSIM2
O
VSIM2
1.8 V/2.95 V supply voltage to SIM2
9
VBAT
P
VBAT
Battery power supply
10
GND
G
11
VSIM1
O
VSIM1
1.8 V/2.95 V supply voltage to SIM1
12
SIM1RST
O
VSIM1
SIM1 reset
13
SIM1I/O
I/O
VSIM1
SIM1 data
14
SIM1CLK
O
VSIM1
SIM1 clock
15
NC
16
SIMRST
I
VDDIO
UICC/SIM reset from baseband
17
SIMCLK
I
VDDIO
UICC/SIM clock
18
SIMI/O
I/O
VDDIO
UICC/SIM data
19
OE
I
VDDIO
UICC/SIM data direction from baseband
20
GND
G
21
VDDIO
P
VDDIO
1.8-V power supply for device operation and I/O buffers toward baseband
22
CLK
I
VDDIO
32-kHz clock
23
SCK
I
VDDIO
I2C clock
24
SDA
I/O
VDDIO
I2C data
Ground
No connect
G = Ground, I = Input, O = Output, P = Power
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Table 1. Register Overview
REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
BYTE
(HEX)
0
0
0
1
0
0
1
0
00h
Device
hardware
revision
information
R
0001 0010
0
0
0
0
0
0
0
0
01h
Software
revision
information
R
0000 0000
Battery
Removal
Interrupt
Status
Battery
Status
SDN
Interrupt
Status
SDN
Status
04h
Status
Register
R
0000 0000
SIM1
Voltage
Select
SIM1
LDO
Enable/
Disable
08h
SIM
Interface
Control
Register
R/W
0000 0000
BSI Debounce Counter Value
0Ah
BSI Input
Debounce
Counter
R/W
0000 0100
SDN Debounce Counter Value
0Bh
SDN Input
Debounce
Counter
R/W
0000 0100
Reserved / Not Supported
0Ch
Reserved
R/W
0000 0000
0Dh
External
Clock
Control
R/W
0000 0000
0Eh
Device
Control
Register
R/W
0000 0000
10h-14h
Devicespecific
testing
R/W
xxxx xxxx
15h
General
purpose
R/W
0000 0000
SIM2 Interface
Status
SIM2 Interface
Status
SIM1 Interface
Status
SIM2
Voltage
Select
Clock
Source
Select
SDN
SDN
Detection
Level
Behavior Detection
control
Select
SIM2
LDO
Enable/
Disable
Clock Control (Reserved)
SDN
Interrupt
Enable/
Disable
Battery
BSI
BSI
Removal
Detection
Level
Interrupt
Behavior Detection
Enable/
Control
Select
Disable
Reserved
4
SIM1 Interface
Status
OE
Direction
Control
SDN
Pulldown
Enable/
Disable
OE
Control
Select
SDN
Pull-up
Enable/
Disable
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REGISTER
READ
OR
WRITE
POWER-UP
DEFAULT
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Table 2. Device Hardware Revision Register (00h)
Device HW Driver
Register
Bits(s)
Type (R/W)
7:0
R
HW identification
(1)
Description
This register contains the manufacturer and device ID (1) (value to be
specified by the manufacturer)
The manufacturer ID part of this data shall remain unchanged when the HW revision ID is updated. The manufacturer ID shall uniquely
identify the manufacturer. The manufacturer ID is encoded on the MSB nibble.
Table 3. Device Software Revision Register (01h)
Device SW Driver
Register
Bits(s)
Type (R/W)
7:0
R
SW Driver Version
Description
This register contains information about the SW driver required for this
device. This information shall only be updated when changes to the
device requires SW modifications. Initial register value is 00h
Table 4. Status Register (04h)
Status Register
Bits(s)
Type (R/W)
SDN Status
0
R
SDN signal state captured at the input pin
'0' SDN signal at GND
'1' SDN signal at VDDIO level
SDN Interrupt
1
R
SDN interrupt status
'0' No interrupt
'1' Interrupt occurred, (the read operation will automatically clear this bit)
Battery Status
2
R
'0' Battery present
'1' Battery not present, i.e. debounce counter expired
Battery Removal Interrupt
3
R
Battery removal interrupt status
'0' No interrupt
'1' Interrupt occurred, (the read operation will automatically clear this bit)
R
Status of SIM1 interface
'00' Powered down with pull-downs activated
'01' Isolated with pull-downs deactivated
'10' Powered with pull downs activated
'11' Active with pull downs deactivated
R
Status of SIM2 interface
'00' Powered down with pull-downs activated
'01' Isolated with pull-downs deactivated
'10' Powered with pull downs activated
'11' Active with pull downs deactivated
SIM1 Interface Status [1:0]
SIM2 Interface Status [1:0]
(1)
5:4 (1)
7:6 (1)
Description
The content of bits 5:4 and 7:6 reflects the value written to the state bits in the SIM Interface control register 3:2 and 7:6 respectively
and the setting of the regulator bits in the SIM interface control register 0 and 4 respectively.
Table 5. State and Status Bit Mapping
SIM Interface Control Register
(08h)
SIM1 interface state bits 3:2
SIM2 interface state bits 7:6
SIM Interface Control Register
(08h)
SIM1 regulator control bit 0
SIM2 regulator control bit 4
'00' Powered down state with pulldowns activated
'0' Regulator is off, regulator output is '00' Powered down with pulldowns
pulled down
activated
'00' Powered down state with pulldowns activated
'1' Regulator is powered on, regulator '10' Powered with totem pole pulloutput pull-down is released
downs
'01' Isolated state with pulldowns
deactivated
'0' Regulator is off, regulator output is '00' Powered down with pulldowns
pulled down
activated
'01' Isolated state with pulldowns
deactivated
'1' Regulator is powered on, regulator '01' Isolated with pull-downs
output pull-down is released
deactivated
'10' Not allowed
'0' Regulator is off, regulator output is '00' Powered down with pulldowns
pulled down
activated
SIM Status Register (04h)
SIM1 status bits 5:4
SIM2 status bits 7:6
Comment
The interface can
only be in isolated
state when the
interface is powered
This combination
shall not be used. If
used the status bit
coding is as specified
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Table 5. State and Status Bit Mapping (continued)
SIM Interface Control Register
(08h)
SIM1 interface state bits 3:2
SIM2 interface state bits 7:6
SIM Interface Control Register
(08h)
SIM1 regulator control bit 0
SIM2 regulator control bit 4
'10' Not allowed
'1' Regulator is powered on, regulator '10' Powered with pull downs
output pull-down is released
activated
This combination
shall not be used. If
used the status bit
coding is as specified
'11' Active state with pull-downs
deactivated
'0' Regulator is off, regulator output is '00' Powered down with pulldowns
pulled down
activated
The interface can
only be active if it is
powered
'11' Active state with pull-downs
deactivated
'1' Regulator is powered on, regulator '11' Active with pull-downs
output pull-down is released
deactivated
SIM Status Register (04h)
SIM1 status bits 5:4
SIM2 status bits 7:6
Table 6. SIM Interface Control Register (08h) (1)
Status
Register
Bit(s)
Comment
(2)
Type
Description
(R/W)
SIM1
Regulator
Control
0
R/W
'0' Regulator is off, regulator output is pulled down
'1' Regulator is powered on, regulator output pull-down is released
SIM1
Regulator
Voltage
Selection
1
R/W
'0' 1.8 V
'1' 2.95 V
Status of SIM1 interface
'00' state is dependent on bit 0:
SIM1
Interface
State [1:0]
3:2
R/W
If bit 0 = '0', then powered down state with pull-downs activated
Pull down resistor active
If bit 0 = '1', then isolated state with pull-downs deactivated
Totem pole pull down
'01' Isolated state with pull-downs deactivated
Output latched at previous state driven
by totem pole output
'10' Not allowed
Not allowed
'11' Active state with pull-downs deactivated
Outputs follow the inputs
SIM2
Regulator
Control
4
R/W
'0' Regulator is off, regulator output is pulled down
'1' Regulator is powered on, regulator output pull-down is released
SIM2
Regulator
Voltage
Selection
5
R/W
'0' 1.8 V
'1' 2.95 V
Status of SIM2 interface
'00' State is dependent on bit 4:
SIM2
Interface
State [1:0]
(1)
(2)
6
7:6
R/W
If bit 4 = '0', then powered down state with pull-downs activated
Pull down resistor active
If bit 4 = '1', then isolated state with pull-downs deactivated
Totem pole pull down
'01' Isolated state with pull-downs deactivated
Output latched at previous state driven
by totem pole output
'10' Not allowed
Not allowed
'11' Active state with pull-downs deactivated
Outputs follow the inputs
Reset value: 00h
The state '10', on bits 3:2 and 7:6, is not prevented by HW but shall never be set by SW. State '10' means that the interface is powered
with the pull-downs active, this state correspond to state '00' with the regulator being switched on. Setting the state to '10' does not have
any impact on the corresponding regulator bit setting. The regulator control bits do not impact the state bits in this register. The regulator
control bits however do impact the status bits in the status register.
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Table 7. Battery Presence Detection Debounce Counter (0Ah) (1)
BSI Debounce Counter
Debounce Counter Value
[7:0]
(1)
(2)
Bits(s)
Type (R/W)
7:0
R/W
Description
This register contains the BSI input debounce counter value. The value
00h means that the counter is not used, i.e. no debounce.
Reset value: 04h
Updating the register causes the counter to restart with the new value if the counter is counting when the register is updated. The new
value shall take affect no later than one clock cycle (32 KHz) after the register has been updated.
Table 8. SDN Input Debounce Counter (0Bh) (1)
SDN Debounce Counter
Debounce Counter Value
[7:0]
(1)
(2)
(2)
Bits(s)
Type (R/W)
7:0
R/W
(2)
Description
This register contains the SDN input debounce counter value. The value
00h means that the counter is not used, i.e. no debounce.
Reset value: 04h
Updating the register causes the counter to restart with the new value if the counter is counting when the register is updated. The new
value shall take affect no later than one clock cycle (32 KHz) after the register has been updated.
Table 9. External Clock Control (0Dh) (1)
Clock Control Register
Clock Control
Clock Source Select
(1)
Bits(s)
Type (R/W)
6:0
R/W
Description
Reserved
7
R/W
'0' Internal clock source used
'1' External clock source CLK (supplied on pin 22 used)
Reset value: 00h
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Table 10. Device Control Register (0Eh) (1)
Clock Control Register
Bits(s)
Type (R/W)
Description
OE Control
0
R/W
‘0’ OE is not used to control the data direction on the selected SIM I/O
and the base band I/O
‘1’ OE controls the data direction, see below
OE Direction Control
1
R/W
‘0’ OE input = ‘0’ data direction Base band -> SIM
OE input = ‘1’ data direction SIM -> base band
‘1’ OE input = ‘0’ data direction SIM -> base band
OE input = ‘1’ data direction Base band -> SIM
Battery Removal Interrupt
2
R/W
‘0’ Battery removal interrupt disabled
‘1’ Battery removal detected causes interrupt on IRQ (interrupt sets b3 in
the status register)
BSI Level Detection
3
R/W
BSI detection level
‘0’ 1.2V
‘1’ 1.65V
BSI Detection Control
4
R/W
BSI detection behavior
‘0’ Battery not present causes automatic power down of both SIM
interfaces
‘1’ Battery not present doesn’t cause automatic power down
SDN Detection Interrupt
5
R/W
‘0’ SDN detection interrupt disabled
‘1’ SDN detected causes interrupt on IRQ (interrupt sets b1 in the status
register)
SDN Detection Level
6
R/W
SDN input active level
‘0’ SDN is active low
i.e. automatic shutdown occurs when debounced SDN is low.
‘1’ SDN is active high
i.e. automatic shutdown occurs when debounced SDN is high
SDN Detection Control
7
R/W
Disable automatic power down upon SDN detection
‘0’ SDN detection causes automatic power down of SIM2 interface
‘1’ SDN detection doesn’t cause automatic power down of SIM2 interface
(1)
Reset value: 00h
Table 11. General Purpose Register (15h) (1)
Function
Bit(s)
Type (R/W)
SDN pull-up control
0
R/W
'0' SDN input pull-up enabled
'1' SDN input pull-up disabled
SDN pull-down control
1
R/W
'0' SDN pull-down disabled
'1' SDN pull-down enabled
7:2
R/W
RFU
(1)
8
Description
The RFU bits shall allow for the write operation to complete but shall read as '0'. The SW should write '0' into these locations, reset
value.
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SCES830A – MAY 2012 – REVISED AUGUST 2013
BASIC DEVICE OPERATION
The TXS02326A is controlled through a standard I2C interface reference to VDDIO. It is connected between the
two SIM card slots and the SIM/UICC interface of the baseband. The device uses VBAT and VDDI/O as supply
voltages. The supply voltage for each SIM card is generated by an on-chip low drop out regulator. The interface
between the baseband and the TXS02326A is reference to VDDIO while the interface between the TXS02326A
and the SIM card is referenced to the LDO output of either VSIM1 or VSIM2 depending on which slot is being
selected. The VDDIO on the baseband side normally does not exceed 1.8V, thus voltage level shifting is needed
to support a 3V SIM/UICC interface (Class B).
The TXS02326A has two basic states, the reset and operation state. The baseband utilizes information in the
status registers to determine how to manipulate the control registers to properly switch between two SIM cards.
These fundamental sequences are outlined below and are to help the user to successfully incorporate this device
into the system.
DEVICE ADDRESS
The address of the device is shown below:
Slave Address
0
1
1
1
1
0
IRQ
R/W
Address Reference
IRQ@ Reset
R/W
Slave Address
0
0 (W)
120 (decimal), 78(h)
0
1 (R)
121 (decimal), 79(h)
1
0 (W)
122 (decimal), 7A(h)
1
1 (R)
123 (decimal), 7B(h)
RESET STATE
In the reset state the device settings are brought back to their default values and any SIM card that has been
active is deactivated. After reset, neither of the UICC/SIM interfaces is selected. The active pull-downs at the
UICC/SIM interface are automatically activated. To ensure the system powers up in an operational state, device
uses an internal 32 KHz clock for internal timing generation. After power up, the system has the option to
continue to utilize the internal clock or select an external clock source. This clock source is selectable by the
Clock Source Select I2C register bit.
• Power up the TXS02326A by asserting VBAT to enter the operation state
• I2C Interface becomes active with the VDD_I/O supply
RESET summary:
• Any pending interrupts are cleared
• I2C registers are in the default state
• BSI and SDN counter value in the registers are set to four clock cycles or “0000 0100”
• Both on chip regulators are set to 1.8V and disabled
• All SIM1 and SIM2 signals are pulled to GND
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SETTING UP THE SIM INTERFACE
The TXS02326A supports both Class C (1.8V) or Class B (2.95V) SIM cards. In order to support these cards
types, the interface on the SIM side needs to be properly setup. After power up, the system should default to
SIM1 card. The following sequence outlines a rudimentary sequence of preparing the SIM1 card interface:
• Configure the SIM1 regulator to 1.8V by asserting B1 = 0 in the SIM Interface Control Register (08h). The
system by default should start in 1.8V mode.
• Configure the OE signal by asserting B0 = 0 in the Device Control Register (0Eh). The default value
essentially disables the OE pin and the device is configured as an auto direction translator.
• The baseband SIM interface is set to a LOW state.
• Disable the SIM1 interface by asserting B2 = 0 and B3 = 0 in the SIM Interface Control Register.
• Disable the SIM2 interface by asserting B6 = 0 and B7 = 0 in the SIM Interface Control Register.
• VSIM1 voltage regulator should now be activated by asserting B0 = 1 in the SIM Interface Control Register.
• Enable the SIM1 interface by asserting B2 = 1 and B3 = 1 in the SIM Interface Control Register.
• The SIM1 interface (VSIM1, SIM1CLK, SIM1I/O) is now active. The TXS02326A relies on the baseband to
perform the power up sequencing of the SIM card. If there is lack of communication between the baseband
and the SIM card, the SIM1 interface must be powered-down and then powered up again through the
regulator by configuring it to 2.95V by asserting B1 = 1 in the SIM Interface Control Register.
SWITCHING BETWEEN SIM CARDS
The following sequence outlines a rudimentary sequence of switching between the SIM1 card and SIM2 card:
• Put the SIM1 card interface into “clock stop” mode then assert B2 = 1 and B3 = 0 in the SIM Interface Control
Register (08h). This will latch the state of the SIM1 interface (SIM1CLK, SIM1I/O, SIM1RST).
• There can be two scenarios when switching to SIM2 card:
– SIM2 may be in the power off mode, B6 = 0 and B7 = 0 in the Status Register (04h). If SIM2 is in power
off mode, the SIM/UICC interface will need to be set to the power off state. In this case the baseband will
most likely need to go through a power up sequence iteration
– SIM2 may already be in the “clock stop” mode, B6 = 1 and B7 = 0 in the Status Register (04h). If SIM2 is
in “clock stop” mode, the interface between the baseband and the device is set to the clock stop mode
levels that correspond to the SIM2 card interface.
• After determining whether the SIM2 card is either in power off mode or clock stop mode, the SIM2 card
interface is then activated by asserting B6 = 1 and B7 = 1 in the SIM Interface Control Register (08h) and the
negotiation between the baseband and card can continue.
• Switching from SIM2 to SIM1 done in the same manner.
AUTOMATIC SHUTDOWN
Both SIM card interfaces can be configured to automatically shut down upon disconnecting the battery. The
shutdown threshold BSIThreshold is configured in B3 of the Device Control Register (0Eh). Two threshold levels are
available for this configuration. When the BSI input level exceeds the BSIThreshold level that caused this powerdown, both SIM card interfaces will automatically be shut down. If the battery removal interrupt is enabled
through B2 of the Device Control Register, then an interrupt will be issued to the baseband on IRQ. This case
may happen if the user decides to remove the battery.
There are two scenarios for shutting down each SIM: SIMx is “active”, or in “clock stop” mode. In clock stop
mode, when the debounce timer expires, the SIMx signals all go low immediately, then the regulator is disabled
one 32KHz cycle later. If SIMx is active, the signals go low and the regulator is disabled in a particular sequence
to be described in the next section.
The SIM2 interface can also be configured to automatically shut down via the SDN pin.
10
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BSI / SDN DEBOUNCE AND AUTOMATIC SHUTDOWN SEQUENCE TIMING
There are two debounce counters: one each for the BSI and SDN inputs. For each counter, when the device is
reset or the related input is “false”, the counter is loaded with the value in the associated Debounce Counter
register and the debounced signal (i.e. BSI_DEB or SDN_DEB) is subsequently set to a “false” state. When the
related input becomes “true”, the counter begins counting down on subsequent CLK rising-edges. (CLK is either
the internal or external 32 kHz clock as selected by Clock Source Select)
If the input changes state during the count, the counter is again loaded with the register value. The debounce
counter propagates the input signal to the output when the counter expires.
For BSI and BSI_DEB, the “true” state is high. For SDN and SDN_DEB, the “true” state is the state stored in the
SDN Detection Level register. Once either count reaches zero, the debounced signal switches to the “true” state
on the next CLK rising edge. Writing a new value to the SDN detection level register such that SDN is now in the
TRUE state will force the debounce counter to zero, but will not generate an interrupt nor initiate a shutdown
sequence.
If BSI_DEB goes high and Battery Removal Interrupt (bit 2 of the Device Control Register) is 1, an interrupt is
generated and appears on IRQ. Also, if BSI_DEB goes high and BSI Detection Control (bit 4 of the Device
Control Register) is 0, the Automatic Shutdown sequence begins for both SIM’s.
If SDN_DEB goes “true” and SDN Detection Interrupt (bit 5 of the Device Control Register) is 1, an interrupt is
generated and appears on IRQ. Also, if SDN_DEB goes “true” and SDN Detection Control (bit 7 of the Device
Control Register) is 0, the Automatic Shutdown sequence begins for SIM2 only, leaving SIM1 unaffected.
CLK
DEB CNT
1
2
4
3
4
3
5
2
6
7
4
8
3
9
2
10
1
11
12
13
14
0
15
16
17
4
BSI
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
Active Data
SIM1 VCC
SIM2 RST
Latched RST
SIM2 CLK
Latched Clock
SIM2 I/O
Latched Data
SIM2 VCC
Figure 2. BSI Debounce Timing – SIM1 Active and SIM2 Isolated
Notes:
BSI debounce count value set to 4
SIM1 Active, SIM2 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to 1
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Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.
Since SIM1 is active with SIMCLK running, it follows the staged shutdown sequence. Since SIM2 is powered up
but inactive, it follows the instant shutdown sequence.
CLK
DEB CNT
1
2
4
3
4
3
5
2
6
4
7
8
3
9
2
10
1
11
12
13
14
0
15
16
17
4
BSI
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
Clock stopped
Active Data
SIM1 I/O
SIM1 VCC
SIM2 RST
Latched RST
SIM2 CLK
Latched Clock
SIM2 I/O
Latched Data
SIM2 VCC
Figure 3. BSI Debounce Timing – SIM1 Clock Stop and SIM2 Isolated
Notes:
BSI debounce counter set to 4
SIM1 Active in Clock Stop Mode
SIM2 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to 1
Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.
Since SIM1 is active with SIMCLK stopped, it follows the instant shutdown sequence. Since SIM2 is powered up
but inactive, it follows the instant shutdown sequence.
12
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CLK
DEB CNT
SCES830A – MAY 2012 – REVISED AUGUST 2013
1
2
4
3
4
3
5
2
6
4
7
8
3
9
2
10
1
11
12
13
0
14
15
16
17
4
BSI
BSI_DEB
IRQ
SIMCLK
SIM1 RST
Latched RST
SIM1 CLK
Latched Clock
SIM1 I/O
Latched Data
SIM1 VCC
SIM2 RST
SIM2 CLK
Active Data
SIM2 I/O
SIM2 VCC
Figure 4. BSI Debounce Timing – SIM1 Isolated, SIM2 Active
Notes:
BSI debounce counter set to 4
SIM2 Active
SIM1 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to 1
Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.
Since SIM2 is active with SIMCLK running, it follows the staged shutdown sequence. Since SIM1 is powered up
but inactive, it follows the instant shutdown sequence.
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CLK
1
DEB CNT
4
2
3
3
4
2
1 7
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5
6
6
7
5
8
4
9
3 2
10
11
1
12
0
13
14
15
16
17
4
Wt. 0Ah
BSI
BSI_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
Active Data
SIM1 I/O
SIM1 VCC
SIM2 RST
Latched RST
SIM2 CLK
Latched Clock
SIM2 I/O
Latched Data
SIM2 VCC
Figure 5. BSI Debounce Timing – Debounce Count Value Write During Debounce
Notes:
BSI debounce count value set to 4, but written to 7 during debounce
SIM1 Active
SIM2 powered but Isolated
BSI Detection Control set to 0
Battery Removal Interrupt set to
BSI_DEB goes high causing automatic shutdown sequence on both SIM’s. Since SIM1 follows the staged
shutdown sequence. SIM2 follows the instant shutdown sequence. BSI returning low does not interrupt shutdown
sequence.
14
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CLK
DEB CNT
1
2
4
3
4
3
5
2
6
4
7
8
3
9
2
10
1
11
12
13
0
14
15
16
17
4
SDN
SDN_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
Active Data
SIM1 VCC
SIM2 RST
Latched RST
SIM2 CLK
Latched Clock
SIM2 I/O
Latched Data
SIM2 VCC
Figure 6. SDN Debounce Timing – SDN Detection Level High
Notes:
SDN debounce count value set to 4
SIM1 Active
SIM2 powered but Isolated
SDN Detection Control set to 0
SDN Detection level set to 1
SDN Detection Interrupt set to 1
Once SDN is high for four cycles, SDN_DEB goes high causing automatic shutdown sequence on SIM2. SIM1 is
unaffected. Since SIM2 is powered up but inactive, it follows the instant shutdown sequence.
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1
CLK
DEB CNT
2
4
3
4
3
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5
2
6
4
7
8
3
9
2
10
1
11
12
13
0
14
15
16
17
4
SDN
SDN_DEB
IRQ
SIMCLK
SIM1 RST
SIM1 CLK
SIM1 I/O
Active Data
SIM1 VCC
SIM2 RST
Latched RST
SIM2 CLK
Latched Clock
SIM2 I/O
Latched Data
SIM2 VCC
Figure 7. SDN Debounce Timing – SDN Detection Level Low
Notes:
SDN debounce count value set to 4
SIM1 Active
SIM2 powered but Isolated
SDN Detection Control set to 0
SDN Detection level set to 0
SDN Detection Interrupt set to 1
Once SDN is low for four cycles, SDN_DEB goes low causing automatic shutdown sequence on SIM2. SIM1 is
unaffected. Since SIM2 is powered up but inactive, it follows the instant shutdown sequence.
16
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1
CLK
DEB CNT
2
4
3
4
3
5
2
6
4
7
8
3
9
2
10
1
11
12
13
14
0
15
16
17
4
SDN
SDN_DEB
IRQ
SIMCLK
SIM1 RST
Latched RST
SIM1 CLK
Latched Clock
SIM1 I/O
Latched Data
SIM1 VCC
SIM2 RST
SIM2 CLK
Active Data
SIM2 I/O
SIM2 VCC
Figure 8. SDN Debounce Timing – SIM1 Isolated and SIM 2 Active
Notes:
SDN debounce count value set to 4
SIM1 powered but Isolated
SIM2 Active
SDN Detection Control set to 0
SDN Detection level set to 1
SDN Detection Interrupt set to 1
SDN_DEB goes high causing automatic shutdown sequence on SIM2. Since SIM2 is active with SIMCLK
running, it follows the staged shutdown sequence, SIM1 is unaffected.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Level Translator (1)
VDDIO
Supply voltage range
VI
Input voltage range
MIN
MAX
UNIT
–0.3
4.0
V
VDDIO-port
–0.5
4.6
VSIMx-port
–0.5
4.6
Control inputs
–0.5
4.6
VDDIO-port
–0.5
4.6
VSIMx-port
–0.5
4.6
VDDIO-port
–0.5
4.6
VSIMx-port
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off
state
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA or GND
Tstg
Storage temperature range
ESD rating
–65
Human-Body Model (HBM)
All pins
Human-Body Model (HBMHV)
Baseband Side I/O:
SIM1CLK, SIM1I/O,
SIM1RST,
SIM2CLK, SIM2I/O,
SIM2RST
Charge-Device Model (CDM)
(1)
V
V
150
°C
2.5
kV
6
Kv
1000
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
LDO (1)
MIN
MAX
UNIT
VIN
Input voltage range
–0.3
6
V
VOUT
Output voltage range
–0.3
6
V
TJ
Junction temperature range
–55
150
°C
Tstg
Storage temperature range
–55
150
°C
6
kV
1000
V
ESD rating
Human-Body Model (HBM-HV)
Charged-Device Model (CDM)
(1)
18
LDO Output:
VSIM1, VSIM2
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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THERMAL IMPEDANCE RATINGS
UNIT
Package thermal impedance (1)
θJA
(1)
RGE package
45
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
Level Translator
Description
VDDIO
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
Applies to pins: RESET, SDN,
SCL, SDA, IRQ, OE, 32kHz,
SIM_RST, SIM_CLK, SIM_I/O
MIN
MAX
UNIT
1.7
3.3
V
VDDIO × 0.7
1.9
V
0
VDDIO × 0.3
V
5
ns/V
85
°C
–40
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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ELECTRICAL CHARACTERISTICS
Level Translator
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SIM1_RST
SIM1_CLK
SIM1_I/O
SIM2_RST
VOH
SIM2_CLK
SIM2_I/O
SIM_I/O
20
MAX
VSIM1 × 0.8
IOH = –100 µA
Push-Pull
1.7 V
to 3.3
V
1.8 V / 2.95 V
(Supplied by
LDO)
1.8 V / 2.95 V
(Supplied by
LDO)
VSIM2 × 0.8
VSIM2 × 0.8
V
VSIM2 × 0.8
IOH = –100 µA
Push-Pull
IOH = –10 µA
Open-Drain
VDDIO × 0.8
IOH = –100 µA
Push-Pull
IOL = 1 mA
Push-Pull
VSIM1 × 0.2
IOL = 1 mA
Open-Drain
0.3
IOL = 1 mA
Push-Pull
SIM2_RST
IOL = 1 mA
Push-Pull
SIM2_CLK
IOL = 1 mA
Push-Pull
1.7 V
to 3.3
V
1.8 V / 2.95 V
(Supplied by
LDO)
VSIM2 × 0.2
1.8 V / 2.95 V
(Supplied by
LDO)
V
VSIM2 × 0.2
IOL = 1 mA
Open-Drain
0.3
IOL = 1 mA
Push-Pull
IOL = 1 mA
Open-Drain
0.3
IOL = 1 mA
Push-Pull
Control inputs VI = OE
1.7 V
to 3.3
V
1.8 V / 2.95 V
(Supplied by
LDO)
1.8 V / 2.95 V
(Supplied by
LDO)
±1
SIM_I/O port
7
SIMx port
4
Control inputs
Clock input
UNIT
VSIM1 × 0.8
IOH = –10 µA
Open-Drain
IOH = –10 µA
Open-Drain
TYP (1)
VSIM1 × 0.8
IOH = –100 µA
Push-Pull
IOH = –100 µA
Push-Pull
MIN
SIM1_CLK
SIM_I/O
(1)
VSIM2
VSIM1 × 0.2
SIM2_I/O
Ci
VSIM1
IOL = 1 mA
Push-Pull
VOL
Cio
VDDIO
SIM1_RST
SIM1_I/O
II
TEST CONDITIONS
VI = VDDIO or GND
3
µA
pF
pF
All typical values are at TA = 25°C.
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ELECTRICAL CHARACTERISTICS
LDO (Control Input Logic = High)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VBAT
TEST CONDITIONS
Input voltage
VOUT
Output voltage
VDO
Dropout voltage
IGND
Ground-pin current
IOUT(SC)
Short-circuit current
COUT
Output Capacitor
MAX
UNIT
5.5
V
2.3
Class-B Mode
2.85
2.95
3.05
Class-C Mode
1.7
1.8
1.9
IOUT = 50 mA
100
IOUT = 0 mA
35
IOUT = 50 mA
150
RL = 0 Ω
V
mV
µA
400
mA
1
PSRR
Power-supply rejection ratio
VBAT = 3.25 V,
VSIMx = 1.8 V or 3 V,
COUT = 1 µF, IOUT = 50 mA
TSTR
Start-up time
VSIMx = 1.8 V or 3 V, IOUT = 10 mA,
COUT = 1 µF
TJ
Operating junction temperature
(1)
TYP (1)
MIN
f = 1 kHz
50
f = 10 kHz
40
µF
dB
–40
50
µS
85
°C
All typical values are at TA = 25°C.
GENERAL ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
IBAT_ACT
VBAT Current Consumption in Active
Mode
RSTX = High,
VSIMx = 1.8 V or 2.95 V, IOUT = 0 mA
VBAT = 2.3 to 5.5 V
VDDIO = 1.7 to 3.3 V
IBAT_SDN
VBAT Current Consumption in
Shutdown Mode
RSTX = Low,
VSIMx = 0 V (Disabled), IOUT = 0 mA
VBAT = 2.3 to 5.5 V
VDDIO = 1.8 V
IDDIO_ACT
VDDIO Current Consumption in Active
Mode
RSTX = High,
VSIMx = 1.8 V or 2.95 V, IOUT = 0 mA
VBAT = 2.3 to 5.5 V
VDDIO = 1.7 to 3.3 V
5
IDDIO_SDN
VDDIO Current Consumption in
Shutdown Mode
RSTX = Low,
VSIMx = 0 V (Disabled), IOUT = 0 mA
VBAT = 2.3 to 5.5 V
VDDIO = 1.7 to 3.3 V
0.25
BSIThreshold
Comparator Threshold
Hyst
Internal hysteresis of comparator
CLKInt
Internal System Clock
RSIMPU
SIM I/O pull-up
RSIMxPU
SIMx I/O pull-up
RSIMPD
SIMx I/O pull-down
UNIT
250
1
5
µA
BSI detection level “1”
1.6
1.7
BSI detection level “0”
1.1
1.3
±50
–20%
mV
32
+20%
KHz
kΩ
18
20
22.6
Class B
6
7.5
9
Class C
3.8
4.5
5.2
Active pull-downs are connected to the
VSIM1/2 regulator output to the SIM1/2
CLK, SIM1/2 RST, SIM1/2 I/O when
the respective regulator is disabled
2
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kΩ
kΩ
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SWITCHING CHARACTERISTICS
VSIMx = 1.8 V or 2.95 V Supplied by Internal LDO, VBAT = 2.3V to 5.5V
over recommended operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
trA
Baseband side to SIM side
tfA
Baseband side to SIM side
VDDIO = 1.7 V to 3.3 V
MIN
MAX
UNIT
SIMx_I/O
Open Drain
320
ns
SIMx_I/O
Push Pull
8.6
ns
SIMx_RST
Push Pull
4.3
ns
SIMx_CLK
Push Pull
9.3
ns
SIMx_I/O
Open Drain
16
ns
SIMx_I/O
Push Pull
6.5
ns
SIMx_RST
Push Pull
4.5
ns
SIMx_CLK
Push Pull
9.5
ns
trB
SIM side to Baseband side
SIM_I/O
Open Drain
245
ns
SIM_I/O
Push Pull
10
ns
tfB
SIM side to Baseband side
SIM_I/O
Open Drain
18
ns
SIM_I/O
Push Pull
8
ns
fmax
SIMx_CLK
Push Pull
5
MHz
SIM_CLK to SIMx_CLK
Push Pull
8.9
ns
SIM_RST to SIMx_RST
Push Pull
8
ns
SIM_IO to SIMx_IO
Open Drain
18
ns
SIM_IO to SIMx_IO
Push Pull
10
ns
SIMx_IO to SIMIO
Open Drain
10
ns
SIMx_IO to SIMIO
Push Pull
10.5
ns
SIM_CLK to SIMx_CLK
Push Pull
10
ns
SIM_RST to SIMx_RST
tPLH
tPHL
Push Pull
7
ns
SIM_IO to SIMx_IO
Open Drain
23
ns
SIM_IO to SIMx_IO
Push Pull
8
ns
SIMx_IO to SIM_IO
Open Drain
23
ns
SIMx_IO to SIM_IO
Push Pull
10
ns
OPERATING CHARACTERISTICS
TA = 25°C, VSIMx = 1.8 V for Class C, VSIMx = 2.95 V for Class B
PARAMETER
Cpd
(1)
22
(1)
Class B
Class C
TEST
CONDITIONS
CL = 0,
f = 5 MHz,
tr = tf = 1 ns
TYP
UNIT
11
9.5
pF
Power dissipation capacitance per transceiver
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APPLICATION INFORMATION
The LDO’s included on the TXS02326A achieve ultra-wide bandwidth and high loop gain, resulting in extremely
high PSRR at very low headroom (VBAT – VSIM1/2). The TXS02326A provides fixed regulation at 1.8V or 2.95V.
Low noise, enable through I2C control, and low ground pin current make it ideal for portable applications. The
device offers sub-bandgap output voltages, current limit, thermal protection, and is fully specified from –40°C to
+85°C.
VSIM1
VDDIO
VBAT
TXS02326A
GND
1 μF
VSIM2
1μF
0.1μF
1 μF
Figure 9. Typical Application circuit for TXS02326A
Input and Output Capacitor Requirements
It is good analog design practice to connect a 1.0 μF low equivalent series resistance (ESR) capacitor across the
input supply (VBAT) near the regulator. Also, a 0.1uF is required for the logic core supply (VDDIO).
This capacitor will counteract reactive input sources and improve transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if
the device is located several inches from the power source. The LDO’s are designed to be stable with standard
ceramic capacitors of values 1.0 μF or larger. X5R- and X7R-type capacitors are best because they have
minimal variation in value and ESR over temperature. Maximum ESR should be < 1.0 Ω.
Output Noise
In most LDO’s, the bandgap is the dominant noise source. To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN
and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground
connection for the bypass capacitor should connect directly to the GND pin of the device.
Internal Current Limit
The TXS02326A internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the
device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TXS02326A has a built-in body diode that conducts current when the voltage at
VSIM1/2 exceeds the voltage at VBAT. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
Dropout Voltage
The TXS02326A uses a PMOS pass transistor to achieve low dropout. When (VBAT – VSIM1/2) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO will approximately scale with output current because
the PMOS device behaves like a resistor in dropout.
Startup
The TXS02326A uses a quick-start circuit which allows the combination of very low output noise and fast start-up
times. Note that for fastest startup, VBATT should be applied first, and then enabled by asserting the I2C register.
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Transient Response
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but
increases duration of the transient response.
Minimum Load
The TXS02326A is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from
lower loop gain at very light output loads. The TXS02326A employs an innovative low-current mode circuit to
increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation
performance down to zero output current.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage
because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature should be limited to +85°C maximum. To estimate the
margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of +85°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TXS02326A has been designed to protect against overload conditions. It
was not intended to replace proper heat sinking. Continuously running the TXS02326A into thermal shutdown will
degrade device reliability.
TYPICAL CHARACTERISTICS
110
-80
90
-70
-60
-50
2.95 V Vsim
-40
-30
-20
80
85°C Vsim
70
60
50
40
-40°C Vsim
30
20
-10
0
100
24
100
1.8 V Vsim
VDO - Dropout Voltage - mV
PSRR - Power Supply Rejection Ratio - dB
-90
25°C Vsim
10
1000
10000
100000
f - Frequency - Hz
Figure 10. PSRR
1000000
0
0
5
15 20 25 30 35 40 45 50
IOUT - Output Current - mA
Figure 11. Dropout Voltage vs Output Current
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TXS02326A
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SCES830A – MAY 2012 – REVISED AUGUST 2013
0
-100 mA, Vsim
-50 mA, Vsim
-0.4
-40°C Vsim
85°C Vsim
-0.8
-1
-1.2
-1.4
25°C Vsim
-1.8
0
-2
0
10 20 30 40 50 60 70 80
5
10
15 20 25 30 35 40
IOUT - Output Current - mA
45
50
Figure 13. Load Regulation, Iout = 50 mA, Class-C
0.2
0
0
-0.2
-40°C Vsim
IO = 50 mA
-0.4
-0.2
-0.4
-0.6
25°C Vsim
-0.8
85°C Vsim
-1
-1.2
-1.4
-1.6
DVOUT - Output Voltage - %
DVOUT - Output Voltage - %
-0.6
-1.6
TA - Temperature - °C
Figure 12. Output Voltage vs Temperature, Class-B/C
-0.6
-0.8
-40°C Vsim
-1
-1.2
25°C Vsim
-1.4
-1.6
85°C Vsim
-1.8
-2
IO = 50 mA
-1.8
-2
0
IO = 50 mA
-0.2
DVOUT - Output Voltage - %
DVOUT - Output Voltage - %
TYPICAL CHARACTERISTICS (continued)
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-40 -30 -20 -10
5
10
15
20 25 30 35 40 45 50
IOUT - Output Current - mA
Figure 14. Load Regulation, Iout = 50 mA, Class-B
-2.2
-2.4
2.7
3.1
3.5
3.9
4.3
VBAT - V
4.7
5.1
5.5
Figure 15. Line Regulation, Iout = 50 mA, Class-C
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25
TXS02326A
SCES830A – MAY 2012 – REVISED AUGUST 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
330
0
300
DVOUT - Output Voltage - %
-0.4
-40°C Vsim
270
IOUT(SC) - Output Current - mA
-0.2
IO = 50 mA
-0.6
-0.8
25°C Vsim
-1
85°C Vsim
-1.2
-1.4
-1.6
-1.8
240
85°C Vsim
180
25°C Vsim
150
120
90
-2
60
-2.2
30
-2.4
3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VBAT - V
Figure 16. Line Regulation, Iout = 50 mA, Class-B
-40°C Vsim
210
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VBAT - V
Figure 17. Current Limit vs Input Voltage, Class-B/C
150
-50 mA, Vsim
IGND - Ground Current - mA
120
90
60
30
-100 mA, Vsim
0
-40 -30 -20 -10
20 30 40 50 60 70 80
TA - ºC
Figure 18. Ground Current vs Temperature, Class-C
26
0 10
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Product Folder Links: TXS02326A
TXS02326A
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SCES830A – MAY 2012 – REVISED AUGUST 2013
REVISION HISTORY
Changes from Original (May 2012) to Revision A
Page
•
Deleted ISHDN from LDO characteristics as ISHUTDOWN applies to total device while in the reset mode outlined in the
General Characteristics ...................................................................................................................................................... 21
•
Added IBAT_ACT, IBAT_SDN, IDDIO_ACT, and IDDIO_SDN to the General Electrical Characteristics table ....................................... 21
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Product Folder Links: TXS02326A
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TXS02326AMRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YJ326A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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