UC2526AQG3

UC1526A UC2526A UC3526A Regulating Pulse Width Modulator FEATURES DESCRIPTION • Reduced Supply Current • Oscillator Frequency to 600kHz • Precision Band-Gap Reference • 7 to 35V Operation • Dual 200mA Source/Sink Outputs • Minimum Output Cross-Conduction • Double-Pulse Suppression Logic The UC1526A Series are improved-performance pulse-width modulator circuits intended for direct replacement of equivalent non- “A” versions in all applications. Higher frequency operation has been enhanced by several significant improvements including: a more accurate oscillator with less minimum dead time, reduced circuit delays (particularly in current limiting), and an improved output stage with negligible cross-conduction current. Additional improvements include the incorporation of a precision, band-gap reference generator, reduced overall supply current, and the addition of thermal shutdown protection. • Under-Voltage Lockout • Programmable Soft-Start • Thermal Shutdown • TTL/CMOS Compatible Logic Ports • 5 Volt Operation (VIN = VC = VREF = 5.0V) BLOCK DIAGRAM 6/93 Along with these improvements, the UC1526A Series retains the protective features of under-voltage lockout, soft-start, digital current limiting, double pulse suppression logic, and adjustable deadtime. For ease of interfacing, all digital control ports are TTL compatible with active low logic. Five volt (5V) operation is possible for “logic level” applications by connecting VIN, VC and VREF to a precision 5V input supply. Consult factory for additional information. UC1526A UC2526A UC3526A ABSOLUTE MAXIMUM RATINGS (Note 1, 2) RECOMMENDED OPERATING CONDITIONS Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (+VC) . . . . . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Source/Sink Load Current (each output) . . . . . . . . . . . . 200mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . 1000mW Power Dissipation at TC = +25°C (Note 2) . . . . . . . . . . 3000mW Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (soldering, 10 seconds) . . . . . . . . . . +300°C (Note 3) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +35V Collector Supply Voltage . . . . . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (each output) . . . . . . . . 0 to 100mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 600kHz Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ Oscillator Timing Capacitor. . . . . . . . . . . . . . . . . 400pF to 20µF Available Deadtime Range at 40kHz . . . . . . . . . . . . 1% to 50% Operating Ambient Temperature Range UC1526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C UC2526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C UC3526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Note 3: Range over which the device is functional and parameter limits are guaranteed. Note 1: Values beyond which damage may occur. Note 2: Consult packaging Section of Databook for thermal limitations and considerations of package. CONNECTION DIAGRAMS DIL-18, SOIC-18 (TOP VIEW) J or N Package, DW Package PLCC-20, LCC-20 (TOP VIEW) Q and L Packages 2 PACKAGE PIN FUNCTION FUNCTION PIN N/C +ERROR -ERROR COMP. CSS RESET - CURRENT SENSE + CURRENT SENSE SHUTDOWN RTIMING CT RD SYNC OUTPUT A VC N/C GROUND OUTPUT B +VIN VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 UC1526A UC2526A UC3526A ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise specified TA = TJ. UC1526A / UC2526A PARAMETER TEST CONDITIONS UC3526A UNITS MIN TYP MAX MIN TYP MAX 4.95 5.00 5.05 4.90 5.00 5.10 V Reference Section (Note 4) Output Voltage TJ = +25°C Line Regulation +VIN = 7 to 35V 2 10 2 15 mV Load Regulation IL = 0 to 20mA 5 20 5 20 mV Temperature Stability Over Operating TJ (Note 5) Total Output Voltage Range Over Recommended Operating Conditions Short Circuit Current VREF = 0V 15 50 15 50 mV 4.90 5.00 5.10 4.85 5.00 5.15 V 25 50 100 25 50 100 mA 0.2 0.4 0.2 0.4 V Under-Voltage Lockout RESET Output Voltage VREF = 3.8V VREF = 4.7V 2.4 4.7 2.4 4.8 V Oscillator Section (Note 6) Initial Accuracy TJ = +25°C ±3 Voltage Stability +VIN = 7 to 35V Temperature Stability Over Operating TJ (Note 5) Minimum Frequency RT = 150kΩ, CT = 20µF (Note 5) Maximum Frequency RT = 2kΩ, CT = 470pF Sawtooth Peak Voltage +VIN = 35V Sawtooth Valley Voltage +VIN =7V SYNC Pulse Width TJ = 25°C, RL = 2.7kΩ to VREF ±8 ±3 0.5 1 0.5 1 % 2 6 1 3 % 1 550 1 650 3.0 0.5 ±8 3.5 1.0 1.1 Hz kHz 3.0 0.5 % 3.5 V 1.0 V 1.1 µs Error Amplifier Section (Note 7) Input Offset Voltage RS ≤ 2kΩ Input Bias Current Input Offset Current 2 5 2 10 mV -350 -1000 -350 -2000 nA 35 100 35 200 nA DC Open Loop Gain RL ≥ 10MΩ 64 72 60 72 dB HIGH Output Voltage VPIN 1 - VPIN 2 ≥ 150mV, ISOURCE = 100µA 3.6 4.2 3.6 4.2 V LOW Output Voltage VPIN 2 - VPIN 1 ≥ 150mV, ISINK = 100µA Common Mode Rejection RS ≤ 2kΩ 70 94 70 94 dB Supply Voltage Rejection +VIN = 12 to 18V 66 80 66 80 dB 45 49 45 49 % 2.4 4.0 2.4 4.0 V 0.2 0.4 0.2 0.4 V PWM Comparator (Note 6) Minimum Duty Cycle VCOMPENSATION = +0.4V Maximum Duty Cycle VCOMPENSATION = +3.6V 0 0 % Digital Ports (SYNC, SHUTDOWN, and RESET) HIGH Output Voltage ISOURCE = 40µA LOW Output Voltage ISINK = 3.6mA 0.2 0.4 0.2 0.4 V HIGH Input Current VIH = +2.4V -125 -200 -125 -200 µA LOW Input Current VIL = +0.4V -225 -360 -225 -360 µA Shutdown Delay From Pin 8, TJ = 25°C 160 160 ns Current Limit Comparator (Note 8) Sense Voltage RS ≤ 50Ω 90 Input Bias Current Shutdown Delay From pin 7, 100mV Overdrive, TJ = 25°C Note 4: IL = 0mA. Note 5: Guaranteed by design, not 100% tested in production. Note 6: FOSC = 40kHz, (RT = 4.12kΩ ± 1%, CT = 0.01µF± 1%, RD = 0 Ω). 100 110 -3 -10 260 Note 7: VCM = 0 to +5.2V Note 8: VCM = 0 to +12V. Note 9: VC = +15V. Note 10:VIN = +35V, RT = 4.12kΩ. 3 80 100 120 mV -3 -10 µA 260 ns UC1526A UC2526A UC3526A ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise specified TA = TJ. PARAMETER UC1526A UC2526A TEST CONDITIONS MIN UC3526A UNITS TYP MAX 0.1 0.4 50 100 150 ISOURCE = 20mA 12.5 ISOURCE = 100mA 12 MIN TYP MAX 0.1 0.4 V 50 100 150 µA 13.5 12.5 13.5 V 13 12 13 V Soft-Start Section Error Clamp Voltage RESET = +0.4V CS Charging Current RESET = +2.4V Output Drivers (Each Output) (Note 9) HIGH Output Voltage LOW Output Voltage ISINK = 20mA 0.2 0.3 0.2 0.3 V ISINK = 100mA 1.2 2.0 1.2 2.0 V Collector Leakage VC = 40V 50 150 50 150 µA Rise Time CL = 1000pF (Note 5) 0.3 0.6 0.3 0.6 µs Fall Time CL = 1000pF (Note 5) 0.1 0.2 0.1 0.2 Cross-Conduction Charge Per cycle, TJ = 25°C 8 8 µs nC Power Consumption (Note 10) Standby Current SHUTDOWN = +0.4V 14 Note 4: IL = 0mA. Note 5: Guaranteed by design, not 100% tested in production. Note 6: FOSC = 40kHz, (RT = 4.12kΩ ± 1%, CT = 0.01µF± 1%, RD = 0 Ω). Note 7: VCM = 0 to +5.2V Note 8: VCM = 0 to +12V. Note 9: VC = +15V. Note 10:VIN = +35V, RT = 4.12kΩ. Open Loop Test Circuit UC1526A 4 20 14 20 mA UC1526A UC2526A UC3526A APPLICATIONS INFORMATION Voltage Reference The reference regulator of the UC1526A is based on a precision band-gap reference, internally trimmed to ±1% accuracy. The circuitry is fully active at supply voltages above +7V, and provides up to 20mA of load current to external circuitry at +5.0V. In systems where additional current is required, an external PNP transistor can be used to boost the available current. A rugged low frequency audio-type transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillations. Even so, some types of transistors may require collector-base capacitance for stability. Up to 1 amp of load current can be obtained with excellent regulation if the device selected maintains high current gain. Figure 2. Under-Voltage Lockout Schematic Soft-Start Circuit The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the UC1526A, the under-voltage lockout circuit holds RESET LOW with Q3. Q1 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of Q1 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the supply voltage reaches normal operating range, RESET will go HIGH. Q1 turns off, allowing the internal 100µA current source to charge CS. Q2 clamps the error amplifier output to 1VBE above the voltage on CS. As the soft-start voltage ramps up to +5V, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null. Figure 1. Extending Reference Output Current Under-Voltage Lockout The under-voltage lockout circuit protects the UC1526A and the power devices it controls from inadequate supply voltage, If +VIN is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state. The circuit consists of a +1.2V bandgap reference and comparator circuit which is active when the reference voltage has risen to 3VBE or +1.8V at 25°C. When the reference voltage rises to approximately +4.4V, the circuit enables the output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 350mV of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed and the reference drops to +4.2V, the under-voltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle. Figure 3. Soft-Start Circuit Schematic Digital Control Ports The three digital control ports of the UC1526A are bi-directional. Each pin can drive TTL and 5V CMOS logic directly, up to a fan-out of 10 low-power Schottky gates. Each pin can also be directly driven by open-collector TTL, open-drain CMOS, and open-collector voltage comparators; fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start The UC1526A can operate from a +5V supply by connecting the VREF pin to the +VIN pin and maintaining the supply between +4.8 and +5.2V. 5 UC1526A UC2526A UC3526A APPLICATIONS INFORMATION (cont.) the SYNC pin will then lock the oscillator to the external frequency. capacitor. The logic threshold is +1.1V at +25°C. Noise immunity can be gained at the expense of fan-out with an external 2k pull-up resistor to +5V. Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master and all SYNC terminals are likewise connected to the SYNC pin of the master. Slave RT terminals are left open or connected to VREF. Slave RD terminal may be either left open or grounded. Figure 4. Digital Control Port Schematic Oscillators The oscillator is programmed for frequency and dead time with three components: RT, CT and RD. Two waveforms are generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The following procedure is recommended for choosing timing values: Figure 6. Error Amplifier Connections Error Amplifier 1. With RD= 0Ω (pin 11 shorted to ground) select values for RT and CT from the graph on page 4 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +VC terminal is the same as the oscillator frequency. The error amplifier is a transconductance design, with an output impedance of 2MΩ. Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 100pF, the amplifier has an open-loop pole at 800Hz. 2. If more dead time is required, select a larger value of RD. At 40kHz dead time increases by 400ns/Ω. The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 6B. 3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value. The UC1526A can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower than the SYNC frequency. A periodic LOW logic pulse approximately 0.5µs wide at Figure 5. Oscillator Connections and Waveforms Figure 7. Push-Pull Configuration 6 UC1526A UC2526A UC3526A APPLICATIONS INFORMATION (cont.) +VC terminal to ground during switching; however, improved design has limited this cross-conduction period to less than 50ns. Capacitor decoupling at VC is recommended and careful grounding of Pin 15 is needed to insure that high peak sink currents from a capacitive load do not cause ground transients. Output Drivers The totem pole output drivers of the UC1526A are designed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +VC, as required. Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the Figure 8. Single-Ended Configuration Figure 9. Driving N-Channel Power MOSFETs TYPICAL CHARACTERISTICS OSCILLATOR PERIOD vs RT and CT OUTPUT BLANKING 7 UC1526A UC2526A UC3526A TYPICAL CHARACTERISTICS (Cont.) Output Driver Deadtime vs. RD Value Under Voltage Lockout Characteristic Error Amplifier Open Loop Gain vs. Frequency Current Limit Transfer Function Shutdown Delay Output Driver Saturation Voltage UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 8 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 85515022A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 85515022A UC1526AL/ 883B 8551502VA ACTIVE CDIP J 18 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8551502VA UC1526AJ/883B Samples UC1526AJ ACTIVE CDIP J 18 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 UC1526AJ Samples UC1526AJ883B ACTIVE CDIP J 18 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8551502VA UC1526AJ/883B Samples UC1526AL ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 UC1526AL Samples UC1526AL883B ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 85515022A UC1526AL/ 883B UC2526ADW ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2526ADW Samples UC2526ADWG4 ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2526ADW Samples UC2526ADWTR ACTIVE SOIC DW 18 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2526ADW Samples UC2526AN ACTIVE PDIP N 18 20 RoHS & Green NIPDAU N / A for Pkg Type -25 to 85 UC2526AN Samples UC2526ANG4 ACTIVE PDIP N 18 20 RoHS & Green NIPDAU N / A for Pkg Type -25 to 85 UC2526AN Samples UC3526ADW ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3526ADW Samples UC3526ADWG4 ACTIVE SOIC DW 18 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3526ADW Samples UC3526ADWTR ACTIVE SOIC DW 18 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3526ADW Samples UC3526AN ACTIVE PDIP N 18 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UC3526AN Samples UC3526J ACTIVE CDIP J 18 1 Non-RoHS & Green SNPB N / A for Pkg Type 0 to 70 UC3526J Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of