UC2824DWG4

UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 HIGH SPEED PWM CONTROLLER FEATURES • • • • • • • • • • • DESCRIPTION Complementary Outputs Practical Operation Switching Frequencies to 1 MHz 50-ns Propagation Delay to Output High Current Dual Totem Pole Outputs (1.5 A Peak) Wide Bandwidth Error Amplifier Fully Latched Logic With Double Pulse Suppression Pulse-by-Pulse Current Limiting Soft Start/Maximum Duty Cycle Control Under-Voltage Lockout with Hysteresis Low Start Up Current (1.1 mA) Trimmed Bandgap Reference (5.1 V ± 1%) The UC1824 family of PWM control devices is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current mode or voltage mode systems with the capability for input voltage feed-forward. Protection circuitry includes a current limit comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft-start pin which doubles as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An under-voltage lockout section with 800 mV of hysteresis assures low start up current. During under-voltage lockout, the outputs are high impedance. BLOCK DIAGRAM Clock 4 RT 5 CT 6 Ramp 7 E/A Out 3 OSC PWM Latch (Set Dom.) R 1.25V + S Wide Bandwidth (Set Dom.) NI 2 INV 1 + Error Amp VIN Inhibit Soft Start 9mA VC 11 Out 14 INVOUT 12 Pwr Gnd 10 VREF 5.1V 8 ILIM CPRTR 1V ILIM/SD 13 Shutdown CPRTR 9 1.4V Output Inhibit VCC 15 Gnd 10 Internal Bias 9V 4V UVLO GATE VCC Good REF GEN VREF Good Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2007, Texas Instruments Incorporated UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 DESCRIPTION (CONTINUED) These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply voltage (pins 13, 15) VALUE UNIT 30 V Output current, source or sink (pins 11, 14) DC 0.5 Pulse (0.5 ms) 2 A Analog inputs (Pins 1, 2, 7) –0.3 TO 7 (Pin 8, 9) –0.3 TO 6 Clock output current (pin 4) –5 Error amplifier output current (pin 3) 5 Soft start sink current (pin 8) 20 Oscillator charging current (pin 5) –5 Power dissipation 1 Storage temperature range –65 to 150 Lead temperature (soldering, 10 seconds) (1) (2) 300 mA W °C All voltages are with respect to GND (Pin 10); all currents are positive into, negative out of part; pin numbers refer to DIL-16 package. Consult Unitrode Integrated Circuit Databook for thermal limitations and considerations of package. SOIC-16 DW PACKAGE (TOP VIEW) DIL-16 J OR N PACKAGE (TOP VIEW) 2 V Submit Documentation Feedback UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 PLCC-20 AND LCC-20 Q AND L PACKAGES (TOP VIEW) PACKAGE PIN FUNCTION FUNCTION N/C INV NI E/A Out Clock N/C RT CT Ramp Soft Start N/C ILIM/SD Gnd Out Pwr Gnd N/C VC INVOUT VCC VREF 5.1V Submit Documentation Feedback PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for, RT = 3.65k, CT = 1 nF, VCC = 15 V, –55°C < TA < 125°C for the UC1824, –40°C < TA < 85°C for the UC2824, and 0°C < TA < 70°C for the UC3824, TA = TJ. PARAMETER UC1824 UC2824 TEST CONDITIONS UC3824 UNIT MIN TYP MAX MIN TYP MAX 5.05 5 Reference Section Output voltage TJ = 25°C, IO = 1 mA 5.10 5.15 5.10 5.20 Line regulation 10 V < VCC < 30 V 2 20 2 20 Load regulation 1 mA < IO < 10 mA 5 20 5 20 Temperature stability (1) TMIN < TA < TMAX Total output variation (1) Line, Load, Temperature Output noise voltage (1) 10 Hz < f < 10 kHz long term stability (1) TJ = 125°C, 1000 hrs. 5 25 5 25 mV Short circuit current VREF = 0 V –15 –50 –100 –15 –50 –100 mA TJ = 25°C 360 400 440 360 400 440 kHz 0.2% 2% 0.2% 2% 0.2 5 0.4 5.20 0.2 4.95 50 0.4 5.25 V mV mV mV/°C V μV 50 Oscillator Section Initial accuracy (1) Voltage stability (1) 10 V < VCC < 30 V Temperature stability (1) TMIN < TA < TMAX Total variation (1) Line, Temperature 5% 340 Clock out high 460 3.9 4.5 Clock out low Ramp peak (1) Ramp valley Ramp valley to peak (1) 340 3.9 2.3 2.9 2.8 3 2.6 0.7 1 1.25 1.6 1.8 2 2.6 (1) 5% 460 kHz 4.5 2.3 2.9 2.8 3 0.7 1 1.25 1.6 1.8 2 V Error Amplifier Section Input offset voltage 10 15 mV Input bias current 0.6 3 0.6 3 μA Input offset current 0.1 1 0.1 1 μA Open loop gain 1 V < VO < 4 V 60 95 60 CMRR 1.5 V < VCM < 5.5 V PSRR 10 V < VCC < 30 V Output sink current VPIN 3 Output source current VPIN 3 Output high voltage IPIN 3 Output low voltage IPIN 75 95 75 95 85 110 85 110 =1V 1 2.5 1 2.5 =4V –0.5 –1.3 –0.5 –1.3 3 = 1 mA 4 4.7 5 4 4.7 5 0 0.5 1 0 0.5 1 3 5.5 3 5.5 MHz 6 12 6 12 V/μs = –0.5 mA Unity gain bandwidth (1) Slew rate (1) 95 dB mA V PWM Comparator Section Pin 7 bias current VPIN 7 =0V VPIN 7 =0V –1 Duty cycle range Pin 3 zero dc threshold 0 1.1 –5 80 1.25 Delay to output (1) 80 9 20 μA 85 % 50 80 ns 9 20 0 1.1 50 –5 –1 1.25 V Soft-Start Section Charge current VPIN 8 Discharge current VPIN = 0.5 V 8= 1V 3 1 3 1 μA mA Current Limit/Shutdown Section Pin 9 bias current (1) 4 0 < VPIN 9 < 4 V 15 This parameter not 100% tested in production but guaranteed by design. Submit Documentation Feedback 10 μA UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for, RT = 3.65k, CT = 1 nF, VCC = 15 V, –55°C < TA < 125°C for the UC1824, –40°C < TA < 85°C for the UC2824, and 0°C < TA < 70°C for the UC3824, TA = TJ. PARAMETER UC1824 UC2824 TEST CONDITIONS MIN Current limit threshold TYP UC3824 MAX MIN TYP UNIT MAX 0.9 1 1.1 0.9 1 1.1 1.25 1.40 1.55 1.25 1.40 1.55 50 80 50 80 IOUT = 20 mA 0.25 0.40 0.25 0.40 IOUT = 200 mA 1.2 2.2 1.2 2.2 Shutdown threshold Delay to output V ns Output Section Output low level Output high level Collector leakage Rise/fall time (2) IOUT = –20 mA 13 IOUT = –200 mA 12 13.5 13 13 13.5 12 13 V VC = 30 V 100 500 10 500 μA CL = 1 nF 30 60 30 60 ns Under-Voltage Lockout Section Start threshold 8.8 9.2 9.6 8.8 9.2 9.6 UVLO hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V Supply Current Section (2) Start up current VCC = 8 V 1.1 2.5 1.1 2.5 ICC VPIN 1, VPIN 7, VPIN 9 = 0 V; VPIN 2 = 1 V 22 33 22 33 mA This parameter not 100% tested in production but guaranteed by design. UC1824 Printed Circuit Board Layout Considerations High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1824 follow these rules: 1. Use a ground plane. 2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this purpose. 3. Bypass VCC, VC, and VREF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4. Treat the timing capacitor, CT, like a bypass capacitor. Submit Documentation Feedback 5 UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 Error Amplifier Circuit Simplified Schematic Open Loop Frequency Response Unity Gain Slew Rate Synchronized Operation Two Units in Close Proximity 6 Generalized Synchronization Submit Documentation Feedback UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 Oscillator Circuit m Primary Output Deadtime vs CT (3k £ RT £ 100k) Primary Output Deadtime vs Frequency Timing Resistance vs Frequency 160 1.0 nF TD (ns) 140 120 100 470 pF 80 10k 100k 1M FREQ (Hz) Typical Non-Overlap Time (T NO) Over Temperature 80 70 60 50 40 TNO (ns) 30 20 10 0 -75 -50 -25 0 25 50 75 100 125 T (°C) Non-Overlap Time (TNO) Submit Documentation Feedback 7 UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 Forward Technique for Off-Line Voltage Mode Application Constant Volt-Second Clamp Circuit The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. Output Section Simplified Schematic Rise/Fall Time (CL=10 nF) 8 Rise/Fall Time (C L=1 nF) Saturation Curves Submit Documentation Feedback UC1824 UC2824 UC3824 www.ti.com SLUS326A – MARCH 1997 – REVISED JULY 2007 Open-Loop Laboratory Test Fixture UDG-92036-2 This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and byUC1824’s functions and measuring their specifications. pass procedures should be followed. The use of a ground plane is highly recommended. Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UC2824DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2824DW UC2824N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 UC2824N UC3824DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3824DW UC3824DWTR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3824DW UC3824N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UC3824N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of