UC2825A-EP
www.ti.com
SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
HIGH-SPEED PWM CONTROLLER
Check for Samples: UC2825A-EP
FEATURES
1
•
•
•
•
•
•
•
•
•
Improved Version of the UC2825 PWM
Compatible With Voltage-Mode or
Current-Mode Control Methods
Practical Operation at Switching Frequencies
to 1 MHz
50-ns Propagation Delay to Output
High-Current Dual Totem-Pole Outputs
(2-A Peak)
Trimmed Oscillator Discharge Current
Low 100-mA Startup Current
Pulse-by-Pulse Current-Limiting Comparator
Latched Overcurrent Comparator With Full
Cycle Restart
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Additional temperature ranges are available - contact factory
DESCRIPTION/ORDERING INFORMATION
The UC2825A-EP pulse width modulation (PWM) controller is an improved version of the standard UC2825.
Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth
product is 12 MHz, while input offset voltage is 2 mV. Current-limit threshold is specified to a tolerance of 5%.
Oscillator discharge current is specified at 10 mA for accurate dead-time control. Frequency accuracy is
improved to 6%. Startup supply current, typically 100 mA, is ideal for off-line applications. The output drivers are
redesigned to actively sink current during undervoltage lockout (UVLO) at no expense to the startup current
specification. In addition, each output is capable of 2-A peak currents during transitions.
Functional improvements also have been implemented in this family. The UC2825A-EP shutdown comparator is
now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that
ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs
are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to
ensure that the fault frequency does not exceed the designed soft-start period. The UC2825 CLOCK pin is
CLK/LEB in the UC2825A-EP. This pin combines the functions of clock output and leading-edge blanking
adjustment and has been buffered for easier interfacing.
The UC2825A-EP has dual alternating outputs and the same pin configuration as UC2825. UVLO thresholds are
identical to the original UC2825.
Consult the application report, The UC3823A,B and UC2825A,B Enhanced Generation of PWM Controllers,
literature number SLUA125, for detailed technical and applications information.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2010, Texas Instruments Incorporated
UC2825A-EP
SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PACKAGE (1)
TA
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 125°C
SOIC – DW
UC2825AQDWREP
UC2825AQEP
–55°C to 125°C
SOIC – DW
UC2825AMDWREP
UC2825AMEP
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
BLOCK DIAGRAM
CLK/LEB 4
13 VC
(60%)
RT 5
11 OUTA
OSC
CT 6
R
RAMP 7
EAOUT 3
NI
T
SD
PWM
LATCH
1.25 V
PWM COMPARATOR
14 OUTB
12 PGND
2
E/A
9 A
INV 1
SOFT-ST ART COMPLETE
SS 8
CURRENT
LIMIT
1.0 V
OVER CURRENT
ILIM 9
1.2 V
0.2 V
VCC 15
9.2V/8.4V
GND 10
RESTART
DELAY
LATCH
5V
RESTART
DELAY
SD
S
R
R
250 A
FAULT LATCH
UVLO
VREF
5.1 V
ON/OFF
4V
INTERNAL
BIAS
VREF GOOD
16 5.1 VREF
UDG-02091
2
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
PIN ASSIGNMENTS
DW PACKAGE
(TOP VIEW)
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CLK/LEB
4
O
Clock/leading-edge blanking. Output of the internal oscillator.
CT
6
I
Capacitor timing. Timing capacitor connection for oscillator frequency programming. The timing capacitor
should be connected to the device ground using minimal trace length.
EAOUT
3
O
Output of the error amplifier for compensation
GND
10
ILIM
9
I
Input to the current-limit comparator
INV
1
I
Inverting input to the error amplifier
Analog ground return
NI
2
I
Noninverting input to the error amplifier
OUTA
11
O
High-current totem-pole output A of the on-chip drive stage
OUTB
14
O
High-current totem-pole output B of the on-chip drive stage
PGND
12
RAMP
7
I
Noninverting input to the PWM comparator, with 1.25-V internal input offset. In voltage-mode operation, this
serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation,
this serves as the slope compensation input.
RT
5
I
Resistor timing. Timing resistor connection for oscillator frequency programming.
SS
8
I
Soft-start. SS also doubles as the maximum duty cycle clamp.
VC
13
VCC
15
VREF
16
Ground return for the output driver stage
Power-supply for the output stage. This pin should be bypassed with a 0.1-mF monolithic ceramic low-ESL
capacitor with minimal trace lengths.
O
Power supply for the device. This pin should be bypassed with a 0.1-mF monolithic ceramic low-ESL
capacitor with minimal trace lengths.
5.1-V reference. For stability, the reference should be bypassed with a 0.1-mF monolithic ceramic low-ESL
capacitor and minimal trace length to the ground plane.
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
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Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VIN
Supply voltage
VC, VCC
22 V
IO
Source or sink current, DC
OUTA, OUTB
0.5 A
IO
Source or sink current, pulse (0.5 ms)
OUTA, OUTB
2.2 A
INV, NI, RAMP
–0.3 V to 7 V
ILIM, SS
–0.3 V to 6 V
Analog inputs
Power ground
PGND
Outputs
OUTA, OUTB limits
ICLK
Clock output current
CLK/LEB
IO(EA)
Error amplifier output current
EAOUT
5 mA
ISS
Soft-start sink current
SS
20 mA
IOSC
Oscillator charging current
RT
–5 mA
TJ
Operating virtual junction temperature range
–55°C to 150°C
Tstg
Storage temperature (2)
–65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s
–55°C to 150°C
Storage temperature (2)
–65°C to 150°C
tstg
±0.2 V
PGND –0.3 V to VC +0.3 V
–5 mA
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1)
(2)
300°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Table 1. DISSIPATION RATING TABLE – FREE-AIR TEMPERATURE
4
PACKAGE
AIR FLOW
(CFM)
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
DW
0
1.105 W
9.62 mW/°C
673 mW
528 mW
144 mW
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
Electrical Characteristics
TA = –40°C to 125°C for Q temperature and TA = –55°C to 125°C for M temperature, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.05
5.1
5.15
2
15
mV
20
mV
Reference, VREF
VO
Output voltage range
TJ = 25°C, IO = 1 mA
Line regulation
12 V ≤ VCC ≤ 20 V
Load regulation
1 mA ≤ IO ≤ 10 mA
Total output variation
Line, load, temperature
5
5.03
V
5.17
V
0.4
mV/°C
(1)
T(min) < TA < T(max)
0.2
Output noise voltage (1)
10 Hz < f < 10 kHz
50
Long-term stability (1)
TJ = 125°C, 1000 h
5
25
mV
Short-circuit current
VREF = 0 V
30
60
90
mA
TJ = 25°C
375
400
425
kHz
RT = 6.6 kΩ, CT = 220 pF, TA = 25°C
0.9
1
1.1
MHz
Line, temperature
350
450
kHz
RT = 6.6 kΩ, CT = 220 pF
0.85
1.15
MHz
Temperature stability
mVRMS
Oscillator
fOSC
Initial accuracy (1)
Total variation (1)
12 V ≤ VCC ≤ 20 V
Voltage stability
Temperature stability
(1)
1%
T(min) < TA < T(max)
High-level output voltage, clock
5%
3.7
Low-level output voltage, clock
IOSC
4
0
V
0.2
V
Ramp peak
2.6
2.8
3
V
Ramp valley
0.7
1
1.25
V
Ramp valley to peak
1.6
1.8
2
V
9
10
11
mA
Oscillator discharge current
RT = OPEN, VCT = 2 V
Error Amplifier
Input offset voltage
Input bias current
Input offset current
2
10
mV
0.6
3
mA
0.1
1
mA
Open-loop gain
1 V < VO < 4 V
60
95
dB
CMRR
Common-mode rejection ratio
1.5 V < VCM < 5.5 V
75
95
dB
PSRR
Power-supply rejection ratio
12 V < VCC < 20 V
85
110
dB
IO(sink)
Output sink current
VEAOUT = 1 V
1
2.5
mA
IO(src)
Output source current
VEAOUT = 4 V
High-level output voltage
IEAOUT = –0.5 mA
Low-level output voltage
IEAOUT = –1 mA
Gain bandwidth product
f = 200 kHz
Slew rate (1)
–1.3
–0.5
mA
4.5
4.7
5
0
0.5
1
6
12
MHz
6
9
V/ms
V
V
PWM Comparator
IBIAS
Bias current, RAMP
VRAMP = 0 V
–1
Minimum duty cycle
–8
mA
0%
Maximum duty cycle
85%
tLEB
Leading-edge blanking time
RLEB = 2 kΩ, CLEB = 470 pF
300
375
450
ns
RLEB
Leading-edge blanking resistance
VCLK/LEB = 3 V
8.5
10
11.5
kΩ
VZDC
Zero dc threshold voltage, EAOUT
VRAMP = 0 V
1.1
1.25
1.4
V
tDELAY
Delay-to-output time (1)
VEAOUT = 2.1 V, VILIM = 0-V to 2-V step
50
80
ns
(1)
Specified by design. Not production tested.
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
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Electrical Characteristics (continued)
TA = –40°C to 125°C for Q temperature and TA = –55°C to 125°C for M temperature, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20
mA
Current Limit/Start Sequence/Fault
ISS
Soft-start charge current
VSS
Full soft-start threshold voltage
IDSCH
Restart discharge current
ISS
Restart threshold voltage
IBIAS
ILIM bias current
ICL
Current-limit threshold voltage
Overcurrent threshold voltage
td
Delay-to-output time, ILIM
VSS = 2.5 V
8
14
4.3
5
100
250
350
mA
0.3
0.5
V
15
mA
0.95
1
1.05
V
1.14
1.2
1.26
V
50
80
ns
IOUT = 20 mA
0.25
0.4
IOUT = 200 mA
1.2
2.2
IOUT = 20 mA
1.9
2.9
2
3
20
45
ns
VSS = 2.5 V
VILIM = 0-V to 2-V step
(2)
VILIM = 0-V to 2-V step
V
Output
Low-level output saturation voltage
High-level output saturation voltage
tr, tf
Rise/fall time (2)
IOUT = 200 mA
CL = 1 nF
V
V
Undervoltage Lockout (UVLO)
Start threshold voltage
8.4
9.2
9.6
V
UVLO hysteresis
0.4
0.8
1.2
V
100
300
mA
28
36
mA
Supply Current
Isu
Startup current
ICC
Input current
(2)
6
VC = VCC = VTH(start) – 0.5 V
Specified by design. Not production tested.
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
APPLICATION INFORMATION
The oscillator of the UC2825A-EP is a sawtooth. The rising edge is governed by a current controlled by the RT
pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for the outputs.
Selection of RT should be done first, based on desired maximum duty cycle. CT then can be chosen, based on
the desired frequency (RT) and DMAX. The design equations are:
RT +
3V
(10 mA) ǒ1 * DMAXǓ
CT +
ǒ1.6
ǒR T
D MAXǓ
(1)
fǓ
Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended.
IR
RT
3V
IC−IR
CT
CLK
ID = 10 mA
R
LEB
VTH
C
UDG−95102
Figure 1. Oscillator
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
100
10 M
DMAX − Maximum Duty Cycle − %
f − Frequency − Hz
95
1M
100 k
90
85
80
75
10 k
70
1k
10 k
100 k
1k
RT − Timing Resistance − W
Figure 2.
10 k
RT − Timing Resistance − W
100 k
Figure 3.
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UC2825A-EP
SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
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Leading-Edge Blanking (LEB)
The UC2825A-EP performs fixed-frequency PWM control. The UC2825A-EP outputs are alternately controlled.
During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying
in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is
controlled by the PWM comparator, current-limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error-amplifier output) and terminates
the pulse. LEB causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse.
This allows noise inherent with switched-mode power conversion to be rejected. The PWM ramp input may not
require any filtering as a result of LEB.
To program an LEB period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal
10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy, an
external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of
2.4%. The design equation is:
t LEB + 0.5
ǒR ø 10 kWǓ
(2)
C
Values of R less than 2 kΩ should not be used.
LEB also is applied to the current-limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold, the
pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent
faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set, and the outputs are
driven low. For this reason, some noise filtering may be required on the ILIM pin.
CT
CLK/LEB
LEB
RAMP
Input
Blanked
RAMP
to PWM
UDG−95105
Figure 4. LEB Operational Waveforms
8
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
Undervoltage Lockout (UVLO), Soft-Start, and Fault Management
Soft-start is programmed by a capacitor on the soft-start (SS) pin. At power up, SS is discharged. When SS is
low, the error-amplifier output also is forced low. While the internal 9-mA source charges SS, the error-amplifier
output follows until closed-loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap then is
discharged by a 250-mA current sink. No more output pulses are allowed until soft-start is fully discharged and
ILIM is below 1.2 V. At this point, the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are terminated immediately, but the soft-start capacitor
does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous
fault conditions.
1.2 V
FAULT
5V
VSS
1.2 V
0.2 V
ON
PWM
OFF
UDG−95106
Figure 5. Soft-Start and Fault Waveforms
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Active-Low Outputs During UVLO
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to
operate.
3
–555C
VOUT – V
2
255C
1
VCC = OPEN
0
0
0.2
0.4
0.6
0.8
1.0
Current – A
UDG−95108
Figure 6. Output Voltage vs Output Current
VCC
250 mA
OUT
50 k
UVLO
Q2
Q1
Q3
Q4
PGND
UDG−95106
Figure 7. Output V and I During UVLO
Control Methods
Current Mode
Voltage Mode
ISWITCH
Oscillator
CT
Oscillator
CT
CT
1.25 V
RSENSE
1.25 V
Ramp
From E/A
CT
Ramp
UDG−95109
From E/A
UDG−95110
Figure 8. Control Methods
10
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
Synchronization
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the
free-running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The
pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge
of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that CLK/LEB no longer
accepts an incoming synchronizing signal.
RT
5
VSYNC
39 W
CT
6
10 W
50-W
External
Clock
UDG−95111
Figure 9. General Oscillator Synchronization
4
39 pF
120 W
CT
6
4.7 k
Master
22 W
CT
Slave
6
RT
5
1.15 RT
5
UDG−95113
Figure 10. Two-Unit Interface
VSYNC
VCT
UDG−95112
Figure 11. Operational Waveforms
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High-Current Outputs
Each totem-pole output of the UC2825A-EP can deliver a 2-A peak current into a capacitive load. The output can
slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground
(PGND) pins help decouple the device analog circuitry from the high-power gate drive noise. The use of 3-A
Schottky diodes (1N5120, USD245, or equivalent) (see Figure 13) from each output to both VC and PGND are
recommended. The diodes clamp the output swing to the supply rails, necessary with any type of
inductive/capacitive load, typical of a MOSFET gate. Schottky diodes must be used because a low forward
voltage drop is required. Do not use standard silicon diodes.
VC
VC
1 nF
10 mF
D1
OUT
6.8 W
D2
PGND
GND
D1, D2 = 1N5820
UDG−95114
Figure 12. Power MOSFET Drive Circuit
12
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
Ground Planes
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct
operation of the chip. A ground plane must be employed. A unique section of the ground plane must be
designated for high di/dt currents associated with the output stages. This point is the power ground to which the
PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a
single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC
should be bypassed directly to power ground with a good high-frequency capacitor. The sources of the power
MOSFET should connect to power ground as should the return connection for input power to the system and the
bulk input capacitor. The output should be clamped with a high-current Schottky diode to both VCC and PGND.
Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high-frequency
capacitor. Low-ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog
circuitry likewise, should be bypassed to the signal ground plane.
VC
To Analog
Circuitry
VCC
CT
VIN
VCC
Power
Stage
CBULK
OUT
VREF
GND
PGND
Signal Ground
RTN
Power Ground
UDG−95115
Figure 13. Ground Planes
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Open-Loop Test Circuit
This test fixture is useful for exercising many functions of this device family and measuring their specifications.
As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground
plane is highly recommended.
UC2825A-EP
CLK/LEB
CLEB
3.65 kW
CT
RT
1 mF
VCC
0.1 mF
15 V
10 mF
Oscillator
CT
15 V
10 mF
VC
0.1 mF
RAMP
OUTA
EAOUT
50 W
22 kW 27 kW
4.7 kW
OUTB
68 kW
INI
10 kW
INV
Error
Amplifier
1N5820 (*4)
PGND
27 kW
SS
4.7 kW
10 kW
3.8 kW
GND
10 mF
ILIM
5.1 V
VREF
0.1 mF
Figure 14. Open-Loop Test Circuit
14
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
UC2825AMDWREP
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
UC2825AMEP
Samples
UC2825AQDWREP
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UC2825AQEP
Samples
V62/05616-01XE
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UC2825AQEP
Samples
V62/05616-02XE
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
UC2825AMEP
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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