UC2848DW

application INFO available UC1848 UC2848 UC3848 Average Current Mode PWM Controller FEATURES BLOCK DIAGRAM • Practical Primary Side Control of Isolated Power Supplies with DC Control of Secondary Side Current • Accurate Programmable Maximum Duty Cycle Clamp • Maximum Volt-Second Product Clamp to Prevent Core Saturation • Practical Operation Up to 1MHz • High Current (2A Pk) Totem Pole Output Driver • Wide Bandwidth (8MHz) Current Error Amplifier • Under Voltage Lockout Monitors VCC, VIN and VREF • Output Active Low During UVLO • Low Startup Current (500µA) • Precision 5V Reference (1%) UDG-93003-1 DESCRIPTION The UC3848 family of PWM control ICs makes primary side average current mode control practical for isolated switching converters. Average current mode control insures that both cycle by cycle peak switch current and maximum average inductor current are well defined and will not run away in a short circuit situation. The UC3848 can be used to control a wide variety of converter topologies. In addition to the basic functions required for pulse width modulation, the UC3848 implements a patented technique of sensing secondary current in an isolated buck derived converter from the primary side. A current waveform synthesizer monitors switch current and simulates the inductor current down slope so that the complete current waveform can be constructed on the primary side without actual secondary side measurement. This information on the primary side allows for full DC control of output current. The UC3848 circuitry includes a precision reference, a wide bandwidth error amplifier for average current control, an oscillator to generate the system clock, latching PWM comparator and logic circuits, and a high current SLUS225A - April 1996 - REVISED MARCH 2004 output driver. The current error amplifier easily interfaces with an optoisolator from a secondary side voltage sensing circuit. A full featured undervoltage lockout (UVLO) circuit is contained in the UC3848. UVLO monitors the supply voltage to the controller (VCC), the reference voltage (VREF), and the input line voltage (VIN). All three must be good before soft start commences. If either VCC or VIN is low, the supply current required by the chip is only 500µA and the output is actively held low. Two on board protection features set controlled limits to prevent transformer core saturation. Input voltage is monitored and pulse width is constrained to limit the maximum volt-second product applied to the transformer. A unique patented technique limits maximum duty cycle within 3% of a user programmed value. These two features allow for more optimal use of transformers and switches, resulting in reduced system size and cost. Patents embodied in the UC3848 belong to Lambda Electronics Incorporated and are licensed for use in applications employing these devices. UC1848 UC2848 UC3848 ABSOLUTE MAXIMUM RATINGS Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . . −65°C to +150°C Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C Supply Voltage (Pin 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V Output Current, Source or Sink (Pin 14) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ± 0.2V Analog Input Voltages (Pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . –0.3 to 7V Analog Input Currents, Source or Sink (Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA CONNECTION DIAGRAMS PLCC-20 & LCC-20 (Top View) Q & L Packages DIL-16, SOIC-16 (Top View) J, N, or DW Packages PACKAGE PIN FUNCTION FUNCTION PIN N/C 1 GND 2 VREF 3 NI 4 INV 5 N/C 6 CAO 7 CT 8 VS 9 DMAX 10 N/C 11 CDC 12 CI 13 IOFF 14 ION 15 N/C 16 PGND 17 OUT 18 VCC 19 UV 20 THERMAL RATINGS TABLE Package DIL-16J DIL-16N SOIC-16DW PLCC-20 LCC-20 QJA 80-120 90(1) 50-100(1) 43-75(1) 70-80 QJC 28(2) 45 27 34 20(2)(3) Q Q Q 2 UC1848 UC2848 UC3848 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP 0.95 1 20 25 MAX UNITS Real Time Current Waveform Synthesizer Ion Amplifier Offset Voltage Slew Rate (Note 1) lib 1.05 V V/µs -2 -20 µA IOFF Current Mirror Input Voltage 0.95 1 1.05 V Current Gain 0.9 1 1.1 A/A 60 100 10 mV -3 µA Current Error Amplifier AVOL Vio 12V ≤ VCC 20V, 0V VCM 5V lib -0.5 Voh IO = −200µA Vol IO = 200µA Source Current VO = 1V GBW Product f = 200kHz 3 Slew Rate (Note 1) dB 3.3 V 0.3 0.6 V 1.4 1.6 2.0 5 8 MHz 8 10 V/µs 240 250 mA Oscillator Frequency TA = 25°C 235 Ramp Amplitude 260 kHz 265 kHz 1.5 1.65 1.8 V 73.5 76.5 79.5 % 1100 ns 14 V Duty Cycle Clamp Max Duty Cycle V(DMAX) = 0.75 • VREF Volt Second Clamp Max On Time 900 VCC Comparator Turn-on Threshold 13 Turn-off Threshold Hysteresis 3 9 10 2.5 3 V 3.5 V UC1848 UC2848 UC3848 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS UV Comparator Turn-on Threshold RHYSTERESIS 4.1 4.35 4.6 V Vuv = 4.2V 77 90 103 kΩ TA = 25°C 4.95 5 5.05 V 0 < IO < 10mA, 12 < VCC < 20 4.93 Reference VREF Line Regulation 12 < VCC < 20V Load Regulation 0 < IO < 10mA Short Circuit Current VREF = 0V 4 30 5.07 V 15 mV 3 15 mV 50 70 mA Output Stage Rise & Fall Time (Note 1) Cl = 1nF 20 45 ns Output Low Saturation IO = 20mA 0.25 0.4 V IO = 200mA 1.2 2.2 V Output High Saturation IO = -200mA 2.0 3.0 V UVLO Output Low Saturation IO = 20mA 0.8 1.2 V ISTART VCC = 12V 0.2 0.4 mA ICC (pre-start) VCC = 15V, V(UV) = 0 0.5 1 mA 22 26 mA ICC ICC (run) APPLICATION INFORMATION Under Voltage Lockout When the UV comparator is low, ICC is low (500µA) and the output is low. The Under Voltage Lockout block diagram is shown in Fig 1. The VCC comparator monitors chip supply voltage. Hysteretic thresholds are set at 13V and 10V to facilitate off-line applications. If the VCC comparator is low, ICC is low (T(osc) / 80k, where T(osc) is the oscillator period. CDC also sets the soft start time constant, so values of CDC larger than minimum may be desired. The soft start time constant is approximately: T(ss) = 20k • CDC. UDG-93012-1 8 UDG-93013-1 UC1848 UC2848 UC3848 UDG-93014 UDG-93015 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) UC1848J OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 UC2848DW LIFEBUY SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2848DW UC2848DWG4 LIFEBUY SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2848DW UC2848J OBSOLETE CDIP J 16 TBD Call TI Call TI -40 to 85 UC3848DW LIFEBUY SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3848DW UC3848DWG4 LIFEBUY SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3848DW UC3848DWTR LIFEBUY SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3848DW UC3848N LIFEBUY PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3848N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF UC1848, UC3848 : • Catalog: UC3848 • Military: UC1848 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UC3848DWTR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC3848DWTR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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