UC2853AD

a pplica tion INFO a va ila ble UC2853A High Power Factor Preregulator FEATURES DESCRIPTION • Complete 8-pin Power Factor Solution • Reduced External Components • RMS Line Voltage Compensation • Precision Multiplier/Squarer/Divider • Internal 63kHz Synchronizable Oscillator The UC2853A provides simple, yet high performance active power factor correction. Using the same control technique as the UC1854, this 8-pin device exploits a simplified architecture and an internal oscillator to minimize external component count. The UC2853A incorporates a precision multiplier/squarer/divider circuit, voltage and current loop error amplifiers, and a precision voltage reference to implement average current mode control with RMS line voltage compensation. This control technique maintains constant loop gain with changes in input voltage, which minimizes input line current distortion over the worldwide input voltage range. • Average Current Mode PWM Control • Overvoltage Protection Comparator • High Current, Clamped Gate Driver The internal 63kHz oscillator includes an external clock input, allowing synchronization to downstream converters. Additionally, the device features an overvoltage protection comparator, a clamped MOSFET gate driver which self-biases low during undervoltage lockout, and low startup and supply current. The UC2853A is identical to the UC2853 except the internal oscillator frequency has been reduced from 75kHz to 63kHz. The switching frequency is lowered in order to keep the second harmonic of the switching frequency below a 150kHz. For EMI specifications at 150kHz this makes it easier for a design to meet system requirements. BLOCK DIAGRAM These devices are available in 8-pin PDIP (P) and SOIC (D) packages. The UC2853A is specified for operation from –40°C to 105°C. UDG-94120-1 SLUS650A - FEBRUARY 2005 - REVISED JANUARY 2006 UC2853A CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Output Drive Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.125A Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Output Minimum Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V IAC Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 1mA IMO Maximum Output Current . . . . . . . . . . . . . . . . . . . . . –2mA IMO Minimum Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V FB Maximum Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5V VCOMP Maximum Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 6.2V ICOMP Sourcing Current . . . . . . . . . . . . . . . . . . . . Self-Limiting ICOMP Sinking Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA ICOMP Maximum Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7.2V Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C All voltages with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. PDIP-8, SOIC-8 (Top View) P or D Package ELECTRICAL CHARACTERISTICS Unless otherwise stated, these parameters apply for TA = –40°C to 105°C for the UC2853A; VCC = 16V, VFB = 3V, IAC = 100mA, VVCOMP = 3.75V, VICOMP = 3V, TA = T J. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 11.5 13 V 1.8 2.1 V Undervoltage Lockout Section VCC Turn-on Threshold VVCOMP, VICOMP Open Hysteresis 1.5 Supply Current Section IVCC Startup VCC = 8V, IAC = 100mA; VVCOMP, VICOMP Open 250 500 mA IVCC IAC = 0mA, VICOMP = 0V 10 15 mA 575 mmho 640 mmho Voltage Loop Error Amplifier Section Transconductance Input Voltage IOUT = ± 20mA 0-70C 300 Temperature 135 0-70C 2.925 Temperature 2.9 AVOL VVCOMP = 1V – 4V 50 Output Sink Current VFB = 3.2V, VVCOMP = 3.75V 20 Output Source Current VFB = 2.8V, VVCOMP = 3.75V Output Voltage High 450 3 5.5 V 3.1 V 60 dB mA 50 –50 Output Voltage Low 3.075 –20 mA 0.9 V 6 mV 6 0.6 V Current Loop Error Amplifier Section Offset Voltage Voltage Gain 0 VICOMP = 1V – 4V Sink Current VIMO = 100mV, VICOMP = 3V Source Current VIMO = –0.1V, VICOMP = 3V 70 1 mA –150 Output High IICOMP = –50mA Output Low IICOMP = 50mA 6 0.3 PWM Modulator Gain VICOMP = 2V – 3V (Note 1) 20 2 dB –80 mA 0.8 V 6.8 V %/V 1 UC2853A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these parameters apply for TA = –40°C to 105°C for the UC2853A; VCC = 16V, VFB = 3V, IAC = 100mA, VVCOMP = 3.75V, VICOMP = 3V, TA = T J. (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS –230 –200 –170 mA Multiplier Section Output Current – IAC Limited VCC = 11V, VVCOMP = 6V Output Current – Zero IAC = 0mA Output Current – Power Limited VCC = 12V, VVCOMP = 5.5V Output Current –2 –0.2 2 mA –236 –178 –168 mA VCC= 12V, VVCOMP = 2V –22 mA VCC= 12V, VVCOMP = 5V –156 mA VCC= 40V, VVCOMP = 2V –2 mA VCC= 40V, VVCOMP = 5V Multiplier Gain Constant VCC= 12V, VVCOMP = 5.5V (Note 2) mA –14 –1.05 –0.9 –0.75 V –1 Oscillator Section Oscillator Initial Frequency TA = 25°C 56 63 70 kHz Oscillator Frequency Line, Load, Temperature 50 63 74 kHz 100 kHz Synchronization Frequency Range Synchronization Pulse Amplitude Pulse slew rate = 100V/msec (Note 3) 2 V Output Driver Section Maximum Output Voltage Output High 0mA load, VCC = 20V 0mA load, VCC = 12V, ref. to VCC –50mA load, VCC = 12V, ref. to VCC Output Low (Device Inactive) 12 15 17.5 V –2.7 –1.7 V –3 –2.2 V Vcc = 0V, 20mA load (Sinking) 0.9 2.0 V Output Low (Device Active) 50mA load (Sinking) 0.5 1 V OUT Rise Time 1nF from OUT to GND 55 100 ns OUT Fall Time 1nF from OUT to GND 35 100 ns OUT Maximum Duty Cycle VICOMP = 0V 88 93 Volts Above EA Input V 90 150 mV 80 mV % OVP Comparator Section Threshold Voltage Hysteresis Note 1: 1PWM modulator gain = Note 2: Gainconstant (K ) = DDutyCycle DVICOMP IAC · (VCOMP – 1. 5V ) VCC IMO ·VCC · , VCC = 12V. 64 Note 3. Synchronization is accomplished with a falling edge of 2V magnitude and 100V/msec slew rate. 3 UC2853A UC2853A TYPICAL APPLICATION UC2853A Note: the application circuit shown is a 100W, 63KHz design. Additional application information can be found in Application Note U–159 (TI literature Number SLUA080) and Design Note DN–78. 4 UC2853A PIN DESCRIPTIONS FB: Voltage Amplifier Inverting Input, Overvoltage Comparator Input, Sync Input. This pin serves three functions. FB accepts a fraction of the power factor corrected output voltage through a voltage divider, and is nominally regulated to 3V. FB voltages 5% greater than nominal will trip the overvoltage comparator, and shut down the output stage until the output voltage drops 5%. The internal oscillator can be synchronized through FB by injecting a 2V clock signal though a capacitor. To prevent false tripping of the overvoltage comparator, the clock signal must have a fast falling edge, but a slow rising edge. See Application Note U-159 for more information. vents excessive MOSFET gate-to-source voltage so that the UC2853A can be operated with VCC and high as 40V. A series gate resistor of at least 5 ohms should be used to minimize clamp voltage overshoot. In addition, a Schottky diode such as a 1N5818 connected between OUT and GND may be necessary to prevent parasitic substrate diode conduction. ICOMP: Current Loop Error Amplifier Output. The current loop error amplifier is a conventional operational amplifier with a 150mA current source class A output stage. Compensate the current loop by placing an impedance between ICOMP and IMO. This output can swing above the oscillator peak voltage, allowing zero duty cycle when necessary. GND: Ground. All voltages are measured with respect to GND. The VCC bypass capacitor should be connected to ground as close to the GND pin as possible. VCC: Input Supply Voltage. This pin serves two functions. It supplies power to the chip, and an input voltage level signal to the squarer circuit. When this input is connected to a DC voltage proportional to the AC input RMS voltage, the voltage loop gain is reduced by IAC: AC Waveform Input. This input provides voltage waveform information to the multiplier. The current loop will try to produce a current waveform with the same shape as the IAC signal. IAC is a low impedance input, nominally at 2V, which accepts a current proportional to the input voltage. Connect a resistor from the rectified input line to IAC which will conduct 500mA at maximum line voltage. 64 VCC 2 . This configuration maintains constant loop gain. The UC2853A input voltage range extends from 12V to 40V, allowing an AC supply voltage range in excess of 85VAC to 265VAC. Bypass VCC with at least a 0.1mF ceramic capacitor to ensure proper operation. See the Applications section for the recommended circuit configuration. IMO: Multiplier Output and Current Sense Inverting Input. The output of the multiplier and the inverting input of the current amplifier are connected together at IMO. Avoid bringing this input below –0.5V to prevent the internal protection diode from conducting. The multiplier output is a current, making this a summing node and allowing a differential current error amplifier configuration to reject ground noise. The input resistance at this node should be 3.9k to minimize input bias current induced offset voltage. See the Applications section for the recommended circuit configuration. VCOMP: Voltage Loop Error Amplifier Output. The voltage loop error amplifier is a transconductance type operational amplifier. A feedback impedance between VCOMP and FB for loop compensation must be avoided to maintain proper operation of the overvoltage protection comparator. Instead, compensate the voltage loop with an impedance between VCOMP and GND. When VCOMP is below 1.5V, the multiplier output current is zero. OUT: Gate Driver Output. OUT provides high current gate drive for the external power MOSFET. A 15V clamp pre- 5 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device UC2853ADTR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2853ADTR SOIC D 8 2500 356.0 356.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) UC2853AD D SOIC 8 75 506.6 8 3940 4.32 Pack Materials-Page 3 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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