UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
IMPROVED CURRENT MODE PWM CONTROLLER
Check for Samples: UC2856Q
FEATURES
1
•
•
•
•
•
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•
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DW PACKAGE
(TOP VIEW)
Pin-for-Pin Compatible With the UC2846
65-ns Typical Delay From Shutdown to
Outputs and 50-ns Typical Delay From
Sync to Outputs
Improved Current Sense Amplifier With
Reduced Noise Sensitivity
Differential Current Sense With 3-V
Common Mode Range
Trimmed Oscillator Discharge Current for
Accurate Deadband Control
Accurate 1-V Shutdown Threshold
High Current Dual Totem Pole
Outputs (1.5-A peak)
TTL Compatible Oscillator SYNC Pin
Thresholds
4-kV ESD Protection
1
2
3
4
5
6
7
8
CL SS
VREF
CS−
CS+
EA+
EA−
COMP
CT
16
15
14
13
12
11
10
9
SHUTDOWN
VIN
BOUT
VC
GND
AOUT
SYNC
RT
P0008-01
DESCRIPTION
The UC2856 is a high performance version of the popular UC2846 series of current mode controllers, and is
intended for both design upgrades and new applications where speed and accuracy are important. All input to
output delays have been minimized, and the current sense output is slew rate limited to reduce noise sensitivity.
Fast 1.5-A peak output stages have been added to allow rapid switching of power FETs.
A low impedance TTL compatible sync output has been implemented with a 3-state function when used as a
sync input.
Internal chip grounding has been improved to minimize internal noise caused when driving large capacitive
loads. This, in conjunction with the improved differential current sense amplifier, results in enhanced noise
immunity.
Other features include a trimmed oscillator current (8%) for accurate frequency and dead time control; a 1 V, 5%
shutdown threshold; and 4 kV minimum ESD protection on all pins.
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
PACKAGE
SOP–DW
Tape and reel
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
UC2856QDWR
UC2856Q
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2011, Texas Instruments Incorporated
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
5.1 V
Reference
Regulator
VIN 15
2
VREF
SYNC 10
RT
UV
Lockout
9
13 VC
OSC
CT
8
FF
11 AOUT
Q
T
4.1 V
CS−
3
−
X3
CS+
Q
+
COMP
+
4
R
S
−
Q
−
S
0.5 V
14 BOUT
+
0.5 mA
EA+
5
−
EA−
6
+
12 GND
EA
1
COMP
7
CL SS
16 SHUTDOWN
+
6 kΩ
−
1V
B0010-01
ORDERING INFORMATION
UC
285
6
Q
DW
R
Tape and Reel Indicator
Package
DW = Plastic SOIC
Temperature Indicator
Q = −405C to 1255C
2
Copyright © 2004–2011, Texas Instruments Incorporated
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
UNIT
Supply voltage
40 V
Collector supply voltage
IO
Output current (sink or source)
40 V
DC
0.5 A
Pulse (0.5 ms)
2A
Error amplifier input voltage
–0.3 V to VIN
Shutdown input voltage
–0.3 V to 10 V
Current sense input voltage
–0.3 V to 3 V
±10 mA
SYNC output current
Error amplifier output current
-5 mA
Soft start sink current
50 mA
Oscillator charging current
Power dissipation
5 mA
TA = 25°C
1W
TC = 25°C
2W
TJ
Operating junction temperature range
–55°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals.
ELECTRICAL CHARACTERISTICS
TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.05
5.1
5.15
UNIT
REFERENCE SECTION
Output voltage
IO = 1 mA,
Line regulation voltage
VIN = 8 V to 40 V
TJ = 25°C
Load regulation voltage
IO = –1 mA to –10 mA
Total output variation
Line, Load, and Temperature
Output noise voltage
f = 10 Hz to 10 kHz,
Long term stability
1000 hours,
Short circuit current
VREF = 0 V
5
V
20
mV
15
mV
5.2
V
µV
TJ = 25°C
50
TJ = 25°C
5
25
mV
–25
–45
–65
mA
TJ = 25°C
180
200
220
TJ = Full range
170
(2)
OSCILLATOR SECTION
Initial accuracy
Voltage stability
230
VIN = 8 V to 40 V
2%
7.5
8
8.8
VCT = 2 V
6.7
8
8.8
Sync output high level voltage
IO = –1 mA
2.4
3.6
Sync output low level voltage
IO = 1 mA
Sync input high level voltage
CT = 0 V, RT = VREF
Sync input low level voltage
CT = 0 V, RT = VREF
Sync input current
CT = 0 V, RT = VREF,VSYNC = 5 V
Sync delay to outputs
CT = 0 V RT = VREF, VSYNC = 0.8 V to 2 V
Discharge current
(1)
(2)
VCT = 2 V,
kHz
TJ = 25°C
0.2
2
mA
V
0.4
1.5
V
V
1.5
0.8
V
1
10
µA
50
100
ns
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
This parameter, although specified over the recommended operating conditions, is not 100% tested in production.
Copyright © 2004–2011, Texas Instruments Incorporated
3
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER SECTION
Input offset voltage
VCM = 2 V
Input bias current
Input offset current
5
mV
–1
µA
500
nA
Common mode range
VIN = 8 V to 40 V
0
Open loop gain
VO = 1.2 V to 3 V
80
100
dB
Unity gain bandwidth
TJ = 25°C
1
1.5
MHz
CMRR
VCM = 0 V to 38 V,
75
100
dB
PSRR
VIN = 8 V to 40 V
80
100
dB
Output sink current
VID = -15 mV
VCOMP = 1.2 V
5
10
mA
Output source current
VID = 15 mV
VCOMP = 2.5 V
–0.4
–0.5
High-level output voltage
VID = 50 mV,
RL (COMP) = 15 kΩ
4.3
4.6
4.9
V
Low-level output voltage
VID = –50 mV,
RL (COMP) = 15 kΩ
0.7
1
V
Amplifier gain
VCS– = 0 V,
CL SS Open (3)
2.5
2.75
3
V/V
Maximum differential input signal (VCS+ – VCS–)
CL SS Open 3,
RL (COMP) = 15 kΩ
1.1
1.2
Input offset voltage
VCL
COMP open (3)
35
mV
CMRR
VCM = 0 V to 3 V
60
PSRR
VIN = 8 V to 40 V
60
Input bias current
VCL
SS = 0.5 V,
COMP open (3)
Input offset current
VCL
SS
= 0.5 V,
COMP open (3)
VIN = 40 V
VIN–2
V
mA
CURRENT SENSE AMPLIFIER SECTION
SS = 0.5 V
(4)
Input common mode range
Delay to outputs
5
dB
dB
0
VEA+ = VREF, EA– = 0 V, CS+ – CS– = 0 V to 1.5 V
V
120
–1
µA
1
mA
3
V
250
ns
CURRENT LIMIT ADJUST SECTION
Current limit offset
VCS– = 0 V, VCS+ = 0 V,
COMP Open (3)
Input bias current
VEA+ = VREF,
VEA– = 0 V
0.4
0.5
0.6
V
–10
–30
µA
1.00
1.05
V
SHUTDOWN TERMINAL SECTION
Threshold voltage
0.95
Input voltage range
0
(5)
Minimum latching current (ICL SS)
3
1.5
(6)
Maximum non-latching current (ICL SS)
Delay to outputs
5
VSHUTDOWN = 0 V to 1.3 V
V
mA
1.5
0.8
mA
65
110
ns
OUTPUT SECTION
Collector-emitter voltage
Off-state bias current
Output low level voltage
Output high level voltage
40
VC = 40 V
0.1
0.5
IOUT = 200 mA
0.5
2.6
IOUT = –20 mA
IOUT = –200 mA
C1 = 1 nF
Fall time
C1 = 1 nF
UVLO low saturation
VIN = 0 V,
(4)
(5)
(6)
4
250
IOUT = 20 mA
Rise time
(3)
V
12.5
13.2
12
13.1
40
IOUT = 20 mA
µA
V
V
80
ns
40
80
ns
0.8
1.5
V
Parameter measured at trip point of latch with VEA+ = VREF, VEA- = 0 V.
DV
COMP ; DV
G+
CS * + 0 V 1 V.
DV CS)
Amplifier gain defined as:
Current into CL SS assured to latch circuit into shutdown state.
Current into CL SS assured not to latch circuit into shutdown state.
Copyright © 2004–2011, Texas Instruments Incorporated
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
45%
47%
50%
UNIT
PWM SECTION
Maximum duty cycle
Minimum duty cycle
0%
UNDERVOLTAGE LOCKOUT SECTION
Startup threshold
7.7
Threshold hysterisis
0.7
8
TOTAL STANDBY CURRENT
Supply current
Copyright © 2004–2011, Texas Instruments Incorporated
18
23
mA
5
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
APPLICATION AND OPERATION INFORMATION
VREF
SAWTOOTH CT
9
COMP
OSC SYNC
8
CT
RT
Output Deadtime (td)
8 mA
10
SYNC
NOTE: Output deadtime is determined by the size of the external capacitor, CT, according to the formula:
For large values of RT: Td + 250 C T
2
ƒT +
Oscillator frequency is approximated by the formula:
RT CT
Td +
2C
T
8 mA * R3.6
T
S0019-01
Figure 1. Oscillator Circuit
NOTE: Error Amplifier can source up to 0.5 mA.
90
VREF
VIN = 20 V
TJ = 25°
5
+
0.5 mA
Zs
−
6
Open-Loop Voltage Gain − dB
80
70
60
50
40
30
20
10
7
0
0
COMP
Zf
lf < 0.5 mA
S0020-01
−10
−90
−20
100
1k
10k
100k
1M
−180
10M
Open-Loop Phase − °
VREF
f − Frequency − Hz
G001
Figure 2. Error Amplifier Output Configuration
6
Figure 3. Error Amplifier Gain and Phase vs
Frequency
Copyright © 2004–2011, Texas Instruments Incorporated
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
110
VIN = 20 V
TJ = 25°
Open-Loop Voltage Gain − dB
105
100
95
90
85
RL
80
75
70
0
10
20
30
40
50
60
70
80
90 100 110
RL − Output Load Resistance − kΩ
G002
Figure 4. Error Amplifier Open-Loop DC Gain vs Load Resistance
9
RT
Master
8
RT
CT
CT
VREF
EA+
SYNC
COMP
EA−
2
5
10
7
6
VOUT
9
2
5
10
7
6
VREF
EA+
SYNC
COMP
EA−
Output
Filters
RT
Slave
(Additional Units)
8
CT
S0021-01
NOTE: Slaving allows parallel operation of two or more units with equal current sharing.
Figure 5. Parallel Operation
Copyright © 2004–2011, Texas Instruments Incorporated
7
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
IS
(+)
4
RS
ISENSE
(−)
X3
COMP
3
−
0.5 V
VREF
+
0.5 mA
R1
EA
1
Current Limit
R2
7
COMP
S0022-01
ǒ
R2
NOTE: Peak current (IS) is determined by the formula:
I +
S
V
Ǔ
REF * 0.5
R1)R2
3RS
Figure 6. Pulse by Pulse Current Limiting
8
Copyright © 2004–2011, Texas Instruments Incorporated
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
VREF
ISENSE
+
R1
1
−
0.5 V
Current Limit
COMP
S
S
ISS
C
R2
EA
VREF
16
SHUTDOWN
+
−
+
-
1.0 V
SHUTDOWN With Auto-Restart
SHUTDOWN Without
Auto-Restart (Latched)
Current Limit
0.5 V
0
Shutdown
On
Off
PWM
S0023-01
NOTE: If VREF / R1 < 0.8 mA, the shutdown latch commutates when ISS = 0.8 mA and a restart cycle will be initiated. If VREF /
R1 > 3 mA, the device will latch off until power is recycled.
Figure 7. Shutdown
Copyright © 2004–2011, Texas Instruments Incorporated
9
UC2856Q
SGLS265A – NOVEMBER 2004 – REVISED MAY 2011
www.ti.com
REVISION HISTORY
Changes from Original (November 2004) to Revision A
•
10
Page
Changed the polarity of the comparator connected to pin 16 in Figure 7 ............................................................................ 9
Copyright © 2004–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UC2856QDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UC2856Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of