UC2879DWG4

UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 PHASE SHIFT RESONANT CONTROLLER FEATURES • • • • • • • • Programmable Output Turn On Delay; Zero Delay Available Compatible with Voltage Mode or Current Mode Topologies Practical Operation at Switching Frequencies to 300 kHz 10-MHz Error Amplifier Pin Programmable Undervoltage Lockout Low Startup Current – 150 µA Soft Start Control Outputs Active Low During UVLO DESCRIPTION The UC3879 controls a bridge power stage by phase shifting the switching of one half-bridge with respect to the other. This allows constant frequency pulse width modulation in combination with resonant, zero-voltage switching for high efficiency performance. The UC3879 can be configured to provide control in either voltage mode or current mode operation, with overcurrent shutdown for fast fault protection. Independently programmable time delays provide dead-time at the turn-on of each output stage, allowing time for each resonant switching interval. BLOCK DIAGRAM Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2007, Texas Instruments Incorporated UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 DESCRIPTION (CONTINUED) With the oscillator capable of operating in excess of 600 kHz, overall output switching frequencies to 300 kHz are practical. In addition to the standard free running mode, with the CLKSYNC pin, the user may configure the UC3879 to accept an external clock synchronization signal. Alternatively, up to three units can be locked together with the operational frequency determined by the fastest device. Protective features include an undervoltage lockout and overcurrent protection. Additional features include a 10-MHz error amplifier, a 5-V precision reference, and soft start. The UC3879 is available in 20 pin N, J, DW, and Q and 28 pin L packages. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT Supply voltage (VC, VIN) PARAMETER 20 V Output current, source or sink, dc 20 Output current, source, sink peak for 0.1 µs at max frequency of 300 kHz 100 mA Analog inputs (Pins 1, 2, 3, 4, 5, 6, 14, 15, 17, 18, 19) –0.3 to 5.3 (Pin 16) V –0.03 to VIN Analog outputs (Pins 7, 8, 12, 13) –0.3 to VC to 0.3 V Storage temperature range –65°C to 150°C Junction temperature –55°C to 150°C Lead temperature (soldering, 10 sec) (1) °C 300°C Pin references are to 20-pin DIL and SOIC packages. All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified terminal. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) (1) (2) (3) 2 PACKAGE θJA θJC J-20 70-85 28 (1) N-20 80 (2) 35 DW-20 SOIC 45-95 (2) 25 PLCC-20 43-75 (2) 34 CLCC-20 N/A 5-8 (2) (3) θJC data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states "The baseline values shown are worst case (mean +2s) for a 60 x 60 mil microcircuit device silicon die and aplicable for devices with die sizes up to 14400 square mils. For devices die sizes greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pacl 10°C/W; pin grid array, 10°C/W". Specified θJA (junction-to-ambient) is for devices mounted to 5-in2 FR4 PC board with one ounce copper wire where noted. When resistance range is given, lower values are for 5-in2 aluminum PC board. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace widths for non-power packages with a 100 x 100 mil probe land area at the end of each trace. θJC estimated for backside of device, through the metalized thermal conduction pads. Submit Documentation Feedback UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 Product Selection Guide TEMPERATURE RANGE AVAILABLE PACKAGES UCC1879 –55°C to 125°C J, L UCC2879 –40°C to 85°C N, DW, Q, J, L UCC3879 0°C to 70°C N, DW, Q DIL-20, SOIC-2 J OR N PACKAGE, DW PACKAGE (TOP VIEW) VREF 1 CLCC-28 L PACKAGE (TOP VIEW) DELSETA-B 20 GND CT COMP 2 EA– 3 CS 4 UVSEL 19 RAMP N/C CLKSYNC 18 RT N/C N/C 17 CLKSYNC 16 UVSEL DELSETC-D 5 SS 6 15 DELSETA-B 9 10 11 3 13 RAMP PWRGND 2 14 GND 15 N/C 1 RT 14 CT OUTC 8 13 OUTA VC 9 12 OUTB VIN 10 11 PWRGND PLCC-20 Q PACKAGE (TOP VIEW) VC 28 16 N/C OUTC 27 17 VREF OUTD 25 24 23 22 21 20 18 COMP N/C EA– N/C CS SS N/C DELSETC-D DELSETC-D SS OUTD CS EA– 3 OUTC 8 4 OUTB VIN OUTD 7 6 7 OUTC 2 1 20 19 4 18 COMP VC 5 17 VREF VIN 6 16 GND PWRGND 7 15 RAMP OUTB 8 14 RT 9 10 11 12 13 OUTA CT CLKSYNC UVSEL DELSETA-B Submit Documentation Feedback 3 UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS Unless specified; VC = VIN = VUVSEL = 12 V, CT = 470 pF, RT = 9.53k, RDELSETA-B = RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01 µF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Undervoltage Lockout Start threshold UVLO hysteresis Input bias, UVSEL pin VUVSEL = VIN 9 10.75 12.5 VUVSEL = Open 12.5 15.25 16.5 VUVSEL = VIN 1.15 1.75 2.15 6 7.4 VUVSEL = Open 5.2 VUVSEL= VIN = 8 V V µA 30 Supply Current IVIN startup VIN = VUVSEL = 8 V, VC = 18 V, IDELSETA-B = IDELSETC-D = 0 150 600 IVC startup VIN = VUVSEL = 8 V, VC = 18 V, IDELSETA-B = IDELSETC-D = 0 10 100 UC3879, UC2879 23 35 UC1879 23 36 4 8 5 5.08 IVIN operating µA IVC operating mA Voltage Reference Output voltage TJ = 25°C 4.92 Line regulation 11 V < VIN < 18 V 1 10 Load regulation IVREF = –10 mA 5 20 Total variation Line, Load, Temperature Short circuit current VREF = 0 V, TJ = 25°C 4.875 5.125 V mV V –60 –15 mA 2.5 2.6 V 0.6 3 µA Error Amplifier Error amplifier input voltage 2.4 Input bias current 4 AVOL 1 V < VCOMP < 4 V 60 90 PSRR 11 V < VIN < 18 V 85 100 Output sink current VCOMP = 1 V 1 2.5 Output source current VCOMP = 4 V Output voltage high ICOMP = –0.5 mA Output voltage low ICOMP = 1 mA Slew rate TA = 25°C Submit Documentation Feedback dB –1.3 –0.5 4 4.7 5 0 0.5 1 6 11 mA V V/µs UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) Unless specified; VC = VIN = VUVSEL = 12 V, CT = 470 pF, RT = 9.53k, RDELSETA-B = RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01 µF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM Comparator RAMP offset voltage TJ = 25°C (1) PWM phase shift, TDELSETA-B, TDELSETC-D = 0 (2) VCOMP> VRAMPpeak+ VRAMPoffset Output skew, TDELSETA-B, TDELSETC-D = 0 (2) VCOMP> VRAMPpeak + VRAMPoffset Ramp to output delay, TDELSETA-B = 0, TDELSETC-D = 0 UC3879, UC2879 115 250 UC1879 115 300 200 220 1 2 VCOMP < Zero Phase Shift Voltage 1.1 1.25 1.4 98% 99.7% 102% 0% 0.3% 2% V 10 VCOMP < Zero Phase Shift Voltage 10 ns Oscillator Initial accuracy TA = 25°C Voltage stability 11 V < VIN < 18 V 180 Total variation Line, Temperature kHz % 160 200 240 CLKSYNC threshold 2.3 2.5 2.7 Clock out high 2.8 4 Clock out low 0.5 1 1.5 Clock out pulse width 400 600 Ramp valley voltage 0.2 0.4 2.8 2.9 3.2 2 10 µA 2.35 2.5 2.65 V 160 300 ns 2 10 µA 2 2.15 V 110 300 ns Ramp peak voltage kHz V ns V Current Limit Input bias VCS = 3 V Threshold voltage Delay to OUTA, B, C, D Cycle-by-Cycle Current Limit Input bias VCS = 2.2 V Threshold voltage 1.85 Delay to output zero phase (1) Ramp offset voltage has a temperature coefficient of about –4 mV/°C. q= (2) 200 f% T Phase shift percentage (0% = 0 , 100% = 180 ) is defined as where is the phase shift, and and T are defined in Figure 1. At 0% phase shift, is the output skew. Submit Documentation Feedback 5 UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) Unless specified; VC = VIN = VUVSEL = 12 V, CT = 470 pF, RT = 9.53k, RDELSETA-B = RDELSEC-D = 4.8k, CDELSETA-B = CDELSETC-D = 0.01 µF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX –3 UNIT Soft Start/Reset Delay Charge current VSS = 0.5 V –20 –9 Discharge current VSS = 1 V 120 230 Restart threshold 4.3 Discharge level µA 4.7 V 300 mV Output Drivers Output Low level IOUT = 10 mA 0.3 0.4 Output High level IOUT = –10 mA, Referenced to VC 2.2 3 Delay Set (3) (3) Delay time (4) RDELSETA-B = RDELSETC-D = 4.8k 250 370 520 Delay time (4) RDELSETA-B = RDELSETC-D = 1.9k 100 155 220 Zero V delay (5) VDELSETA-B = VDELSETC-D = 5 V ns 5 Delay time can be programmed via resistors from the delay set pins to ground. ) ( Delay Time = 0.89 · 10-10 · RDELAY sec (4) The recommended range for RDELAY is 1.9 kΩ to 10 kΩ. Delay time is defined as: æ1 ö delay = T · ç - duty cycle ÷ 2 è ø (5) where T is defined in Figure 1. The zero phase shift voltage is the voltage measured at COMP which forces zero phase shift. This condition corresponds to zero effective output power. Zero phase shift voltage has a temperature coefficient of about –2 mV/°C. DutyCycle = t T Period = T TDHL(A to C) = TDHL (Bto D) = Figure 1. Phase Shift, Output Skew and Delay Time Definitions 6 Submit Documentation Feedback UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 PIN DESCRIPTIONS CLKSYNC (Bi-directional Clock and Synchronization): Used as an output, CLKSYNC provides a clock signal. As an input, this pin provides a synchronization point. Multiple UC3879s, each with their own local oscillator frequency, may be connected together by the CLKSYNC pin, and they will synchronize to the fastest oscillator. This pin may also be used to synchronize the UC3879 to an external clock, provided the frequency of the external signal is higher than the frequency of the local oscillator. CLKSYNC is internally connected to an emitter follower pull-up and a current source pull-down (300 µA typical). Therefore, an external resistor to GND can be used to improve the CLKSYNC pin’s ability to drive capacitive loads. COMP (Error Amplifier Output): This pin is the output of the gain stage for overall feedback control. Error amplifier output voltage levels below 0.9 V forces zero phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving it with a sufficiently low impedance source. CT (Oscillator Frequency Set): After choosing RT to set the required upper end of the linear duty cycle range, the timing capacitor (CT) value is calculated to set the oscillator frequency as follows: CT = Dlin 1.08 · RT · f Connect the timing capacitor directly between CT and GND. Use a high quality ceramic capacitor with low ESL and ESR for best results. A minimum CT value of 200 pF insures good accuracy and less susceptibility to circuit layout parasitics. The oscillator and PWM are designed to provide practical operation to 600 kHz. CS (Current Sense): This pin is the non-inverting input to the two current fault comparators whose references are set internally to fixed values of 2 V and 2.5 V. When the voltage at this pin exceeds 2 V, and the error amplifier output voltage exceeds the voltage on the ramp input, the phase shift limiting overcurrent comparator will limit the phase shifting on a cycle-by-cycle basis. When the voltage at this pin exceeds 2.5 V, the current fault latch is set, the outputs are forced OFF, and a soft start cycle is initiated. If a constant voltage above 2.5 V is applied to this pin the outputs are disabled and held low. When CS is brought below 2.5 V, the outputs will begin switching at 0 degrees phase shift before the SS pin begins to rise. This condition will not prematurely deliver power to the load. DELSETA-B, DELSETC-D (Output Delay Control): The user programmed currents from these pins to GND set the turn on delay for the corresponding output pair. This delay is introduced between the turn off of one switch and the turn on of another in the same leg of the bridge to allow resonant switching to take place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging currents. EA– (Error Amplifier Inverting Input): This is normally connected to the voltage divider resistors which sense the power supply output voltage level. The loop compensation components are connected between this pin and COMP. GND (Signal Ground): All voltages are measured with respect to GND. The timing capacitor on CT, and bypass capacitors on VREF and VIN should be connected directly to the ground plane near GND. OUTA – OUTD (Outputs A-D): The outputs are 100-mA totem pole output drivers optimized to drive FET driver devices. The outputs operate as pairs with a nominal 50% duty cycle. The A-B pair is intended to drive one half-bridge in the external power stage and is synchronized to the clock waveform. The C-D pair drives the other half-bridge with switching phase shifted with respect to the A-B outputs. PWRGND (Power Ground): VC should be bypassed with a ceramic capacitor from VC to the section of the ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should be connected in parallel. PWRGND and GND should be connected at a single point near the chip to optimize noise rejection and minimize DC voltage drops. RAMP (Voltage Ramp): This pin is the input to the PWM comparator. Connect it to CT for voltage mode control. For current mode control, connect RAMP to CS and also to the output of the current sense transformer circuit. Slope compensation can be achieved by injecting a portion of the ramp voltage from CT to RAMP. Submit Documentation Feedback 7 UC1879 UC2879 UC3879 www.ti.com SLUS230B – JUNE 1998 – REVISED JUNE 2007 PIN DESCRIPTIONS (continued) RT (Clock/Sync Duty Cycle Set Pin): The UC3879 oscillator produces a sawtooth waveform. The rising edge is generated by connecting a resistor from RT to GND and a capacitor from CT to GND (see CT pin description). During the rising edge, the modulator has linear control of the duty cycle. The duty cycle jumps to 100% when the voltage on COMP exceeds the oscillator peak voltage. Selection of RT should be done first, based on the required upper end of the linear duty cycle range (Dlin) as follows: RT = 2.5 10 mA · (1 - Dlin ) Recommended values for RT range from 2.5 kΩ to 100 kΩ. SS: Connect a capacitor between this pin and GND to set the soft start time. The voltage at SS will remain near zero volts as long as VIN is below the UVLO threshold. Soft start will be pulled up to about 4.8 V by an internal 9-µA current source when VIN and VREF become valid (assuming a non-fault condition). In the event of a current fault (CS voltage exceeding 2.5 V), soft start will be pulled to GND and then ramp to 4.8 V. If a fault occurs during the soft start cycle, the outputs will be immediately disabled and soft start must fully charge prior to resetting the fault latch. For paralleled controllers, the soft start pins may be paralleled to a single capacitor, but the charge currents will be additive. UVSEL: Connecting this pin to VIN sets a turn on voltage of 10.75 V with 1.5 V of UVLO hysteresis. Leaving the pin open-circuited programs a turn on voltage of 15.25 V with 6 V of hysteresis. VC (Output Switch Supply Voltage): This pin supplies power to the output drivers and their associated bias circuitry. The difference between the output high drive and VC is typically 2.1 V. This supply should be bypassed directly to PWRGND with a low ESR/ESL capacitor. VIN (Primary Chip Supply Voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V for normal operation. To ensure proper functionality, the UC3879 is inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should be bypassed directly to GND with a low ESR/ESL capacitor. NOTE: When VIN exceeds the UVLO threshold the supply current (IIN) jumps from about 100 A to greater than 20 mA. If the UC3879 is not connected to a well bypassed supply, it may immediately enter the UVLO state again. Therefore, sufficient bypass capacity must be added to ensure reliable startup. VREF: This pin provides an accurate 5 V voltage reference. It is internally short circuit current limited. VREF is disabled while VIN is below the UVLO threshold. The circuit is also disabled until VREF reaches approximately 4.75 V. For best results bypass VREF with a 0.1 µF, low ESR/ESL capacitor. ADDITIONAL INFORMATION Please refer to the following Unitrode publications for additional information. The following three topics are available in the Applications Handbook. 1. Application Note U-154, The New UC3879 Phase- Shifted PWM Controller Simplifies the Design of Zero Voltage Transition Full-Bridge Converters, by Laszlo Balogh. 2. Application Note U-136, Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM Controller, by Bill Andreycak. 3. Design Note DN-63, The Current-Doubler Rectifier: An Alternative Rectification Technique for Push-Pull and Bridge Converters, by Laszlo Balogh. 8 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UC2879DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2879DW UC2879DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2879DW UC2879DWTR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2879DW UC2879DWTRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2879DW UC2879N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 UC2879N UC2879NG4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 UC2879N UC3879DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3879DW UC3879DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3879DW UC3879DWTR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3879DW UC3879N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UC3879N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of