UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
LOAD SHARE CONTROLLER
FEATURES
D 2.7-V to 20-V Operation
D 8-Pin Package
D Requires Minimum Number of External
D
D
D
D
D
DESCRIPTION
The UC3902 load share controller is an 8-pin
device that balances the current drawn from
independent, paralleled power supplies. Load
sharing is accomplished by adjusting each
supplies’ output current to a level proportional to
the voltage on a share bus.
Components
Compatible with Existing Power Supply
Designs Incorporating Remote Output
Voltage Sensin
Differential Share Bus
Precision Current Sense Amplifier (40 Gain)
UVLO (Undervoltage Lockout) Circuitry
User Programmable Share Loop
Compensation
The master power supply, which is automatically
designated as the supply that regulates to the
highest voltage, drives the share bus with a
voltage proportional to its output current. The
UC3902 trims the output voltage of the other
paralleled supplies so that they each support their
share of the load current. Typically, each supply is
designed for the same current level although that
is not necessary for use with the UC3902. By
appropriately scaling the current sense resistor,
supplies with different output current capability
can be paralleled with each supply providing the
same percentage of their output current capability
for a particular load.
APPLICATIONS
D Paralelled Power Supplies
GND
1
BIAS
8
VCC
7
SHARE+
6
SHARE−
5
COMP
UVLO
SHARE DRIVE AMPLIFIER
40R
−
+
R
SENSE
2
−
+
+
CURRENT SENSE
AMPLIFIER
ADJ
3
ADJ AMPLIFIER
+
−
35 mV
0.6 V
+
−
ADJR
SHARE SENSE AMPLIFIER
+
+
ERROR AMPLIFIER
−
2.3 V
4
UDG−01141
Copyright © 2002 − 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
DESCRIPTION (continued)
A differential line is used for the share bus to maximize noise immunity and accommodate different voltage drops
in each power converter’s ground return line. Trimming of each converter’s output voltage is accomplished by
injecting a small current into the output voltage sense line, which requires a small resistance (typically 20 Ω to
100 Ω) to be inserted.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UC2902
UC3902
VCC, ADJ
Input voltage range,
range VI
Output current,
current IO
−0.3 to 20
SENSE
−5 to 5
ADJR, COMP
−0.3 to 4
SHARE−, SHARE+
−0.3 to 10
SHARE+
ADJ
2
mA
−1 mA to 30 mA
mA
−40 to 100
Junction temperature range, TJ
−55 to 105
Storage temperature, Tstg
−65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
V
−100 mA to 10 mA
Operating free-air temperature range, TA
(1)
UNIT
°C
300
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are with respect to
GND. Currents are positive into, and negative out of the specified terminal.
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UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 105°C, (unless otherwise noted)
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Power SUPPLY SUPPLY CURRENT
ICC
Supply current
SHARE+ = 1 V,
SENSE = 0 V
VCC = 20 V
4
6
6
10
mA
UNDERVOLTAGE LOCKOUT
VCC
Startup voltage
SHARE+ = 0.2 V, SENSE = 0 V, COMP = 1 V
2.3
2.5
2.7
V
Hysteresis
SHARE+ = 0.2 V, SENSE = 0 V, COMP = 1 V
60
100
140
mV
CURRENT SENSE AMPLIFIER
VIO
RIN
Input offset voltage
0.1 V ≤ V(SHARE+) ≤ 1.1 V
−2.5
−0.5
1.5
mV
SENSE to SHARE gain
0.1 V ≤ V(SHARE+) ≤ 1.1 V
−41
−40
−39
V
0.6
1
1.5
V
VCC = 2.5 V
V(SENSE) = −50 mV
I(SHARE+) = −1 mA
1.2
1.4
VCC = 12 V
V(SENSE) = −250 mV
I(SHARE+) = −1 mA
9.6
10.0
10.4
V
VCC = 20 V
V(SENSE) = −250 mV
I(SHARE+) = −1 mA
9.6
10.0
10.4
VCC = 2.5 V
V(SENSE) = 10 mV
I(SHARE+) = −1 mA
20
50
V(SENSE) = 10 mV
VCC = 12 V
I(SHARE+) = −1 mA
20
50
VCC = 20 V
V(SENSE) = 10 mV
I(SHARE+) = −1 mA
20
50
20
40
Input resistance
SHARE DRIVE AMPLIFIER
VOH
VOL
High-level output voltage,
SHARE+
Low-level output voltage, SHARE+
VO
Output voltage, SHARE+
V(SENSE) = 0 mV, R(SHARE+) = 200 Ω
(SHARE+ to GND)
CMRR
Common mode rejection ratio
0 V ≤ V(SHARE−) ≤ 1 V,
SENSE used as input to amplifier
Load regulation
Load on SHARE+, 1 mA ≤ ILOAD ≤ −20 mA
V(SENSE) = −25 mV
Short circuit current
V(SHARE+) = 0 V,
ISC
Slew rate
mV
50
90
dB
0
20
mV
mA
V(SENSE) = −25 mV
−85
−50
−20
V(SENSE) = 10 mV to −90 mV step
R(SHARE+) = 200 Ω (SHARE+ to GND)
0.12
0.26
0.38
V(SENSE) = −90 mV to 10 mV step
R(SHARE+) = 200 Ω (SHARE+ to GND)
0.12
0.26
0.38
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V/ s
V/μs
3
UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 105°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
8
15
8
15
MAX
UNIT
SHARE SENSE AMPLIFIER
RIN
Input impedance
V(SHARE+) = 1 V,
V(SENSE) = 10 mV
V(SHARE−) = GND
R(SHARE+) = 200 Ω (SHARE+ to GND)
V(SHARE−) = 1 V,
V(SENSE) = 10 mV
kΩ
V(SHARE)
Threshold voltage
V(SENSE) = 0 V
41
70
CMRR
Common mode rejection ratio
0 V ≤ V(SHARE−) ≤ 1 V, V(SENSE) = −2.5 mV
50
60
V(SENSE) = −2.5 mV,
5 nF capacitor from COMP to GND,
1 kΩ resistor from ADJR to GND
50
68
V(SENSE) = −2.5 mV,
5 nF capacitor from COMP to GND,
150 Ω resistor from ADJR to GND
50
66
V(SHARE+) = 0 mV to 10 V step through a 200-Ω
resistor, R(COMP) = 500 Ω,
V(SENSE) = 10 mV, VCC = 10 V
0.2
0.5
0.8
V/μs
3.0
4.5
6.0
mS
−450
−325
−200
80
150
250
AVOL
DESCRIPTION from SHARE+ to
ADJR
Slew rate
100
mV
dB
ERROR AMPLIFIER
gM
Transconductance, SHARE+ to
COMP
200-Ω resistor SHARE+ to GND
IOH
High-level output current
V(COMP) = 1.5 V, SHARE+ ≥ 300 mV
V(SENSE) = −10 mV
IOL
Low-level output current
200-Ω resistor SHARE+ to GND,
V(COMP) = 1.5 V, V(SENSE) = 10 mV
VIO
Input offset voltage
μA
A
15
35
65
mV
1-kΩ resistor ADJR to GND
−2.5 mV ≤ V(SENSE) ≤ −25 mV
−6
0
6
mV/V
ADJR low voltage
200-Ω resistor SHARE+ to GND,
V(SENSE) = 10 mV
−1
0
1
mV
ADJR high voltage
V(SENSE) = 10 mV, V(SHARE+) = 1 V
1.4
1.8
2.1
I(ADJR) = −0.5 mA, V(ADJ) = 2.5 V,
V(SENSE) = 10 mV, V(SHARE+) = 1 V
0.96
0.99
1.02
I(ADJR) = −0.5 mA, V(ADJ) = 20 V,
V(SENSE) = 10 mV, V(SHARE+) = 1 V
0.96
0.99
1.02
I(ADJR) = −10 mA, V(ADJ) = 2.5 V,
V(SENSE) = 10 mV, V(SHARE+) = 1 V
0.96
0.99
1.02
I(ADJR) = −10 mA, V(ADJ) = 20 V,
V(SENSE) = 10 mV, V(SHARE+) = 1 V
0.96
0.99
1.02
ΔVIO/
ΔV(SENSE)
ADJ AMPLIFIER
Current gain ADJR to ADJ
4
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V
A/A
UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
ORDERING INFORMATION
TA
40°C to 85°C
−40°C
0°C to 70°C
(2)
PACKAGE(2)
PART NUMBER
SOIC (D)
UC2902D
Plastic DIP (N)
UC2902N
SOIC (D)
UC3902D
Plastic DIP (N)
UC3902N
The D package is also available taped and reeled. Add an R suffix to the device type (i.e., bq24901DR) for quantities of 3,000 devices per reel.
N PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
GND
SENSE
ADJ
ADJR
1
8
2
7
3
6
4
5
1
2
3
4
GND
SENSE
ADJ
ADJR
VCC
SHARE+
SHARE−
COMP
8
7
6
5
VCC
SHARE+
SHARE−
COMP
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ADJ
3
I
Current output of the adjust amplifier circuit (NPN collector)
ADJR
4
O
Current adjust amplifier range set (NPN emitter)
COMP
5
I/O
Output of the error amplifier, input of the adjust amplifier
GND
1
−
Local power supply return and signal ground
SENSE
2
I
Inverting input of the current sense amplifier
SHARE+
7
I/O
SHARE−
6
I
Reference for SHARE+ pin
VCC
8
I
Local power supply (positive)
Positive input from share bus or drive-to-share bus
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5
UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
APPLICATION INFORMATION
The values of five passive components must be determined to configure the UC3902 load share controller. The
output and return lines of each converter are connected together at the load, with current sense resistor RSENSE
inserted in each negative return line. Another resistor, RADJ, is also inserted in each positive remote sense line.
The differential share bus terminals (SHARE+ and SHARE−) of each UC3902 are connected together
respectively, and the SHARE− node is also connected to the system ground. A typical application is illustrated
in Figure 1.
The load share controller design can be executed by following the next few steps:
Step 1.
R SENSE +
V SHARE(max)
A CSA
I O(max)
(1)
D where ACSA is 40, the gain of the current sense amplifier
At full load, the voltage drop across the RSENSE resistor is IO(max) × RSENSE. Taking into account the gain of the
current sense amplifier, the voltage at full load on the current share bus,
V SHARE(max) +
A CSA
I O(max)
R SENSE
(2)
This voltage must stay 1.5-V below VCC or below 10 V whichever is smaller. VSHARE represents an upper limit
but the designer should select the full scale share bus voltage keeping in mind that every volt on the load share
bus increases the master controller’s supply current by approximately 100 μA times the number of slave units
connected parallel.
Step 2.
RG +
V ADJ(max)
I ADJ(max)
(3)
Care must be taken to ensure that IADJ(max) is low enough so that both the drive current and power dissipation
are within the device’s capability. For most applications, an IADJ(max) current between 5 mA and 10 mA is
acceptable. In a typical application, a 360-Ω RG resistor from the ADJR pin to ground sets IADJ(max) to
approximately 5 mA.
Step 3.
R ADJ +
ǒ
DV O(max) * I O(max)
Ǔ
R SENSE
I ADJ(max)
(4)
RADJ must be low enough to not affect the normal operation of the converter’s voltage feedback loop. Typical
RADJ values are between 20 Ω to100 Ω depending on VO, ΔVO(max) and the selected IADJ(max) value.
Step 4.
CC +
6
gM
2p f C
R ADJ
RG
R SENSE
R LOAD
A CSA
A PWR
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ǒf C Ǔ
(5)
UC2902
UC3902
SLUS232E − DECEMBER 19, 2002 − REVISED JULY 2011
The share loop compensation capacitor, CC is calculated to produce the desired share loop unity gain crossover
frequency, fC. The share loop error amplifier’s transconductance, gM is nominally 4.5 ms. The values of the
resistors are already known. Typically, fC is set to at least one order of magnitude below the converter’s closed
loop bandwidth. The load share circuit is primarily intended to compensate for each converter’s initial output
voltage tolerance and temperature drift, not for differences in their transient response. The term APWR(fc) is the
gain of the power supply measured at the desired share loop crossover frequency, fC. This gain can be
measured by injecting the measurement signal between the positive output and the positive sense terminal of
the power supply.
Step 5.
RC +
2p
1
fC
CC
(6)
A resistor in series with CC is required to boost the phase margin of the load share loop. The zero is placed at
the load share loop crossover frequency, fC.
When the system is powered up, the converter with the highest output voltage tends to source the most current
and take control of the share bus. The other converters increase their output voltages until their output currents
are proportional to the share bus voltage minus 50 mV. The converter which in functioning as the master may
change due to warmup drift and differences in load and line transient response of each converter.
ADDITIONAL INFORMATION
Please refer to the following topic for additional application information.
1. Application Note U−163, (TI Literature No. SLUA128) The UC3902 Load Share Controller and Its
Performance in Distributed Power Systems by Laszlo Balogh
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7
PACKAGE MATERIALS INFORMATION
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5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UC2902DTR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC3902DTR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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5-Jan-2022
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UC2902DTR
SOIC
D
8
2500
340.5
336.1
25.0
UC3902DTR
SOIC
D
8
2500
340.5
336.1
25.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
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5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
UC2902D
D
SOIC
8
75
507
8
3940
4.32
UC2902DG4
D
SOIC
8
75
507
8
3940
4.32
UC2902N
P
PDIP
8
50
506
13.97
11230
4.32
UC3902D
D
SOIC
8
75
507
8
3940
4.32
UC3902DG4
D
SOIC
8
75
507
8
3940
4.32
UC3902N
P
PDIP
8
50
506
13.97
11230
4.32
Pack Materials-Page 3
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