UC1548
UC2548
UC3548
Primary Side PWM Controller
FEATURES
•
Primary Side Voltage Feedforward Control of Isolated Power
Supplies
•
Accurate DC Control of
Secondary Side Short Circuit
Current using Primary Side
Average Current Mode Control
•
Accurate Programmable
Maximum Duty Cycle Clamp
•
Maximum Volt-Second Product
Clamp to Prevent Core Saturation
•
Practical Operation Up to 1MHz
•
High Current (2A Pk) Totem Pole
Output Driver
•
Wide Bandwidth (8MHz) Current
Error Amplifier
•
Undervoltage Lockout Monitors
VCC, VIN and VREF
•
Output Active Low During UVLO
•
Low Startup Current (500µA)
BLOCK DIAGRAM
UDG-95037
DESCRIPTION
Pin numbers refer to 16-pin DIL and SOIC packages only.
The UC3548 family of PWM control ICs uses voltage feedforward control to regulate the output voltage of isolated
power supplies. The UC3548 resides on the primary side
and has the necessary features to accurately control secondary side short circuit current with average current
mode control techniques. The UC3548 can be used to
control a wide variety of converter topologies.
In addition to the basic functions required for pulse width
modulation, the UC3548 implements a patented technique
of sensing secondary current from the primary side in an
isolated buck derived converter. A current waveform synthesizer monitors switch current and simulates the inductor
current downslope so that the complete current waveform
can be constructed on the primary side without actual secondary side measurement. This information on the primary
side is used by an average current mode control circuit to
accurately limit maximum output current.
The UC3548 circuitry includes a precision reference, a
wide bandwidth error amplifier for average current control,
an oscillator to generate the system clock, latching PWM
comparator and logic circuits, and a high current output
4/97
driver. The current error amplifier easily interfaces with an
optoisolator from a secondary side voltage sensing circuit.
A full featured undervoltage lockout (UVLO) circuit is contained in the UC3548. UVLO monitors the supply voltage
to the controller (VCC), the reference voltage (VREF), and
the input line voltage (VIN). All three must be good before
soft start commences. If either VCC or VIN is low, the supply current required by the chip is only 500µA and the
output is actively held low.
Two on board protection features set controlled limits to
prevent transformer core saturation. Input voltage is monitored and pulse width is constrained to limit the maximum
volt-second product applied to the transformer. A unique
patented technique limits maximum duty cycle within 3%
of a user programmed value.
These two features allow for more optimal use of transformers and switches, resulting in reduced system size
and cost.
Both patents embodied in the UC3548 belong to Lambda
Electronics Incorporated and are licensed for use in applications employing these devices.
UC1548
UC2548
UC3548
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Output Current, Source or Sink (Pin 14)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ±0.2V
Analog Input Voltages
(Pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . -0.3 to 7V
Analog Input Currents, Source or Sink
(Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA
Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA
Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range. . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C
Notes: All voltages are with respect to ground (DIL and SOIC
pin 1). Currents are positive into the specified terminal.
Pin numbers refer to the 16 pin DIL and SOIC packages.
Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
J, N, or DW Packages
PLCC-20 & LCC-20 (Top View)
Q & L Packages
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the junction temperature range of
−55°C to +125°C for the UC1548, −40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test conditions are: VCC =
12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.95
1
1.05
V
20
25
Real Time Current Waveform Synthesizer
Ion Amplifier
Offset Voltage
Slew Rate (Note 1)
lib
V/µs
-2
-20
µA
IOFF Current Mirror
Input Voltage
0.95
1
1.05
V
Current Gain
0.9
1
1.1
A/A
60
100
Current Error Amplifier
AVOL
Vio
12V ≤ VCC ≤ 20V, 0V ≤ VCM ≤ 5V
10
mV
-0.5
-3
µA
3.3
3.5
V
0.3
0.6
V
1.4
1.6
2.0
5
8
MHz
8
10
V/µs
240
250
lib
Voh
IO = −200µA
Vol
IO = 200µA
Source Current
VO = 1V
GBW Product
f = 200kHz
3.1
Slew Rate (Note 1)
dB
mA
Oscillator
Frequency
TA = 25°C
235
2
260
kHz
265
kHz
UC1548
UC2548
UC3548
ELECTRICAL CHARACTERISTICS (cont.): Unless otherwise stated, all specifications are over the junction
temperature range of −55°C to +125°C for the UC1548, −40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test
conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
73.5
76.5
79.5
%
13
14
V
Duty Cycle Clamp
Max Duty Cycle
V(DMAX) = 0.75 • VREF
VCC Comparator
Turn-on Threshold
Turn-off Threshold
9
10
2.5
3
3.5
V
4.1
4.35
4.6
V
Vuv = 4.2V
77
90
103
kΩ
TA = 25°C
4.95
5
0 < IO < 10mA, 12 < VCC < 20
4.93
Hysteresis
V
UV Comparator
Turn-on Threshold
RHYSTERESIS
Reference
VREF
5.05
V
5.07
V
Line Regulation
12V < VCC < 20V
4
15
mV
Load Regulation
0 < IO < 10mA
3
15
mV
Short Circuit Current
VREF = 0V
50
70
mA
20
45
ns
30
Output Stage
Rise & Fall Time (Note 1)
Cl = 1nF
IO = 20mA
0.25
0.4
V
IO = 200mA
1.2
2.2
V
Output High Saturation
IO = -200mA
2.0
3.0
V
UVLO Output Low Saturation
IO = 20mA
0.8
1.2
V
ISTART
VCC = 12V
0.2
0.4
mA
ICC (pre-start)
VCC = 15V, V(UV) = 0
0.5
1
mA
22
26
mA
Output Low Saturation
ICC
ICC (run)
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
CAO: Output of the current error amplifier. Also the
resistor load for the collector of an optocoupler.
ION: Input pin to inductor current waveform synthesizer.
Apply a voltage proportional to switch current to this pin.
CDC: Connect a charge balance integration capacitor
from CDC to GND to achieve an accurate duty cycle
clamp. This capacitor also sets the soft start time.
NI: Noninverting input of the current error amplifier.
OUT: Output driver for the gate of a power FET.
PGND: Power ground pin for the output driver. This
ground circuit should be connected to GND at a single
point.
CI: Output of the inductor current waveform synthesizer.
Requires a capacitor to ground.
CT: A capacitor from CT to GND sets the oscillator
frequency.
UV: Line voltage sense pin to insure the chip only
operates with sufficient line voltage. Program with a
resistive divider from the converter input voltage to UV
to GND.
DMAX: Programs maximum duty cycle with a resistive
divider from VREF to DMAX to GND.
GND: Signal ground.
VCC: Chip supply voltage. Bypass with a 1µF ceramic
capacitor to PGND.
INV: Inverting input of the current error amplifier.
VREF: Precision voltage reference. Bypass with a 1µF
ceramic capacitor to GND.
IOFF: Programs the discharge slope of the capacitor on
CI to emulate the down slope of the inductor current
waveform.
VS: Volt second clamp programming pin and feedforward
ramp waveform for the pulse width modulator. Connect a
resistor to the input line voltage and a capacitor to GND.
3
UC1548
UC2548
UC3548
UNDERVOLTAGE LOCKOUT
The undervoltage lockout block diagram is shown in Figure 1. The VCC comparator monitors chip supply voltage.
Hysteretic thresholds are set at 13V and 10V to facilitate
off-line applications. If the VCC comparator is low, ICC is
low (
