UC1610
UC3610
SLUS339B − JUNE 1993 − REVISED DECEMBER 2004
DUAL SCHOTTKY DIODE BRIDGE
FEATURES
D Monolithic Eight-Diode Array
D Exceptional Efficiency
D Low Forward Voltage
D Fast Recovery Time
D High Peak Current
D Small Size
DESCRIPTION
This eight-diode array is designed for
high-current, low duty-cycle applications typical of
flyback voltage clamping for inductive loads. The
dual bridge connection makes this device
particularly applicable to bipolar driven stepper
motors.
The use of Schottky diode technology features
high efficiency through lowered forward voltage
drop and decreased reverse recovery time.
This single monolithic chip is fabricated in both
hermetic CERDIP and copper-leaded plastic
packages. The UC1610 in ceramic is designed for
−55°C to 125°C environments but with reduced
peak current capability. The UC2610 in plastic and
ceramic is designed for −25°C to 125°C
environments also with reduced peak current
capability; while the UC3610 in plastic has higher
current rating over a 0°C to 70°C temperature
range.
AVAILABLE OPTIONS
Packaged Devices
TA = TJ
SOIC Wide (DW)
DIL (J)
DIL (N)
−55°C to 125°C
UC1610DW
UC1610J
UC1610N
−25°C to 125°C
UC2610DW
UC2610J
UC2610N
0°C to 70°C
UC3610DW
UC3610J
UC3610N
THERMAL INFORMATION
PACKAGE
SOIC (DW) 16 pin
θja
50 −
100(1)
θjc
27
DIP (J) 8 pin
125 − 160
20(2)
DIP (N) 8 pin
103(1)
50
NOTES: 1. Specified θja (junction-to-ambient) is for devices mounted to 5-in2 FR4 PC board with one ounce copper where noted. When
resistance range is given, lower values are for 5-in2 aluminum PC board. Test PWB was 0.062 in thick and typically used 0.635-mm
trace widths for power packages and 1.3-mm trace widths for non-power packages with a 100-mil x 100-mil probe land area at the
end of each trace.
2. θjc data values stated were derived from MIL−STD−1835B. MIL−STD−1835B states that the baseline values shown are worst case
(mean + 2s) for a 60-mil x 60-mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils.
For device die sizes greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid array,
10°C/W.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
1
UC1610
UC3610
SLUS339B − JUNE 1993 − REVISED DECEMBER 2004
N OR J PACKAGE
TOP VIEW
DW PACKAGE
TOP VIEW
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Peak inverse voltage (per diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Peak forward current
UC1611 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
UC2610 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
UC3611 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Power dissipation at TA = 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Consult packaging section of databook for thermal limitations and considerations of package.
electrical characteristics, all specifications apply to each individual diode, TJ = 25°C, TA = TJ,
(except as noted)
PARAMETER
Forward voltage drop
Leakage current
TEST CONDITIONS
IF = 100 mA
IF = 1 A
VR = 40 V
VR = 40 V,
TJ = 100°C
MIN
TYP
MAX
UNITS
0.35
0.5
0.7
0.8
1.0
1.3
V
V
0.01
0.1
mA
0.1
1.0
mA
Reverse recovery
0.5 A forward to 0.5 A reverse
15
Forward recovery
1 A forward to 1.1 V recovery
30
ns
Junction capacitance
VR = 5 V
70
pF
NOTE: At forward currents of greater than 1.0 A, a parasitic current of approximately 10 mA may be collected by adjacent diodes.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
www.ti.com
ns
UC1610
UC3610
SLUS339B − JUNE 1993 − REVISED DECEMBER 2004
APPLICATION INFORMATION
FORWARD CURRENT
vs
VOLTAGE
1000
5.0
500
3.0
2.0
300
200
1.0
T J = 125 °C
100
Forward Current − A
50
30
20
10
5
0.3
0.2
0.05
0.03
0.02
T J = 25 °C
0.005
3
2
T J = 125 °C
0.003
0.002
0.001
1
0
10
20
30
40
0
50
0.2 0.4
0.6 0.8
1.0
1.2
1.4 1.6
1.8 2.0
Forward Voltage − V
Reverse Voltage − V
Figure 1
Figure 2
REVERSE RECOVERY CHARACTERISTICS
FORWARD RECOVERY CHARACTERISTICS
I F = 0.5 A
TA= 25 °C
1.1 V
Diode Voltage 1.0 V/DIV
Diode Current 200 mA DIV
T J = −55 °C
0.1
0.01
T J = 25 °C
T J = 75 °C
0.5
0A
IR= 0.5 A
TA= 25 °C
Diode Voltage
TFR
(6 ns)
0A
IF = 1 A
Diode Current 500 mA DIV
Leakage Current − μA
REVERSE CURRENT
vs
VOLTAGE
Diode Current
TRR
(4.6 ns)
0A
Time, 2 ns/DIV
Time, 2 ns/DIV
Figure 4
Figure 3
www.ti.com
3
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
UC2610N
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
-40 to 85
UC2610N.A
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
-40 to 85
UC2610N
UC2610N
UC3610DW
Active
Production
SOIC (DW) | 16
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3610DW
UC3610DW.A
Active
Production
SOIC (DW) | 16
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3610DW
UC3610DWTR
Active
Production
SOIC (DW) | 16
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3610DW
UC3610DWTR.A
Active
Production
SOIC (DW) | 16
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3610DW
UC3610N
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
0 to 70
UC3610N
UC3610N.A
Active
Production
PDIP (P) | 8
50 | TUBE
Yes
NIPDAU
N/A for Pkg Type
0 to 70
UC3610N
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
UC3610DWTR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UC3610DWTR
SOIC
DW
16
2000
353.0
353.0
32.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
UC2610N
P
PDIP
8
50
506
13.97
11230
4.32
UC2610N.A
P
PDIP
8
50
506
13.97
11230
4.32
UC3610DW
DW
SOIC
16
40
507
12.83
5080
6.6
UC3610DW.A
DW
SOIC
16
40
507
12.83
5080
6.6
UC3610N
P
PDIP
8
50
506
13.97
11230
4.32
UC3610N.A
P
PDIP
8
50
506
13.97
11230
4.32
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated
