UC37136MG4

        , SLUS447 - FEBRUARY 2000 - REVISED JULY 2000
250-mA Continuous Total Output Drive
Two Output Power Switches, 35-V DP, M, OR NP PACKAGES (TOP VIEW) Maximum Operation
Low-Side or High-Side Switch





Configuration User Programmable Phasing of Output Switch LS2/HS2 Internal Output Voltage Clamp for Driving Inductive Loads 9 V to 35 V Supply Voltage Range Current Limit Protection Thermal Shutdown Protection UVLO With User Programmable Time Delay VCC SD CDEL GND GND INV2 IN2 IN1 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 LS2 N/C HS2 GND GND HS1 N/C LS1 description The UCx7136 bipolar dual switch contains all the control and drive circuitry required to drive resistive, capacitive, and inductive loads as in industrial sensor applications. The output drivers are 250-mA NPN power switches that can switch a load between a voltage supply up to 35 V and GND with a continuous output current rating of 250 mA, combined or individually. Internal 46-V Zener clamps are provided to clamp collector-to-emitter NPN power switch voltages to safe levels when driving inductive loads. The two outputs can be configured in any combination of high side (load to GND) or low side (load to VCC). The output of switch 1 is fixed in phase with the CMOS compatible IN1 pin. The CMOS compatible exclusive OR gate inputs, IN2 and INV2, determine the output phase of switch 2. An under voltage lockout (UVLO) function is provided to disable both output NPN power switches until VCC is greater than 8 V. Both output NPN power switches can also be disabled past the UVLO enable trip point by an external user programmable time delay capacitor. An internal current limit function enables a low on/off duty cycle of the NPN power switches should the dc current go beyond 1 A. An internal thermal shutdown function disables the switches if the IC temperature reaches 155°C such as in an overcurrent condition. schematic VCC 1 REFERENCE REF REF 2.5 µA CDEL 8V UVLO 15 N/C 10 N/C 16 LS2 3 5 kΩ 4V S R Q CURRENT LIMIT SWITCH 2 0.7 Ω 14 HS2 9 LS1 11 HS1 155°C/135°C SD 2 INV2 6 IN2 7 IN1 8 SWITCH 1 0.7 Ω 4 5 12 UDG-99016 13 GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated    "#%!'#" #"%"& $%#('& " ' #%!') #% &" $& # ) #$!"' %'%&' ' " #'% &$'#"& % &" # & +& "&'%(!"'& %&%)& ' %' '# " #% &#"'"( '& $%#('& *'#(' "#' POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1          SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V LS1, HS1, LS2, HS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V LS1-HS1, LS2-HS2 (clamped by internal circuitry) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA (Total) Output Current, Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 A Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Storage Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Junction Temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Lead Temperature (Soldering, 10 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Data Book for thermal limitations and considerations of packages. AVAILABLE OPTIONS PACKAGE DEVICES TA SOIC Narrow Lead Frame (DP) Plastic Batwing DIP (NP) QSOP Lead Frame (M) –40°C to +85°C UC27136DP UC27136NP N/A 0°C to +70°C UC37136DP UC37136NP UC37136M electrical characteristics VCC = 25 V, IN1 = IN2 = INV2 = 0 V (for low), IN1 = IN2 = INV2 = 5 V (for high), TA = TJ, CDEL = 10 nF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Overall Section VCC supply voltage VCC supply current 9 VCC current with IN1, IN2, INV2 = 0 V 35 7.0 V mA Under Voltage Lockout (UVLO) Section UVLO threshold 7.5 8 8.5 V UVLO hysteresis 0.4 0.5 0.6 V Input Logic Section Digital input high level IN1, IN2, INV2 Digital input low level IN1, IN2, INV2 3.5 V Input bias current, low level IN1, IN2, INV2 = 0 V –10 Input bias current high level IN1, IN2, INV2 = 5 V 5 1.5 Logic input to output delay V µA µA 3 µs Output: High Side Configuration Section Rise time (off to on) RLOAD = 250 Ω, Fall time (on to off) RLOAD = 250 Ω, See Figure 1 RLOAD = 100 Ω, TA = 25°C, TA = –40°C, Saturation voltage Current limit RLOAD = 100 Ω, See Figure 1 RLOAD = 0.25 Ω, Leakage current TA = 25°C, HS1, HS2 = GND, LS1, LS2 = VCC, Voltage clamp Measure (VLS1 – VHS1) or (VLS2 – VHS2) 2 POST OFFICE BOX 655303 100 ns 200 ns See Figure 1 1.15 V See Figure 1 1.3 V 5 µA See Figure 1 1.1 IN1, IN2, INV2 = 0 V • DALLAS, TEXAS 75265 46 A V          SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 electrical characteristics VCC = 25 V, IN1 = IN2 = INV2 = 0 V (for low), IN1 = IN2 = INV2 = 5 V (for high), TA = TJ, CDEL = 10 nF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output: Low Side Configuration Section Rise time (on to off) RLOAD = 250 Ω, See Figure 2 300 ns Fall Time (off to on) RLOAD = 250 Ω, See Figure 2 150 ns Saturation Sa u a o voltage o age RLOAD = 100 Ω, TA = 25°C, TA = –40°C, RLOAD = 100 Ω, Current limit RLOAD = 0.25 Ω, See Figure 2 1.15 V See Figure 2 1.3 V Leakage current TA = 25°C, HS1, HS2 = GND, LS1, LS2 = VCC, See Figure 2 Voltage clamp Measure (VLS1 - VHS1) or (VLS2 - VHS2) 1.1 IN1, IN2, INV2 = 0 V A 5 µA 46 V 4.7 V 4 V ICDEL Thermal Shutdown (see Note 1) 2.5 µA Thermal shutdown threshold 155 °C 20 °C Turn On Delay CDEL maximum voltage CDEL threshold Hysteresis NOTE 1: Ensured by design. Not production tested. pin descriptions CDEL: A capacitor connected to this pin is used to program a turnon delay after the UVLO threshold has been reached. The UVLO function keeps the external capacitor connected to this pin discharged until VCC is greater than 8 V. After the UVLO upper trip point of 8 V has been exceeded, an internal 2.5-µA current source charges the capacitor from GND to 4.7 V. An internal voltage comparator enables the output NPN switches at 4 V, imparting a time delay after UVLO. As an added feature, an external switch can be connected in parallel with the user-programmable time-delay capacitor to disable the output NPN switches and reset the time delay capacitor by external means. GND: The reference point for the internal reference, all thresholds, and the ground for the remainder of the device. IN1: The digital-logic input pin that controls the state of the output NPN switch 1. When the IN1 pin is a logic low (0 V to 1.5 V), output switch 1 is off (non-conducting). When the IN1 pin is a logic high (3.5 V to 17.5 V), output switch 1 is on (conducting). IN2, INV2: The digital logic input pins to the exclusive OR gate that controls the state of the output NPN switch 2. Refer to the truth table for description. A logic low is 0 V to 1.5 V; a logic high is 3.5 V to 17.5 V. HS1: This pin is the emitter of output NPN switch 1. HS2: This pin is the emitter of output NPN switch 2. LS1: This pin is the collector of output NPN switch 1. LS2: This pin is the collector of output NPN switch 2. SD: This ground referenced open collector NPN output is asserted in the event of an overcurrent or during the start up delay due to the CDEL pin, non-conducting otherwise. The maximum SD current is 8 mA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3          SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 APPLICATION INFORMATION TRUTHTABLE INV2 Low High Low High IN2 Low Low High High Switch 2 Off On On Off turn on delay The NPN output switches remains off until the external capacitor connected to CDEL charges up to the internal threshold voltage of 4 V with a charging current of 2.5 µA. This off condition is independent of the state of the input logic pins IN1, IN2, and INV2. This capacitor charging imparts a delay time on the outputs that is equal to approximately 1.6 ms/nF. As an example, a 0.1-µF capacitor connected to CDEL results in a 160 ms turnon delay after VCC crosses the 8-V UVLO threshold. If VCC drops below the 7.5-V hysteresis threshold, the CDEL capacitor is discharged immediately and both outputs turn off. The CDEL pin can also be externally driven low to restart the turnon delay sequence. The minimum acceptable value for the CDEL capacitor, when driving a capacitive load, is determined by: CDEL  (MIN) C 
V LOAD LOAD 2445 (1) Where CLOAD is equal to the output capacitive load and VLOAD is equal to the voltage rail of the output load. The maximum switching frequency to drive a capacitive load, CLOAD, is given by: f (MAX)   9.4
CDEL
1  e    1 C  
V LOAD LOAD 5
10 3
CDEL  CLOAD
VLOAD (2) overcurrent indication The open collector output SD pin can be used to drive an LED to signal when an overload condition is present. The LED turns on, through an external pullup, when the outputs are shut down due to an overcurrent. The maximum SD current is 8 mA. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265          SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 APPLICATION INFORMATION typical applications 0.1 µ F + UC37136 1 VCC LS2 16 2 SD N/C 15 3 CDEL HS2 14 4 GND GND 13 5 GND GND 12 6 INV2 HS1 11 7 IN2 N/C 10 9V TO 35 V 750 + 5V LED 0.1 µ F DELAY CAPACITOR + 5V LOAD LOAD UDG-99017 8 9 LS1 IN1 INPUT NOTE A: VCC, OUTPUT1 and OUTPUT2 can be connected to separate power supplies within the specified Absolute Maximum Ratings. Figure 1. Both Switches Configured as High Side, Switch 2 Inverted with Respect to Switch 1 0.1 µ F + LOAD LOAD 9V TO 35 V UC37136 1 VCC LS2 16 2 SD N/C 15 3 CDEL HS2 14 4 GND GND 13 5 GND GND 12 6 INV2 HS1 11 7 IN2 N/C 10 750 + 5V LED 0.1 µ F DELAY CAPACITOR + 5V UDG-99019 8 IN1 LS1 9 INPUT NOTE A: VCC, OUTPUT1 and OUTPUT2 can be connected to separate power supplies within the specified Absolute Maximum Ratings. Figure 2. Both Switches Configured as Low Side, Switch 2 Inverted with Respect to Switch 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5          SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 APPLICATION INFORMATION typical applications (continued) 0.1 µ F LOAD UC37136 1 VCC LS2 16 2 SD N/C 15 3 CDEL HS2 14 4 GND GND 13 5 GND GND 12 6 INV2 HS1 11 7 IN2 N/C 10 8 IN1 LS1 9 + 9V TO 35 V 750 + 5V LED 0.1 µ F DELAY CAPACITOR LOAD UDG-99018 INPUT NOTE A: VCC, OUTPUT1 and OUTPUT2 can be connected to separate power supplies within the specified Absolute Maximum Ratings. Figure 3. Switch 1 High Side, Switch 2 Low Side, in Phase with Each Other 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) UC37136M ACTIVE SSOP/QSOP DBQ 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples UC37136MG4 ACTIVE SSOP/QSOP DBQ 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. 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