UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
High-Speed PWM Controller
Functional
improvements
have
also
been
implemented in this family. The UC3825 shutdown
comparator is now a high-speed overcurrent
comparator with a threshold of 1.2 V. The overcurrent
comparator sets a latch that ensures full discharge
of the soft-start capacitor before allowing a restart.
While the fault latch is set, the outputs are in the low
state. In the event of continuous faults, the soft-start
capacitor is fully charged before discharge to insure
that the fault frequency does not exceed the designed
soft start period. The UC3825 CLOCK pin has
become CLK/LEB. This pin combines the functions
of clock output and leading edge blanking adjustment
and has been buffered for easier interfacing.
1 Features
•
•
•
•
•
•
•
•
•
Improved versions of the UC3823/UC3825 PWMs
Compatible with voltage-mode or current-mode
control methods
Practical operation at switching frequencies to 1
MHz
50-ns propagation delay to output
High-current dual totem pole outputs (2-A peak)
Trimmed oscillator discharge current
Low 100-μA startup current
Pulse-by-pulse current limiting comparator
Latched overcurrent comparator with full cycle
restart
2 Description
The UC3825A and UC3825B have dual alternating
outputs and the same pin configuration of the
UC3825. The UC3823A and UC3823B outputs
operate in phase with duty cycles from zero to less
than 100%. The pin configuration of the UC3823A
and UC3823B is the same as the UC3823 except pin
11 is now an output pin instead of the reference pin
to the current limit comparator. A version parts have
UVLO thresholds identical to the original UC3823 and
UC3825. The B versions have UVLO thresholds of
16 V and 10 V, intended for ease of use in off-line
applications.
The UC3823A and UC3823B and the UC3825A and
UC3825B family of PWM controllers are improved
versions of the standard UC3823 and UC3825 family.
Performance enhancements have been made to
several of the circuit blocks. Error amplifier gain
bandwidth product is 12 MHz, while input offset
voltage is 2 mV. Current limit threshold is assured
to a tolerance of 5%. Oscillator discharge current is
specified at 10 mA for accurate dead time control.
Frequency accuracy is improved to 6%. Startup
supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to
actively sink current during UVLO at no expense
to the startup current specification. In addition each
output is capable of 2-A peak currents during
transitions.
CLK/LEB 4
Consult the application note, The UC3823A,B
and UC3825A,B Enhanced Generation of PWM
Controllers (SLUA125) for detailed technical and
applications information.
13 VC
(60%)
RT 5
11 OUTA
*
OSC
CT 6
R
RAMP 7
EAOUT 3
NI
T
SD
PWM
LATCH
1.25 V
PWM COMPARATOR
14 OUTB
12 PGND
2
E/A
9 mA
INV 1
SOFT-START COMPLETE
SS 8
CURRENT
LIMIT
1.0 V
OVER CURRENT
ILIM 9
1.2 V
0.2 V
VCC 15
”B” 16V/10V
”A” 9.2V/8.4V
GND 10
RESTART
DELAY
LATCH
5V
RESTART
DELAY
SD
S
R
R
250 mA
FAULT LATCH
UVLO
VREF
5.1 V
ON/OFF
4V
INTERNAL
BIAS
VREF GOOD
16 5.1 VREF
UDG-02091
* On the UC1823A version, toggles Q and Q are always low.
Figure 2-1. Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
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SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Ordering Information.......................................................3
5 Pin Configuration and Functions...................................3
Terminal Functions............................................................4
6 Specifications.................................................................. 5
6.1 ABSOLUTE MAXIMUM RATINGS..............................5
6.2 Thermal Information....................................................5
6.3 ELECTRICAL CHARACTERISTICS...........................6
6.4 ELECTRICAL CHARACTERISTICS...........................7
7 Application and Implementation.................................... 8
7.1 LEADING EDGE BLANKING......................................8
7.2 UVLO, SOFT-START AND FAULT
MANAGEMENT.............................................................9
7.3 ACTIVE LOW OUTPUTS DURING UVLO................10
7.4 CONTROL METHODS............................................. 10
7.5 SYNCHRONIZATION............................................... 10
7.6 HIGH CURRENT OUTPUTS.................................... 11
7.7 GROUND PLANES...................................................12
7.8 OPEN LOOP TEST CIRCUIT................................... 13
8 Device and Documentation Support............................14
8.1 Documentation Support............................................ 14
8.2 Receiving Notification of Documentation Updates....14
8.3 Support Resources................................................... 14
8.4 Trademarks............................................................... 14
8.5 Electrostatic Discharge Caution................................14
8.6 Glossary....................................................................14
9 Mechanical, Packaging, and Orderable Information.. 15
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2010) to Revision F (August 2022)
Page
• Added SOIC package......................................................................................................................................... 3
• Added Thermal Information................................................................................................................................ 5
2
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SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
4 Ordering Information
UVLO
TA
40°C to 85°C
0°C to 70°C
(1)
MAXIMUM
DUTY CYCLE
9.2 V / 8.4 V
SOIC-16
(DW)
(1)
16 V / 10 V
PDIP-16
(N)
PLCC-20(1)
(Q)
SOIC-16
(DW)
PDIP-16
(N)
< 100%
UC2823ADW
UC2823AN
UC2823AQ
UC2823BDW
UC2823BN
< 50%
UC2825ADW
UC2825AN
UC2825AQ
UC2825BDW
UC2825BN
< 100%
UC3823ADW
UC3823AN
UC3823AQ
UC3823BDW
UC3823BN
< 50%
UC3825ADW
UC3825AN
UC3825AQ
UC3825BDW
UC3825BN
PLCC-20 (1)
(Q)
UC3825BQ
The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order
quantities of 1000 devices per reel for the Q package and 2000 devices per reel for the DW package.
5 Pin Configuration and Functions
TA
55°C to 125°C
UVLO (9.2 V/8.4 V)
MAXIMUM
DUTY CYCLE
CDIP-16 (J)
LCCC-20 (L)
< 100%
UC1823AJ, UC1823AJ883B, UC1823AJQMLV
UC1823AL, UC1823AL883B
< 50%
UC1825AJ, UC1825AJ883B, UC1825AJQMLV
UC1825AL, UC1825AL883B, UC1825ALQMLV
Q OR L PACKAGES
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
EAOUT
CLK/LEB
NC
RT
CT
4
3 2 1 20 19
18
5
6
17
16
7
8
15
14
9 10 11 12 13
OUTB
VC
NC
PGND
OUTA
RAMP
SS
NC
ILIM
GND
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
NI
INV
NC
VREF
VCC
DW, J, OR N PACKAGES
(TOP VIEW)
NC = no connection
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SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
Terminal Functions
TERMINAL
NO.
NAME
4
I/O
DESCRIPTION
J, N, or
DW
Q or L
CLK/LEB
4
5
O
Output of the internal oscillator
CT
6
8
I
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor
should be connected to the device ground using minimal trace length.
O
Output of the error amplifier for compensation
EAOUT
3
4
GND
10
13
ILIM
9
12
I
Input to the current limit comparator
INV
1
2
I
Inverting input to the error amplifier
Analog ground return pin
NI
2
3
I
Non-inverting input to the error amplifier
OUTA
11
14
O
High current totem pole output A of the on-chip drive stage.
OUTB
14
18
O
High current totem pole output B of the on-chip drive stage.
PGND
12
15
RAMP
7
9
I
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RT
5
7
I
Timing resistor connection pin for oscillator frequency programming
SS
8
10
I
Soft-start input pin which also doubles as the maximum duty cycle clamp.
VC
13
17
Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic
ceramic low ESL capacitor with minimal trace lengths.
VCC
15
19
Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor with minimal trace lengths
VREF
16
20
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Ground return pin for the output driver stage
O
5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic
ceramic low ESL capacitor and minimal trace length to the ground plane.
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SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
6 Specifications
6.1 ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
VALUE
UNIT
VIN
Supply voltage,
VC, VCC
22
V
IO
Source or sink current,DC
OUTA, OUTB
0.5
A
IO
Source or sink current, pulse (0.5 μs)
OUTA, OUTB
2.2
A
INV, NI, RAMP
–0.3 to 7
V
ILIM, SS
–0.3 to 6
V
Analog inputs
ICLK
Power ground
PGND
Clock output current
CLK/LEB
±0.2
V
–5
mA
IO(EA) Error amplifier output current
EAOUT
5
mA
ISS
Soft-start sink current
SS
20
mA
IOSC
Oscillator charging current
RT
–5
mA
TJ
Operating virtual junction temperature range
–55 to 150
°C
Tstg
Storage temperature
–65 to 150
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
–55 to 150
°C
Storage temperature
–65 to 150
°C
300
°C
tSTG
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Thermal Information
PACKAGE
(1)
(2)
θJA
θJC
J-16
80-120
28(2)
N-16
90(1)
45
DW-16
45-90(1)
25
PLCC-20 (Q package)
43-75(1)
34
LCC-20 (L package)
70-80
20(2)
Specified θJA (junction to ambient) is for devices mounted to 5 in2 FR4 PC board with one ounce copper where noted. When
resistance range is given, lower values are for 5 in2 aluminum PC board. Test PWB was 0.062" thick and typically used 0.635 mm
trace widths for power packages and 1.3 mm trace widths for non-power packages with 100 x 100 mil probe land area at the end of
each trace.
θJC data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, "The baseline values shown are worst case (mean
+ 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device die
size greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid array, 10°C/W".
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SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
6.3 ELECTRICAL CHARACTERISTICS
TA = –55°C to 125°C for the UC1823A/UC1825A, TA = –40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the
UC3823x/UC3825x, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.05
V
REFERENCE, VREF
VO
Ouput voltage range
TJ = 25°C, IO = 1 mA
5.1
5.15
Line regulation
12 V ≤ VCC ≤ 20 V
2
15
Load regulation
1 mA ≤ IO ≤ 10 mA
5
20
Total output variation
Long term stability
5.03
5.17
T(min) < TA < T(max)
0.2
(1)
10 Hz < f < 10 kHz
50
Temperature stability
Output noise voltage
Line, load, temperature
(1)
(1)
TJ = 125°C, 1000 hours
Short circuit current
0.4
mV
V
mV/°C
μVRMS
5
25
mV
30
60
90
mA
375
400
425
kHz
RT = 6.6 kΩ, CT = 220 pF, TA = 25°C
0.9
1
1.1
MHz
Line, temperature
350
450
kHz
RT = 6.6 kΩ, CT = 220 pF
0.85
1.15
MHz
VREF = 0 V
OSCILLATOR
fOSC
Initial accuracy
Total variation
TJ = 25°C
(1)
(1)
Voltage stability
Temperature stability
12 V < VCC < 20 V
(1)
1%
T(min) < TA < T(max)
High-level output voltage, clock
±5%
3.7
4
0
0.2
Ramp peak
2.6
2.8
3
Ramp valley
0.7
1
1.25
Ramp valley-to-peak
1.6
1.8
2
9
10
11
mA
mV
Low-level output voltage, clock
IOSC
Oscillator discharge current
RT = OPEN, VCT = 2 V
V
ERROR AMPLIFIER
Input offset voltage
2
10
Input bias current
0.6
3
Input offset current
0.1
1
Open loop gain
1 V < VO < 4 V
60
95
CMRR
Common mode rejection ratio
1.5 V < VCM < 5.5 V
75
95
PSRR
Power supply rejection ratio
12 V < VCC < 20 V
85
110
IO(sink)
Output sink current
VEAOUT = 1 V
1
2.5
IO(src)
Output source current
VEAOUT = 4 V
High-level output voltage
IEAOUT = –0.5 mA
Low-level output voltage
Gain bandwidth product
Slew rate
(1)
6
(1)
μA
dB
mA
–1.3
–0.5
4.5
4.7
5
IEAOUT = –1 mA
0
0.5
1
f = 200 kHz
6
12
Mhz
6
9
V/μs
V
Ensured by design. Not production tested.
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SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
6.4 ELECTRICAL CHARACTERISTICS
TA = –55°C to 125°C for the UC1823A/UC1825A, TA = –40°C to 85°C for the UC2823x/UC2825x, TA = 0°C to 70°C for the
UC3823x/UC3825x, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIIONS
MIN
TYP MAX
UNIT
PWM COMPARATOR
IBIAS
Bias current, RAMP
VRAMP = 0 V
–1
Minimum duty cycle
Maximum duty cycle
Leading edge blanking time
RLEB = 2 kΩ, CLEB = 470 pF
RLEB
Leading edge blanking resistance
VCLK/LEB = 3 V
VZDC
Zero dc threshold voltage, EAOUT
VRAMP = 0 V
tDELAY Delay-to-output
μA
85%
tLEB
time(1)
–8
0%
300
375
450
ns
8.5
10.0
11.5
kΩ
1.10
1.25
1.4
V
50
80
ns
20
μA
VEAOUT = 2.1 V, VILIM = 0 V to 2 V step
CURRENT LIMIT / START SEQUENCE / FAULT
ISS
Soft-start charge current
VSS
Full soft-start threshold voltage
IDSCH
Restart discharge current
ISS
Restart threshold voltage
IBIAS
ILIM bias current
ICL
Current limit threshold voltage
Overcurrent threshold voltage
td
Delay-to-output time, ILIM(1)
VSS= 2.5 V
8
14
4.3
5
100
250
350
μA
0.3
0.5
V
15
µA
0.95
1
1.05
1.14
1.2
1.26
50
80
IOUT = 20 mA
0.25
0.4
IOUT = 200 mA
1.2
2.2
IOUT = -20 mA
1.9
2.9
VSS= 2.5 V
VILIM = 0 V to 2 V step
VILIM = 0 V to 2 V step
V
V
ns
OUTPUT
Low-level output saturation voltage
High-level output saturation voltage
tr, tf
Rise/fall time(1)
IOUT = -200 mA
V
2
3
CL = 1 nF
20
45
UC2823B, UC2825B, UC3825B, UC3825B
16
17
8.4
9.2
9.6
9
10
0.4
0.8
1.2
5
6
7
100
300
μA
28
36
mA
ns
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage
UC1823A, UC1825A, UC2823A, UC2825A UC3825A,
UC3825A
Stop threshold voltage
UC2823B, UC2825B, UC3825B, UC3825B
OVLO hysteresis
UC1823A, UC1825A, UC2823A, UC2825A UC3825A,
UC3825A
UC2823B, UC2825B, UC3825B, UC3825B
V
SUPPLY CURRENT
Isu
Startup current
ICC
Input current
(1)
VC = VCC = VTH(start) –0.5 V
Ensured by design. Not production tested.
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7 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
7.1 LEADING EDGE BLANKING
The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The
UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some
value less than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle,
one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to
less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is
controlled by the PWM comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates
the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time
after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The
PWM ramp input may not require any filtering as result of leading edge blanking.
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set
by C and the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance.
For more accuracy, an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66
kΩ with a tolerance of 2.4%. The design equation is:
t LEB + 0.5
ǒR ø 10 kWǓ
C
(1)
Values of R less than 2 kΩ should not be used.
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V
threshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic
overcurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the
outputs driven low. For this reason, some noise filtering may be required on the ILIM pin.
8
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UDG-95105
Figure 7-1. Leading Edge Blanking Operational Waveforms
7.2 UVLO, SOFT-START AND FAULT MANAGEMENT
Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error
amplifier output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output
follows until closed loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then
discharged by a 250-μA current sink. No more output pulses are allowed until soft-start is fully discharged and
ILIM is below 1.2 V. At this point the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor
does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous
fault conditions.
UDG-95106
Figure 7-2. Soft-Start and Fault Waveforms
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7.3 ACTIVE LOW OUTPUTS DURING UVLO
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to
operate.
UDG-95108
Figure 7-3. Output Voltage vs Output Current
UDG-95106
Figure 7-4. Output V and I During UVLO
7.4 CONTROL METHODS
Current Mode
Voltage Mode
UDG-95110
UDG-95109
.
Figure 7-5. Control Methods
7.5 SYNCHRONIZATION
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the
free running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The
pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge
of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no
longer accepts an incoming synchronizing signal.
10
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Product Folder Links: UC1823A UC2823A UC2823B UC3823A UC3823B UC1825A UC2825A UC2825B
UC3825A UC3825B
UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
www.ti.com
SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
UDG-95113
Figure 7-6. General Oscillator Synchronization
Figure 7-7. Two Unit Interface
UDG-95112
Figure 7-8. Operational Waveforms
7.6 HIGH CURRENT OUTPUTS
Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak
current into a capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns.
Separate collector supply (VC) and power ground (PGND) pins help decouple the device's analog circuitry from
the high-power gate drive noise. The use of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in
the Figure 7-10 from each output to both VC and PGND are recommended. The diodes clamp the output swing
to the supply rails, necessary with any type of inductive/capacitive load, typical of a MOSFET gate. Schottky
diodes must be used because a low forward voltage drop is required. DO NOT USE standard silicon diodes.
Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B
devices. These can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each
output for a combined peak current of 4 A.
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UC3825A UC3825B
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UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
www.ti.com
SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
UDG-95114
Figure 7-9. Power MOSFET Drive Circuit
7.7 GROUND PLANES
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct
operation of the chip. A ground plane must be employed. A unique section of the ground plane must be
designated for high di/dt currents associated with the output stages. This point is the power ground to which the
PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a
single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC
should be bypassed directly to power ground with a good high frequency capacitor. The sources of the power
MOSFET should connect to power ground as should the return connection for input power to the system and the
bulk input capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND.
Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency
capacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog
circuitry should likewise be bypassed to the signal ground plane.
UDG-95115
Figure 7-10. Ground Planes Diagram
12
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Product Folder Links: UC1823A UC2823A UC2823B UC3823A UC3823B UC1825A UC2825A UC2825B
UC3825A UC3825B
UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
www.ti.com
SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
7.8 OPEN LOOP TEST CIRCUIT
This test fixture is useful for exercising many functions of this device family and measuring their specifications.
As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground
plane is highly recommended.
UDG-95116
Figure 7-11. Open Loop Test Circuit Schematic
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UC3825A UC3825B
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UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
www.ti.com
SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
8 Device and Documentation Support
8.1 Documentation Support
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
8.6 Glossary
TI Glossary
14
This glossary lists and explains terms, acronyms, and definitions.
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UC3825A UC3825B
UC1823A, UC2823A, UC2823B, UC3823A, UC3823B
UC1825A, UC2825A, UC2825B, UC3825A, UC3825B
www.ti.com
SLUS334F – AUGUST 1995 – REVISED AUGUST 2022
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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UC3825A UC3825B
15
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-87681022A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596287681022A
UC1825AL/
883B
5962-8768102EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8768102EA
UC1825AJ/883B
5962-89905022A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596289905022A
UC1823AL/
883B
5962-8990502EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8990502EA
UC1823AJ/883B
5962-8990502VEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8990502VE
A
UC1823AJQMLV
UC1823AJ
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1823AJ
Samples
UC1823AJ883B
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8990502EA
UC1823AJ/883B
Samples
UC1823AL
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1823AL
Samples
UC1823AL883B
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596289905022A
UC1823AL/
883B
UC1825AJ
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1825AJ
Samples
UC1825AJ883B
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8768102EA
UC1825AJ/883B
Samples
UC1825AL
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
UC1825AL
Samples
UC1825AL883B
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596287681022A
UC1825AL/
883B
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
UC2823ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2823ADW
Samples
UC2823ADWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2823ADW
Samples
UC2823AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
UC2823AN
Samples
UC2823BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2823BDW
Samples
UC2825ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2825ADW
Samples
UC2825ADWG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2825ADW
Samples
UC2825ADWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2825ADW
Samples
UC2825ADWTRG4
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2825ADW
Samples
UC2825AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
UC2825AN
Samples
UC2825ANG4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
UC2825AN
Samples
UC2825BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2825BDW
Samples
UC2825BDWG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2825BDW
Samples
UC2825BN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
UC2825BN
Samples
UC3823ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3823ADW
Samples
UC3823ADWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3823ADW
Samples
UC3823AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3823AN
Samples
UC3823BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3823BDW
Samples
UC3823BDWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3823BDW
Samples
UC3825ADW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3825ADW
Samples
UC3825ADWG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3825ADW
Samples
UC3825ADWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3825ADW
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
UC3825ADWTRG4
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3825ADW
Samples
UC3825AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3825AN
Samples
UC3825ANG4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3825AN
Samples
UC3825BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3825BDW
Samples
UC3825BDWTR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3825BDW
Samples
UC3825BN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
UC3825BN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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