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UCC21222-Q1
SLUSDA5 – FEBRUARY 2018
UCC21222-Q1 Automotive 4-A, 6-A, 3.0-kVRMS Isolated Dual-Channel Gate Driver
with Dead Time
1 Features
3 Description
•
The UCC21222-Q1 device is an isolated dual channel
gate driver with programmable dead time and wide
temperature range. This device exhibits consistent
performance and robustness under extreme
temperature conditions. It is designed with 4-A peaksource and 6-A peak-sink current to drive power
MOSFET, IGBT, and GaN transistors.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC Q100 Qualified with:
– Device Temperature Grade 1
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
Junction Temperature Range –40°C to 150°C
Resistor-Programmable Dead Time
Universal: Dual Low-Side, Dual High-Side or HalfBridge Driver
4-A Peak Source, 6-A Peak Sink Output
3-V to 5.5-V Input VCCI Range
Up to 18-V VDD Output Drive Supply
– 8-V VDD UVLO
Switching Parameters:
– 28-ns Typical Propagation Delay
– 10-ns Minimum Pulse Width
– 5-ns Maximum Delay Matching
– 5.5-ns Maximum Pulse-Width Distortion
TTL and CMOS Compatible Inputs
Integrated Deglitch Filter
I/Os withstand –2-V for 200 ns
Common-Mode Transient Immunity (CMTI)
Greater than 100-V/ns
Isolation Barrier Life >40 Years
Surge Immunity up to 7800-VPK
Narrow Body SOIC-16 (D) Package
Safety-Related Certifications (Planned):
– 4242-VPK Isolation per DIN V VDE V 088411:2017-01 and DIN EN 61010-1
– 3000-VRMS Isolation for 1 Minute per UL 1577
– CSA Certification per IEC 60950-1, IEC 623681 and IEC 61010-1 End Equipment Standards
– CQC Certification per GB4943.1-2011
2 Applications
•
•
•
HEV and EV Battery Chargers
Isolated converters in AC-to-DC and DC-to-DC
Power Supplies
Motor Drives and Inverters
The UCC21222-Q1 device can be configured as two
low-side drivers, two high-side drivers, or a halfbridge driver. 5ns delay matching performance allows
two outputs to be paralleled, doubling the drive
strength for heavy load conditions without risk of
internal shoot-through.
The input side is isolated from the two output drivers
by a 3.0-kVRMS isolation barrier, with a minimum of
100-V/ns common-mode transient immunity (CMTI).
Resistor programmable dead time gives the capability
to adjust dead time for system constraints to improve
efficiency and prevent output overlap. Other
protection features include: Disable feature to shut
down both outputs simultaneously when DIS is set
high, integrated deglitch filter that rejects input
transients shorter than 5-ns, and negative voltage
handling for up to -2-V spikes for 200-ns on input and
output pins. All supplies have UVLO protection.
Device Information(1)
PART NUMBER
UCC21222-Q1
PACKAGE
SOIC (16)
BODY SIZE (NOM)
9.9 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VCCI 3,8
16 VDDA
Driver
INA
1
DIS
5
DT
6
NC
7
MOD
DEMOD
Isolation Barrier
1
Input
Logic,
Disable,
UVLO,
Dead
Time
UVLO
15 OUTA
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
Driver
INB
2
GND
4
MOD
DEMOD
UVLO
10 OUTB
9
VSSB
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21222-Q1
SLUSDA5 – FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
7.6 Power-up UVLO Delay to OUTPUT........................ 17
7.7 CMTI Testing........................................................... 18
1
1
1
2
3
4
8
8.1
8.2
8.3
8.4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety-Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 9
Thermal Derating Curves ...................................... 10
Typical Characteristics .......................................... 11
9
Minimum Pulses......................................................
Propagation Delay and Pulse Width Distortion.......
Rising and Falling Time .........................................
Input and Disable Response Time..........................
Programmable Dead Time ......................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
23
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 38
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Parameter Measurement Information ................ 15
7.1
7.2
7.3
7.4
7.5
Detailed Description ............................................ 19
15
15
15
16
16
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
40
41
41
13 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2018
*
Initial release.
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5 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
Pin Functions
PIN
NAME
DIS
NO.
5
I/O
(1)
Description
I
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to DIS pin when connecting to a µC with
distance.
DT
6
I
Programmable dead time function.
Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (RDT) between DT
and GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends
bypassing this pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place
this capacitor and RDT close to the DT pin.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
NC
12
-
No internal connection.
7
13
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close
to the device as possible.
VCCI
8
P
This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located
as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located
as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P = power, I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.5
6
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.5
20
V
–0.5
VVDDA+0.5,
VVDDB+0.5
V
–2
VVDDA+0.5,
VVDDB+0.5
V
–0.5
VVCCI+0.5
V
–2
VVCCI+0.5
V
–40
150
°C
–65
150
°C
OUTA to VSSA, OUTB to VSSB
Output signal voltage
OUTA to VSSA, OUTB to VSSB, Transient for 200
ns (2)
INA, INB, DIS to GND
Input signal voltage
Junction temperature, TJ
INA, INB Transient to GND for 200ns (2)
(3)
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Values are verified by characterization and are not production tested.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCI
VCCI Input supply voltage
3
5.5
V
VDDA,
VDDB
Driver output bias supply
9.2
18
V
TJ
Junction Temperature
–40
150
°C
TA
Ambient Temperature
–40
125
°C
4
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6.4 Thermal Information
UCC21222-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
68.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
30.5
°C/W
RθJB
Junction-to-board thermal resistance
22.8
°C/W
ψJT
Junction-to-top characterization parameter
17.1
°C/W
ψJB
Junction-to-board characterization parameter
22.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Ratings
PD
Power dissipation
PDI
Power dissipation by transmitter side
PDA, PDB
Power dissipation by each driver side
VCCI = 5.5 V, VDDA/B = 12 V, INA/B = 3.3
V, 5.4 MHz 50% duty cycle square wave 1.0nF load
VALUE
UNIT
1825
mW
15
mW
905
mW
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6.6 Insulation Specifications
VALUE
UNIT
CLR
PARAMETER
External clearance (1)
Shortest pin-to-pin distance through air
TEST CONDITIONS
>4
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
>4
mm
DTI
Distance through the
insulation
Minimum internal gap (internal clearance)
>17
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
I
Overvoltage category per
IEC 60664-1
DIN V VDE V 0884-11:2017-01
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
Rated mains voltage ≤ 600 VRMS
I-II
AC voltage (bipolar)
990
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB) test;
700
VRMS
(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
DC Voltage
990
VDC
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t
= 1 s (100% production)
4242
VPK
VIOSM
Maximum surge isolation
voltage (3)
Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST =
1.3 × VIOSM = 7800 VPK (qualification)
6000
VPK
Apparent charge (4)
qpd
CIO
Barrier capacitance, input to
output (5)
RIO
Isolation resistance, input to
output
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s
109
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 3000 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 3600VRMS, t = 1 sec (100% production)
3000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
Plan to certify according to
DIN V VDE V 0884-11:201701 and DIN EN 61010-1
(VDE 0411-1):2011-07
Plan to certify according to IEC 609501, IEC 62368-1 and IEC 61010-1
UL
CQC
Plan to be recognized under
UL 1577 Component
Recognition Program
Plan to certify according to GB
4943.1-2011
6.8 Safety-Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
Safety output supply
current
θJA = 68.5ºC/W, VVDDA/B = 12 V, TJ =
150°C, TA = 25°C
See
PS
Safety supply power
θJA = 68.5ºC/W, VVCCI = 5.5 V, TJ = 150°C,
TA = 25°C
See
TS
Safety temperature (1)
IS
(1)
SIDE
MIN
TYP
MAX
DRIVER A,
DRIVER B
75
INPUT
15
DRIVER A
905
DRIVER B
905
TOTAL
1825
150
UNIT
mA
mW
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TJ = –40°C to +150°C unless
otherwise noted (1) (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA, IVDDB
VDDA and VDDB quiescent
current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI operating current
(f = 500 kHz) current per channel
2.5
mA
VDDA and VDDB operating
current
(f = 500 kHz) current per channel,
COUT = 100 pF,
VVDDA, VVDDB = 12 V
2.5
mA
IVDDA, IVDDB
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON
UVLO Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
UVLO Falling threshold
2.35
2.5
2.65
V
VVCCI_HYS
UVLO Threshold hysteresis
0.2
V
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
8
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
7.5
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
8.5
9
V
8
8.5
V
0.5
V
INA, INB AND DISABLE
VINAH, VINBH,
VDISH
Input high threshold voltage
1.6
1.8
2
V
VINAL, VINBL,
VDISL
Input low threshold voltage
0.8
1
1.25
V
VINA_HYS,
VINB_HYS,
VDIS_HYS
Input threshold hysteresis
0.8
V
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, ROHA, ROHB do not
represent drive pull-up
performance. See tRISE in
Switching Characteristics and
Output Stage for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 12 V, IOUT = –10
mA
11.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 12 V, IOUT = 10
mA
VOAPDA, VOAPDB
Driver output (VOUTA, VOUTB)
active pull down
VVDDA and VVDDB unpowered,
IOUTA, IOUTB = 200 mA
(1)
(2)
8
5.5
1.75
mV
2.1
V
Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless
otherwise noted).
Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
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Electrical Characteristics (continued)
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TJ = –40°C to +150°C unless
otherwise noted(1)(2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEAD TIME AND OVERLAP PROGRAMMING
DT pin open or pull DT pin to
VCCI
Dead time, DT
Dead time matching, |DTAB-DTBA|
Overlap determined by INA, INB
-
RDT = 10 kΩ
80
100
120
RDT = 20 kΩ
160
200
240
RDT = 50 kΩ
400
500
600
RDT = 10 kΩ
-
0
10
RDT = 20 kΩ
-
0
20
RDT = 50 kΩ
-
0
65
ns
ns
6.10 Switching Characteristics
VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +150°C unless otherwise noted (1).
TYP
MAX
tRISE
Output rise time, see Figure 28
PARAMETER
CVDD = 10 µF, COUT = 1.8 nF,
VVDDA, VVDDB = 12 V, f = 1 kHz
5
16
ns
tFALL
Output fall time, see Figure 28
CVDD = 10 µF, COUT = 1.8 nF ,
VVDDA, VVDDB = 12 V, f = 1 kHz
6
12
ns
tPWmin
Minimum input pulse width that
passes to output,
see Figure 25 and Figure 26
Output does not change the state if
input signal less than tPWmin
10
20
ns
tPDHL
Propagation delay at falling edge,
see Figure 27
INx high threshold, VINH, to 10% of
the output
28
40
ns
tPDLH
Propagation delay at rising edge,
see Figure 27
INx low threshold, VINL, to 90% of
the output
28
40
ns
tPWD
Pulse width distortion in each
channel, see Figure 27
|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB|
5.5
ns
tDM
Propagation delays matching,
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|,
see Figure 27
5
ns
f = 250kHz
VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See Figure 31
INA or INB tied to VCCI
tVCCI+ to
OUT
tVDD+ to
TEST CONDITIONS
MIN
40
OUT
VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
INA or INB tied to VCCI
See Figure 32
|CMH|
High-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1000 V;
100
|CML|
Low-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1000 V;
100
(1)
UNIT
µs
22
V/ns
Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
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2000
100
IVDDA/B for VDD = 12V
IVDDA/B for VDD = 18V
Safety Limiting Power (mW)
Safety Limiting Current per Channel (mA)
6.11 Thermal Derating Curves
80
60
40
20
1600
1200
800
400
0
0
0
50
100
150
Ambient Temperature (qC)
200
0
D002
50
100
150
Ambient Temperature (qC)
200
D003
Current in Each Channel with Both Channels Running
Simultaneously
Figure 1. Thermal Derating Curve for Limiting Current Per
VDE
10
Figure 2. Thermal Derating Curve for Limiting Power Per
VDE
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6.12 Typical Characteristics
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
2.7
VCCI = 3.3V
VCCI = 5.0V
1.45
VCCI Operating Current (mA)
VCCI Quiescent Current (mA)
1.5
1.4
1.35
1.3
1.25
1.2
-40
-20
0
20
No Load
40
60
80 100
Temperature (qC)
120
140
2.65
2.6
2.55
2.5
2.45
2.4
-40
160
-20
0
D004
20
40
60
80 100
Junction Temperature (qC)
Figure 3. VCCI Quiescent Current
140
160
D005
Figure 4. VCCI Operating Current - IVCCI
VDD Per Channel Quiescent Current (mA)
VCCI = 3.3V
VCCI = 5.0V
2.58
2.56
2.54
2.52
2.5
0
100
200
300
400 500 600 700
Frequency (kHz)
800
900 1000
1.6
VDD = 12V
VDD = 18V
1.4
1.2
1
0.8
-40
-20
0
D006
20
40
60
80 100
Junction Temperature (qC)
No Load
Figure 5. VCCI Operating Current vs. Frequency
3
2.7
2.4
2.1
VDD = 12V, fS=50kHz
VDD = 12V, fS=1.0MHz
VDD = 15V, fS=50kHz
VDD = 15V, fS=1.0MHz
1.8
1.5
1.2
0.9
-40
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
160
160
D007
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
VDD = 12V
VDD = 15V
1.2
1
0
100
No Load
Figure 7. VDD Per Channel Operating Current - IVDDA/B
140
INA = INB = GND
D008
No Load
120
Figure 6. VDD Per Channel Quiescent Current (IVDDA, IVDDB)
VDD Per Channel Operating Current (mA)
VDD Per Channel Operating Current (mA)
120
INA = INB = GND
2.6
VCCI Operating Current (mA)
VCCI = 3.3V, fS=50kHz
VCCI = 3.3V, fS=1.0MHz
VCCI = 5.0V, fS=50kHz
VCCI = 5.0V, fS=1.0MHz
200
300
400 500 600 700
Frequency (kHz)
800
900 1000
D009
INA and INB both switching
Figure 8. Per Channel Operating Current (IVDDA/B) vs.
Frequency
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Typical Characteristics (continued)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
212
2.9
VCCI UVLO Hysteresis (mV)
VCCI UVLO Thresholds (V)
VVCCI_ON
VVCCI_OFF
2.8
2.7
2.6
2.5
2.4
-40
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
204
200
196
192
188
-40
160
-20
0
D010
Figure 9. VCCI UVLO Threshold Voltage
20
40
60
80 100
Junction Temperature (qC)
120
140
160
D011
Figure 10. VCCI UVLO Threshold Hysteresis Voltage
540
VDD UVLO Hysteresis (mV)
9
VDD UVLO Thresholds (V)
208
8.7
8.4
8.1
7.8
530
520
510
VVDD_ON
VVDD_OFF
7.5
-40
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
500
-40
160
Figure 11. VDD UVLO Threshold Voltage
INA/INB/DIS Threshold Hysteresis (mV)
INA/INB/DIS Thresholds (V)
20
40
60
80 100
Junction Temperature (qC)
120
140
160
D013
Figure 12. VDD UVLO Threshold Hysteresis Voltage
IN/DIS High
IN/DIS Low
2
1.5
1
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
160
IN/DIS High
850
825
800
775
750
-40
-20
D014
Figure 13. INA/INB/DIS High and Low Threshold Voltage
12
0
875
2.5
0.5
-40
-20
D012
0
20
40
60
80 100
Junction Temperature (qC)
120
140
160
D015
Figure 14. INA/INB/DIS High and Low Threshold Hysteresis
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Typical Characteristics (continued)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
10
37.5
OUTA/OUTB Pull-Up
OUTA/OUTB Pull-Down
Rising Edge (tPDLH)
Falling Edge (tPDHL)
35
Propagation Delay (ns)
Resistance (:)
8
6
4
32.5
30
27.5
25
2
22.5
0
-40
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
20
-40
160
Figure 15. OUT Pullup and Pulldown Resistance
20
40
60
80 100
Junction Temperature (qC)
120
140
160
D017
Figure 16. Propagation Delay, Rising and Falling Edge
Rising Edge
Falling Edge
2
Pulse Width Distortion (ns)
Propagation Delay Matching (ns)
0
3
3
1
0
-1
-2
-40
-20
D016
2
1
0
-1
-2
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
-3
-40
160
-20
0
D018
20
40
60
80 100
Junction Temperature (qC)
120
140
160
D019
tPDLH – tPDHL
Figure 17. Propagation Delay Matching, Rising and Falling
Edge
Figure 18. Pulse Width Distortion
10
60
DIS Low to High
DIS High to Low
56
8
DIS Response Time (ns)
Rising and Falling Time (ns)
Rising
Falling
6
4
2
52
48
44
40
36
0
-40
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
160
32
-40
-20
D020
0
20
40
60
80 100
Junction Temperature (qC)
120
140
160
D021
CL = 1.8 nF
Figure 19. Rise Time and Fall Time
Figure 20. DISABLE Response Time
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Typical Characteristics (continued)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
10
VDD Open
VDD Tied to VSS
9
2
Minimum Input Pulse (ns)
Output Active Pull-Down Voltage (V)
2.5
1.5
1
0.5
0
-40
8
7
6
5
-20
0
20
40
60
80 100
Junction Temperature (qC)
120
140
4
-40
160
Figure 21. OUTPUT Active Pulldown Voltage
RDT = 10k:
RDT = 20k:
RDT = 50k:
120
140
160
D023
RDT = 10k:
RDT = 20k:
RDT = 50k:
Dead Time Matching (ns)
5
500
Dead Time (ns)
20
40
60
80 100
Junction Temperature (qC)
6
600
400
300
200
100
4
3
2
1
0
-1
-20
0
20
40
60
80 100
Junction Temperature (°C)
120
140
160
-2
-40
-20
D024
Figure 23. Dead Time Temperature Drift
14
0
Figure 22. Minimum Pulse that Changes Output
700
0
-40
-20
D022
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0
20
40
60
80 100
Junction Temperature (°C)
120
140
160
D025
Figure 24. Dead Time Matching
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7 Parameter Measurement Information
7.1 Minimum Pulses
A typical 5-ns deglitch filter removes small input pulses introduced by ground bounce or switching transients. An
input pulse with duration longer than tPWmin, typically 10 ns, must be asserted on INA or INB to guarantee an
output state change at OUTA or OUTB. See Figure 25 and Figure 26 for detailed information of the operation of
deglitch filter.
INx
VINH
VINL
VINL
VINH
INx
tPWM < tPWmin
tPWM < tPWmin
OUTx
OUTx
Figure 25. Deglitch Filter – Turn ON
Figure 26. Deglitch Filter – Turn OFF
7.2 Propagation Delay and Pulse Width Distortion
Figure 27 shows calculation of pulse width distortion (tPWD) and delay matching (tDM) from the propagation delays
of channels A and B. To measure delay matching, both inputs must be in phase, and the DT pin must be shorted
to VCCI to enable output overlap.
INA/B
tPDLHA
tPDHLA
tDM
OUTA
tPDLHB
tPDHLB
tPWDB = |tPDLHB t tPDHLB|
OUTB
Figure 27. Delay Matching and Pulse Width Distortion
7.3 Rising and Falling Time
Figure 28 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how
short rising and falling times are achieved see Output Stage.
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Rising and Falling Time (continued)
80%
tRISE
90%
tFALL
20%
10%
Figure 28. Rising and Falling Time Criteria
7.4 Input and Disable Response Time
Figure 29 shows the response time of the disable function. For more information, see Disable Pin.
INx
DIS High
Response Time
DIS
DIS Low
Response Time
OUTx
90%
90%
tPDLH
tPDHL
10%
10%
10%
Figure 29. Disable Pin Timing
7.5 Programmable Dead Time
Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (RDT) between DT and
GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this
pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place this capacitor and RDT
close to the DT pin.. For more details on dead time, refer to Programmable Dead Time (DT) Pin.
16
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Programmable Dead Time (continued)
INA
INB
90%
10%
OUTA
tPDHL
tPDLH
90%
10%
OUTB
tPDHL
Dead Time
(Set by RDT)
Dead Time
(Determined by Input signals if
longer than DT set by RDT)
Figure 30. Dead Time Switching Parameters
7.6 Power-up UVLO Delay to OUTPUT
Whenever the supply voltage VCCI crosses from below the falling threshold VVCCI_OFF to above the rising
threshold VVCCI_ON, and whenever the supply voltage VDDx crosses from below the falling threshold VVDDx_OFF to
above the rising threshold VVDDx_ON, there is a delay before the outputs begin responding to the inputs. For VCCI
UVLO this delay is defined as tVCCI+ to OUT, and is typically 40 µs. For VDDx UVLO this delay is defined as tVDD+ to
OUT, and is typically 22 µs. TI recommends allowing some margin before driving input signals, to ensure the
driver VCCI and VDD bias supplies are fully activated. Figure 31 and Figure 32 show the power-up UVLO delay
timing diagram for VCCI and VDD.
Whenever the supply voltage VCCI crosses below the falling threshold VVCCI_OFF, or VDDx crosses below the
falling threshold VVDDx_OFF, the outputs stop responding to the inputs and are held low within 1 µs. This
asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.
VCCI,
INx
VDDx
VVCCI_ON
VVCCI_OFF
VCCI,
INx
VDDx
tVCCI+ to OUT
OUTx
VVDD_ON
tVDD+ to OUT
VVDD_OFF
OUTx
Figure 31. VCCI Power-up UVLO Delay
Figure 32. VDDA/B Power-up UVLO Delay
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7.7 CMTI Testing
Figure 33 is a simplified diagram of the CMTI testing configuration.
VCC
VDD
VCC
VCCI
GND
DIS
DT
GND
VCCI
2
15
3
14
4
5
Isolation Barrier
INB
16
1
Input Logic
INA
VDDA
OUTA
OUTA
VSSA
Functional
Isolation
11
6
10
8
9
VDDB
OUTB
OUTB
VSSB
VSS
Common Mode Surge
Generator
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Figure 33. Simplified CMTI Testing Setup
18
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8 Detailed Description
8.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21222-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and
motor drive topologies, as well as drive several types of transistors. The UCC21222-Q1 has many features that
allow it to integrate well with control circuitry and protect the gates it drives such as: resistor-programmable dead
time (DT) control, disable pin, and under voltage lock out (UVLO) for both input and output supplies. The
UCC21222-Q1 also holds its outputs low when the inputs are left open or when the input pulse duration is too
short. The driver inputs are CMOS and TTL compatible for interfacing with digital and analog power controllers
alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and independent control
of each of the outputs.
8.2 Functional Block Diagram
INA
1
16 VDDA
200 k:
VCCI 3,8
GND
4
DT
6
DIS
5
UVLO
Dead Time
Control
Driver
DEMOD
UVLO
Isolation Barrier
MOD
VCCI
Deglitch
Filter
14 VSSA
13 NC
Functional Isolation
INB
2
NC
7
12 NC
11 VDDB
Driver
50 k:
MOD
15 OUTA
DEMOD
UVLO
Deglitch
Filter
10 OUTB
9
VSSB
200 k:
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8.3 Feature Description
8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC21222-Q1 has an internal under voltage lock out (UVLO) protection feature on each supply voltage
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the channel output low, regardless of
the status of the input pins.
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (illustrated in Figure 34). In this condition, the
upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP.
In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically around 1.5V, regardless of whether bias power is available.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
Figure 34. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which
commonly occurs when the device starts switching and operating current consumption increases suddenly.
The inputs of the UCC21222-Q1 also have an internal under voltage lock out (UVLO) protection feature. The
inputs cannot affect the outputs unless the supply voltage VCCI exceeds VVCCI_ON on start-up. The outputs are
held low and cannot respond to inputs when the supply voltage VCCI drops below VVCCI_OFF after start-up. Like
the UVLO for VDD, there is hystersis (VVCCI_HYS) to ensure stable operation.
Table 1. VCCI UVLO Feature Logic
CONDITION
20
INPUTS
OUTPUTS
INA
INB
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
H
L
L
L
VCCI-GND < VVCCI_ON during device start up
L
H
L
L
VCCI-GND < VVCCI_ON during device start up
H
H
L
L
VCCI-GND < VVCCI_ON during device start up
L
L
L
L
VCCI-GND < VVCCI_OFF after device start up
H
L
L
L
VCCI-GND < VVCCI_OFF after device start up
L
H
L
L
VCCI-GND < VVCCI_OFF after device start up
H
H
L
L
VCCI-GND < VVCCI_OFF after device start up
L
L
L
L
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Table 2. VDD UVLO Feature Logic
CONDITION
INPUTS
INA
OUTPUTS
INB
OUTA
OUTB
VDD-VSS < VVDD_ON during device start up
H
L
L
L
VDD-VSS < VVDD_ON during device start up
L
H
L
L
VDD-VSS < VVDD_ON during device start up
H
H
L
L
VDD-VSS < VVDD_ON during device start up
L
L
L
L
VDD-VSS < VVDD_OFF after device start up
H
L
L
L
VDD-VSS < VVDD_OFF after device start up
L
H
L
L
VDD-VSS < VVDD_OFF after device start up
H
H
L
L
VDD-VSS < VVDD_OFF after device start up
L
L
L
L
8.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up (see VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes). Table 3 shows the operation with INA, INB and DIS and the corresponding output state.
Table 3. INPUT/OUTPUT Logic Table (1)
INPUTS
INA
INB
L
L
L
DIS
OUTPUTS
OUTB
L or Left Open
L
L
H
L or Left Open
L
H
H
L
L or Left Open
H
L
H
H
L or Left Open
L
L
DT is programmed with RDT.
DT pin is left open or pulled to VCCI.
H
H
L or Left Open
H
H
Left Open
Left Open
L or Left Open
L
L
X
X
H
L
L
(1)
NOTE
OUTA
If the dead time function is used, output transitions occur after the dead
time expires. See Programmable Dead Time (DT) Pin.
"X" means L, H or left open. For improved noise immunity, TI recommends connecting INA, INB, and DIS to GND, and DT to VCCI,
when these pins are not used.
8.3.3 Input Stage
The input pins (INA, INB, and DIS) of the UCC21222-Q1 are based on a TTL and CMOS compatible inputthreshold logic that is totally isolated from the VDD supply voltage of the output channels. The input pins are
easy to drive with logic-level control signals (such as those from 3.3-V microcontrollers), since the UCC21222-Q1
has a typical high threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature
(see Figure 11 and Figure 13). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise immunity and stable
operation. If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors
are typically 200 kΩ for INA/B and 50 kΩ for DIS (see Functional Block Diagram). TI recommends grounding any
unused inputs.
The amplitude of any signal applied to the inputs must never be at a voltage higher than VCCI.
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8.3.4 Output Stage
The UCC21222-Q1 output stage features a pull-up structure which delivers the highest peak-source current
when it is most needed: during the Miller plateau region of the power-switch turn on transition (when the power
switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel
MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to
provide a boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the
N-channel MOSFET during a narrow instant when the output is changing states from low to high. The onresistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the pull-up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC21222-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH
parameter.
The pull-down structure of the UCC21222-Q1 is composed of an N-channel MOSFET. The ROL parameter, which
is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs
of the UCC21222-Q1 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output
voltage swings between VDD and VSS for rail-to-rail operation.
VDD
ROH
Input
Signal
ShootThrough
Prevention
Circuitry
RNMOS
OUT
Pull Up
ROL
VSS
Figure 35. Output Stage
22
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8.3.5 Diode Structure in the UCC21222-Q1
Figure 36 illustrates the multiple diodes involved in the ESD protection components. This provides a pictorial
representation of the absolute maximum rating for the device.
VCCI
VDDA
3,8
16
20 V
6V
15 OUTA
6V
14 VSSA
INA
1
INB
2
DIS
5
DT
6
11 VDDB
20 V
10 OUTB
4
9
GND
VSSB
Figure 36. ESD Structure
8.4 Device Functional Modes
8.4.1 Disable Pin
When the DIS pin is set high, both outputs are shut down simultaneously. When the DIS pin is set low or left
open, the UCC21222-Q1 operates normally. The DIS circuit logic structure is nearly identical compared to INA or
INB, and the propagation delay is similar (see Figure 20). The DIS pin is only functional (and necessary) when
VCCI stays above the UVLO threshold. It is recommended to tie this pin to GND if the DIS pin is not used to
achieve better noise immunity.
8.4.2 Programmable Dead Time (DT) Pin
The UCC21222-Q1 allows the user to adjust dead time (DT) in the following ways:
8.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
Outputs completely match inputs, so no minimum dead time is asserted. This allows the outputs to overlap. TI
recommends connecting this pin directly to VCCI if it is not used to achieve better noise immunity.
8.4.2.2 Connecting a Programming Resistor between DT and GND Pins
Program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value can be
determined from:
tDT | 10 u RDT
where
•
•
tDT is the programmed dead time, in nanoseconds.
RDT is the value of resistance between DT pin and GND, in kilo-ohms.
(1)
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Device Functional Modes (continued)
The steady state voltage at the DT pin is about 0.8 V. RDT programs a small current at this pin, which sets the
dead time. As the value of RDT increases, the current sourced by the DT pin decreases. The DT pin current will
be less than 10 µA when RDT = 100 kΩ. For larger values of RDT, TI recommends placing RDT and a ceramic
capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better
dead time matching between both channels.
The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed
dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may
also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a
dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs
will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does
not affect the programmed dead time setting for normal operation. Various driver dead time logic operating
conditions are illustrated and explained in Figure 37.
INA
INB
DT
OUTA
OUTB
A
B
C
D
E
F
Figure 37. Input and Output Logic Relationship with Input Signals
Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead
time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead
time for OUTA. In this case, the input signal dead time is longer than the programmed dead time. When INA
goes high after the duration of the input signal dead time, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead
time to OUTB. In this case, the input signal dead time is longer than the programmed dead time. When INB goes
high after the duration of the input signal dead time, it immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, OUTB is immediately pulled
low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low.
After the programmed dead time, OUTA is allowed to go high.
Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, OUTA is immediately pulled
low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low.
After the programmed dead time, OUTB is allowed to go high.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC21222-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal
capability of the UCC21222-Q1 (with up to 5.5-V VCCI and 18-V VDDA/VDDB) allows the device to be used as a
low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or GaN transistor. With
integrated components, advanced protection features (UVLO, dead time, and disable) and optimized switching
performance, the UCC21222-Q1 enables designers to build smaller, more robust designs for enterprise, telecom,
automotive, and industrial applications with a faster time to market.
9.2 Typical Application
The circuit in Figure 38 shows a reference design with the UCC21222-Q1 driving a typical half-bridge
configuration which could be used in several popular power converter topologies such as synchronous buck,
synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VCC
VDD
RBOOT
HV DC-Link
VCC
RIN
INB
PWM-B
CIN
PC
VCCI
CVCC
GND
I/O
DIS
DIS
RDIS
16
2
15
3
14
4
5
6
CDT
VCCI
VDDA
ROFF
RON
OUTA
VSSA
8
CIN
RGS
CBOOT
SW
Functional
Isolation
VDD
11
DT
CDIS
RDT
1
Isolation Barrier
PWM-A
Input Logic
INA
10
VDDB
OUTB
VSSB
ROFF
RON
CBOOT
RGS
9
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Figure 38. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Table 4 lists reference design parameters for the example application: UCC21222-Q1 driving 650-V MOSFETs in
a high side-low side configuration.
Table 4. UCC21222-Q1 Design Requirements
PARAMETER
VALUE
UNITS
Power transistor
650-V, 150-mΩ RDS_ON with 12-V VGS
-
VCC
5.0
V
VDD
12
V
Input signal amplitude
3.3
V
Switching frequency (fs)
100
kHz
Dead Time
200
ns
DC link voltage
400
V
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC21222 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to 100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
9.2.2.3 Select Dead Time Resistor and Capacitor
From Equation 1, a 20-kΩ resistor is selected to set the dead time to 200 ns. A 2.2-nF capacitor is placed in
parallel close to the DT pin to improve noise immunity.
9.2.2.4 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
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When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss
introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 400
VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.
Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example.
A bootstrap resistor, RBOOT, is used to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive
negative transient voltage. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode
used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode.
The estimated worst case peak current through DBoot is,
IDBoot
pk
VDD VBDF
RBoot
12V 1.5V
| 4A
2.7:
where
•
VBDF is the estimated bootstrap diode forward voltage drop around 4 A.
(2)
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9.2.2.5 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
1. Limit ringing caused by parasitic inductances/capacitances.
2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4. Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC21222-Q1 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:
IOA
IOB
§
VDD VBDF
min ¨ 4A,
¨
RNMOS || ROH RON RGFET _ Int
©
·
¸
¸
¹
§
VDD
min ¨ 4A,
¨
RNMOS || ROH RON RGFET _ Int
©
·
¸
¸
¹
(3)
where
•
•
•
RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(4)
In this example:
IOA
IOB
VDD VBDF
RNMOS || ROH RON RGFET _ Int
12V 0.8V
| 2.3A
1.47: || 5: 2.2: 1.5:
VDD
RNMOS || ROH RON RGFET _ Int
12V
| 2.5A
1.47: || 5: 2.2: 1.5:
(5)
(6)
Therefore, the high-side and low-side peak source current is 2.3 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
IOA
IOB
§
VDD VBDF VGDF
min ¨ 6A,
¨
R
OL ROFF || RON RGFET _ Int
©
·
¸
¸
¹
§
min ¨ 6A,
¨
ROL
©
·
¸
¸
¹
VDD VGDF
ROFF || RON RGFET _ Int
(7)
where
•
•
•
28
ROFF: External turn-off resistance, ROFF=0 in this example;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(8)
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In this example,
VDD VBDF VGDF
ROL ROFF || RON RGFET _ Int
IOA
IOB
ROL
VDD VGDF
ROFF || RON RGFET _ Int
12V 0.8V 0.85V
| 5.0A
0.55: 0: 1.5:
(9)
12V 0.85V
| 5.4A
0.55: 0: 1.5:
(10)
Therefore, the high-side and low-side peak sink current is 5.0 A and 5.4A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
9.2.2.6 Estimating Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21222-Q1 (PGD) and the
power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not
included in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21222-Q1, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. Figure 5 and Figure 8 show the operating current consumption vs. operating frequency
with no load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with INA/INB
switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI ≈ 2.5 mA, and IVDDA = IVDDB ≈ 1.5 mA. Therefore,
the PGDQ can be calculated with
PGDQ
VVCCI u IVCCI
VVDDA u IDDA
VVDDB u IDDB
50mW
(11)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW
2 u VDD u QG u fSW
where
•
QG is the gate charge of the power transistor.
(12)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:
PGSW
2 u 12V u 100nC u 100kHz
240mW
(13)
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QG represents the total gate charge of the power transistor switching 480 V at 14 A provided by the datasheet,
and is subject to change with different testing conditions. The UCC21222-Q1 gate driver loss on the output
stage, PGDO, is part of PGSW. PGDO will be equal to PGSW if the external gate driver resistances are zero, and all
the gate driver loss is dissipated inside the UCC21222-Q1. If there are external turn-on and turn-off resistances,
the total loss will be distributed between the gate driver pull-up/down resistances and external gate resistances.
Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated
to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in
these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
PGSW §
ROH || RNMOS
u¨
¨ ROH || RNMOS RON RGFET _ Int
2
©
PGDO
ROL
ROL
ROFF || RON RGFET _ Int
·
¸
¸
¹
(14)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the the
UCC21222-Q1 gate driver loss can be estimated with:
240mW §
5: || 1.47:
u¨
2
© 5: || 1.47: 2.2: 1.5:
PGDO
·
0.55:
¸ | 60mW
0.55: 0: 1.5: ¹
(15)
Case 2 - Nonlinear Pull-Up/Down Resistor:
2 u fSW
PGDO
TR _ Sys
ª
«
u 4A u
VDD
«
0
¬«
³
TF _ Sys
VOUTA /B t dt 6A u
³
0
º
VOUTA /B t dt »
»
»¼
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(16)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pulldown based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21222Q1 PGD, is:
PGD
PGDQ
PGDO
(17)
which is equal to 127 mW in the design example.
9.2.2.7 Estimating Junction Temperature
The junction temperature of the UCC21222-Q1 can be estimated with:
TJ
TC
< JT u PGD
where
•
•
•
TJ is the junction temperature.
TC is the UCC21222-Q1 case-top temperature measured with a thermocouple or some other instrument.
ψJT is the junction-to-top characterization parameter from the Thermal Information table.
(18)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
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estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor
and IC Package Thermal Metrics application report.
9.2.2.8 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC
will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500
nF when a DC bias of 15 VDC is applied.
9.2.2.8.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 25-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
9.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
QTotal
QG
IVDD @100kHz No Load
fSW
100nC
1.5mA
100kHz
115nC
where
•
•
•
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
(19)
Therefore, the absolute minimum CBoot requirement is:
QTotal
'VVDDA
CBoot
115nC
0.5V
230nF
where
•
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
(20)
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.
CBoot =1 F
(21)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
NOTE
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and
VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal
command. Also during initial CBOOT charging cycles, the bootstrap diode has highest
reverse recovery current and losses.
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9.2.2.8.3 Select a VDDB Capacitor
Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in
Figure 38) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current
for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If
the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor
with a value over 10 µF, should be used in parallel with CVDD.
9.2.2.9 Application Circuits with Output Stage Negative Bias
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
Figure 39 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 17 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 17 V – 5.1 V ≈ 12 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
16
1
15
2
VDDA
ROFF
CA1
RZ
OUTA
+
VA
±
RON
CIN
CA2
4
5
Input Logic
3
Isolation Barrier
VSSA
VZ
14
SW
Functional
Isolation
11
6
10
VDDB
OUTB
VSSB
8
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9
Figure 39. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
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Figure 40 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
16
1
15
2
VDDA
CA1
OUTA
CA2
4
5
Input Logic
3
Isolation Barrier
VSSA
14
HV DC-Link
ROFF
+
VA+
±
RON
CIN
+
VA±
SW
Functional
Isolation
11
6
10
8
9
VDDB
OUTB
VSSB
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Figure 40. Negative Bias with Two Iso-Bias Power Supplies
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The last example, shown in Figure 41, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and
the bootstrap power supply can be used for the high side drive. This design requires the least cost and design
effort among the three solutions. However, this solution has limitations:
1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which
means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed
duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this
solution.
2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,
which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)
diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%
duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in
the other two example circuits.
VDD
RBOOT
HV DC-Link
1
16
2
15
VDDA
ROFF
RON
CBOOT
CIN
RGS
Input Logic
Isolation Barrier
14
3
5
VZ
OUTA
VSSA
4
CZ
6
SW
Functional
Isolation
VDD
11
10
VDDB
CZ
VZ
OUTB
ROFF
RON
CVDD
8
RGS
VSSB
9
VSS
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Figure 41. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
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9.2.3 Application Curves
Figure 42 and Figure 43 shows the bench test waveforms for the design example shown in Figure 38 under
these conditions: VCC = 5.0 V, VDD = 12 V, fSW = 100 kHz, VDC-Link = 400 V.
Channel 1 (Blue): Gate-source signal on the high side power transistor.
Channel 2 (Cyan): Gate-source signal on the low side power transistor.
Channel 3 (Pink): INA pin signal.
Channel 4 (Green): INB pin signal.
In Figure 42, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals. The gate drive signals on
the power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement
section of Figure 42. Note that with high voltage present, lower bandwidth differential probes are required, which
limits the achievable accuracy of the measurement.
Figure 43 shows a zoomed-in version of the waveform of Figure 42, with measurements for propagation delay
and dead time. Importantly, the output waveform is measured between the power transistors’ gate and source
pins, and is not measured directly from the driver OUTA and OUTB pins.
Figure 42. Bench Test Waveform for INA/B and OUTA/B
Figure 43. Zoomed-In bench-test waveform
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10 Power Supply Recommendations
The recommended input supply voltage (VCCI) for the UCC21222-Q1 is between 3 V and 5.5 V. The output bias
supply voltage (VDDA/VDDB) ranges from 9.2 V to 18 V. The lower end of this bias supply range is governed by
the internal under voltage lockout (UVLO) protection feature of each device. VDD and VCCI must not fall below
their respective UVLO thresholds during normal operation. (For more information on UVLO see VDD, VCCI, and
Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate
voltage of the power device being driven by the UCC21222-Q1. The recommended maximum VDDA/VDDB is 18
V.
A local bypass capacitor should be placed between the VDD and VSS pins, to supply current when the output
goes high into a capacitive load. This capacitor should be positioned as close to the device as possible to
minimize parasitic impedance. A low ESR, ceramic surface mount capacitor is recommended. If the bypass
capacitor impedance is too large, resistive and inductive parasitics could cause the supply voltage seen at the IC
pins to dip below the UVLO threshold unexpectedly. To filter high frequency noise between VDD and VSS, it can
be helpful to place a second capacitor with lower impedance at higher frequency. As an example, the primary
bypass capacitor could be 1 µF, with a secondary high frequency bypass capacitor of 100 pF.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of the UCC21222-Q1, this bypass capacitor has a
minimum recommended value of 100 nF.
36
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11 Layout
11.1 Layout Guidelines
Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21222-Q1.
11.1.1 Component Placement Considerations
• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
• To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
• To improve noise immunity when driving the DIS pin from a distant microcontroller, TI recommends adding a
small bypass capacitor, ≥ 1000 pF, between the DIS pin and GND.
• If the dead time feature is used, TI recommends placing the programming resistor RDT and capacitor close to
the DT pin of the UCC21222-Q1 to prevent noise from unintentionally coupling to the internal dead time
circuit. The capacitor should be ≥ 2.2 nF.
11.1.2 Grounding Considerations
• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSBreferenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
11.1.3 High-Voltage Considerations
• To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may
compromise the isolation performance.
• For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout
between the high and low-side PCB traces.
11.1.4 Thermal Considerations
• A large amount of power may be dissipated by the UCC21222-Q1 if the driving voltage is high, the load is
heavy, or the switching frequency is high (refer to Estimating Gate Driver Power Loss for more details).
Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal
impedance (θJB).
• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see Figure 45 and Figure 46). However, high voltage PCB
considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces
or copper from different high-voltage planes overlap.
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11.2 Layout Example
Figure 44 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 44. Layout Example
Figure 45 and Figure 46 shows top and bottom layer traces and copper.
NOTE
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
Figure 45. Top Layer Traces and Copper
Figure 46. Bottom Layer Traces and Copper (Flipped)
38
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Layout Example (continued)
Figure 47 and Figure 48 are 3-D layout pictures with top view and bottom views.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
Figure 47. 3-D PCB Top View
Figure 48. 3-D PCB Bottom View
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC21222 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC21222-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
40
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12.6 Trademarks (continued)
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC21222QDQ1
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
21222Q
UCC21222QDRQ1
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
21222Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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