UCC21521
SLUSCO3B – SEPTEMBER 2016 – REVISED DECEMBER 2021
UCC21521 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with Enable
1 Features
3 Description
•
The UCC21521 is an isolated dual-channel gate
driver with 4-A source and 6-A sink peak current. It
is designed to drive power MOSFETs, IGBTs, and SiC
MOSFETs up to 5-MHz with best-in-class propagation
delay and pulse-width distortion.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Universal: dual low-side, dual high-side or halfbridge driver
Operating temperature range –40 to +125°C
Switching parameters:
– 19-ns typical propagation delay
– 10-ns minimum pulse width
– 5-ns maximum delay matching
– 6-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater
than 100 V/ns
Surge immunity up to 12.8 kV
Isolation barrier life >40 years
4-A peak source, 6-A peak sink output
TTL and CMOS compatible inputs
3-V to 18-V input VCCI range to interface with both
digital and analog controllers
Up to 25-V VDD output drive supply
– 5-V, 8-V, 12-V VDD UVLO options
Programmable overlap and dead time
Rejects input pulses and noise transients shorter
than 5 ns
Fast enable for power sequencing
Wide body SOIC-16 (DW) package
Safety-related certifications:
– 8000-VPK reinforced isolation per DIN V VDE V
0884-11:2017-01
– 5700-VRMS Isolation for 1 minute per UL 1577
– CSA certification per IEC 60950-1, IEC
62368-1, IEC 61010-1 and IEC 60601-1 end
equipment standards
– CQC certification per GB4943.1-2011
The input side is isolated from the two output
drivers by a 5.7-kVRMS reinforced isolation barrier,
with a minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1500 VDC.
Every driver can be configured as two low-side
drivers, two high-side drivers, or a half-bridge driver
with programmable dead time (DT). The EN pin
pulled low shuts down both outputs simultaneously
and allows for normal operation when left open or
pulled high. As a fail-safe measure, primary-side logic
failures force both outputs low.
The device accepts VDD supply voltages up to 25 V.
A wide input VCCI range from 3 V to 18 V makes
the driver suitable for interfacing with both analog and
digital controllers. All the supply voltage pins have
under voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21521
enables high efficiency, high power density, and
robustness in a wide variety of power applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC21521ADW
DW SOIC (16)
10.30 mm × 7.50 mm
2 Applications
UCC21521DW
DW SOIC (16)
10.30 mm × 7.50 mm
•
UCC21521CDW
DW SOIC (16)
10.30 mm × 7.50 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VCCI 3,8
16 VDDA
Driver
INA
1
EN
5
NC
7
DT
6
INB
2
GND
4
MOD
DEMOD
Reinforced Isolation
•
•
•
•
•
Isolated converters in offline AC-to-DC power
supplies
Server, telecom, IT, and industrial infrastructures
Motor drive and DC-to-AC solar inverters
LED lighting
Inductive heating
Uninterruptible power supply (UPS)
EN,
UVLO
and
Deadtime
UVLO
15 OUTA
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
Driver
MOD
DEMOD
UVLO
10 OUTB
9
VSSB
Copyright © 2016, Texas Instruments Incorporated
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21521
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SLUSCO3B – SEPTEMBER 2016 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 5
6.7 Safety-Related Certifications...................................... 6
6.8 Safety-Limiting Values................................................ 7
6.9 Electrical Characteristics.............................................7
6.10 Switching Characteristics..........................................9
6.11 Insulation Characteristics Curves............................10
6.12 Typical Characteristics............................................ 11
7 Parameter Measurement Information.......................... 16
7.1 Propagation Delay and Pulse Width Distortion......... 16
7.2 Rising and Falling Time.............................................16
7.3 Input and Enable Response Time.............................16
7.4 Programmable Dead Time........................................ 17
7.5 Powerup UVLO Delay to OUTPUT........................... 17
7.6 CMTI Testing.............................................................17
8 Detailed Description......................................................19
8.1 Overview................................................................... 19
8.2 Functional Block Diagram......................................... 19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................23
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 25
10 Power Supply Recommendations..............................36
11 Layout........................................................................... 37
11.1 Layout Guidelines................................................... 37
11.2 Layout Example...................................................... 38
12 Device and Documentation Support..........................40
12.1 Third-Party Products Disclaimer............................. 40
12.2 Documentation Support.......................................... 40
12.3 Certifications........................................................... 40
12.4 Receiving Notification of Documentation Updates..40
12.5 Support Resources................................................. 40
12.6 Trademarks............................................................. 40
12.7 Electrostatic Discharge Caution..............................40
12.8 Glossary..................................................................40
13 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
Changes from Revision A (October 2021) to Revision B (December 2021)
Page
• Changed maximum pulse-width distortion from "5-ns" to "6-ns" in Features .....................................................1
• Changed maximum pulse-width distortion specification from "5-ns" to "6-ns" in Switching Characteristics ......9
Changes from Revision * (October 2016) to Revision A (October 2021)
Page
• Updated Safety-Related and Regulatory Approvals........................................................................................... 1
• Updated DT pin description................................................................................................................................ 3
• Updated Certifications........................................................................................................................................ 6
• Added the powerup delay time specifications.....................................................................................................9
• Added Powerup UVLO Delay to OUTPUT ...................................................................................................... 17
• Updated for bootstrap recommendation........................................................................................................... 26
• Added Ferrite bead recommendation............................................................................................................... 27
• Added Gate to Source Resistor Selection ....................................................................................................... 28
• Updated Certifications...................................................................................................................................... 40
2
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5 Pin Configuration and Functions
INA
1
16
VDDA
INB
2
15
OUTA
VCCI
3
14
VSSA
GND
4
13
NC
EN
5
12
NC
DT
6
11
VDDB
NC
7
10
OUTB
VCCI
8
9
VSSB
Not to scale
Figure 5-1. DW Package 16-Pin SOIC Top View
Table 5-1. Pin Functions
PIN
NAME
EN
NO.
5
DT
6
I/O(1)
DESCRIPTION
I
Enable both driver outputs if asserted high or left open, disable the output if set low. This pin
is pulled high internally if left open. It is recommended to tie this pin to VCCI if not used to
achieve better noise immunity.
I
Programmable dead time function.
Tying DT to VCCI allows the outputs to overlap. Placing a 500-Ω to 500-kΩ resistor (RDT)
between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is
recommended to parallel a ceramic capacitor, 2.2nF or above, close to the DT pin with RDT
to achieve better noise immunity. It is not recommended to leave DT floating.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin
is pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin
is pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
NC
7
–
No internal connection.
NC
12
–
No internal connection.
NC
13
–
No internal connection.
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
VCCI
8
P
Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL
capacitor located as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P =Power, G= Ground, I= Input, O= Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.3
20
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.3
30
V
OUTA to VSSA, OUTB to VSSB
–0.3
VVDDA+0.3,
VVDDB+0.3
V
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
–2
VVDDA+0.3,
VVDDB+0.3
V
–0.3
VVCCI+0.3
V
–5
VVCCI+0.3
V
Output signal voltage
Input signal voltage
Channel to channel voltage
INA, INB, EN, DT to GND
INA, INB Transient for 50ns
1500
V
Junction temperature, TJ (2)
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
VSSA-VSSB, VSSB-VSSA
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime. See Section 9 for more information on the
typical application and how to avoid device overstress.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
VCCI
VCCI Input supply voltage
5-V UVLO version - UCC21521ADW
VDDA,
VDDB
Driver output bias supply
8-V UVLO version - UCC21521DW
12-V UVLO version - UCC21521CDW
4
MIN
MAX
UNIT
3
18
V
6.5
25
V
9.2
25
V
14.7
25
V
TA
Ambient Temperature
–40
125
°C
TJ
Junction Temperature
–40
130
°C
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6.4 Thermal Information
UCC21521
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
DW-16 (SOIC)
UNIT
78.1
°C/W
Junction-to-case (top) thermal resistance
11.1
°C/W
Junction-to-board thermal resistance
48.4
°C/W
ψJT
Junction-to-top characterization parameter
12.5
°C/W
ψJB
Junction-to-board characterization parameter
48.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Ratings
PD
Power dissipation by UCC21521
PDI
Power dissipation by transmitter side of
UCC21521
PDA, PDB
Power dissipation by each driver side of
UCC21521
VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3
V, 3 MHz 50% duty cycle square wave 1-nF
load
VALUE
UNIT
1.05
W
0.05
W
0.5
W
6.6 Insulation Specifications
PARAMETER
CLR
External clearance(1)
CPG
creepage(1)
External
VALUE
UNIT
Shortest pin to pin distance through air
TEST CONDITIONS
>8
mm
Shortest pin to pin distance across the package surface
>8
mm
>21
µm
> 600
V
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 x 10.5 µm)
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN V VDE 0884-11 (VDE V 0884-11): 2017-01(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum isolation working
voltage
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (See Figure 6-1)
1500
VRMS
DC voltage
2121
VDC
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM , t = 60 sec (qualification)
VTEST = 1.2 x VIOTM, t = 1 s (100% production)
8000
VPK
VIOSM
Maximum surge isolation
voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,VTEST =
1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After Input/Output safety test subgroup 2/3. Vini =
VIOTM, tini = 60s;
Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s
Ω
109
Pollution degree
2
Climatic category
40/125/21
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
6.7 Safety-Related Certifications
VDE
Certified according to DIN
VDE V 0884-11 :2017-01
and DIN EN 60950-1 (VDE
0805 Teil 1):2014-08
6
CSA
Certified according to IEC 60950-1 and IEC
60601-1
UL
Recognized
under UL
1577 Component
Recognition
Program
CQC
Certified according to GB 4943.1-2011
Reinforced insulation per CSA 60950-107+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2,
800 VRMS maximum working voltage (pollution
degree 2, material group I)
Reinforced insulation per CSA 62368-1-14 and
Reinforced Insulation
IEC 62368-1 2nd Ed., 800 VRMS maximum
Maximum Transient
working voltage (pollution degree 2, material
Isolation voltage, 8000 VPK;
group I);
Single protection,
Maximum Repetitive Peak
5700 VRMS
Basic
insulation
per
CSA
61010-1-12+A1
and
Isolation Voltage, 2121 VPK;
Maximum Surge Isolation
IEC 61010-1 3rd Ed., 600 VRMS maximum
Voltage, 8000 VPK
working voltage (pollution degree 2, material
group III);
2 MOPP (Means of Patient Protection) per CSA
60601- 1:14 and IEC 60601-1 Ed. 3.1, 250
VRMS (354 VPK) max working voltage
Reinforced Insulation,Altitude ≤ 5000m,
Tropical Climate, 660 VRMS maximum
working voltage
Certification number:
40040142
Certificate number: CQC16001155011
Master contract number: 220991
File number:
E181974
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6.8 Safety-Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
Safety output supply
current
IS
PS
Safety supply power
TS
Safety temperature(2)
(1)
(2)
TEST CONDITIONS
RθJA = 78.1°C/W, VDDA/B = 12
25°C, TJ = 150°C
See Figure 6-2
V(1),
SIDE
TA =
RθJA = 78.1°C/W, VDDA/B = 25 V(1), TA =
25°C, TJ = 150°C
See Figure 6-2
RθJA = 78.1°C/W, TA = 25°C, TJ = 150°C
See Figure 6-3
MIN
TYP
MAX
UNIT
DRIVER A,
DRIVER B
64
mA
DRIVER A,
DRIVER B
31
mA
INPUT
50
DRIVER A
775
DRIVER B
775
TOTAL
1600
150
mW
°C
VDDA=VDDB=12V is used for the test condition of 5V and 8V UVLO, and VDDA=VDDB=25V is used for 12V UVLO.
The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junctionto-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed
junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K test board for leaded surface
mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS , where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI , where VI is the maximum input voltage.
6.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15 V(1) , 1-µF capacitor from VDDA and
VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI per channel operating current
(f = 500 kHz) current per channel,
COUT = 100 pF
2.0
mA
(f = 500 kHz) current per channel,
COUT = 100 pF, VDD=12 V
2.5
mA
(f = 500 kHz) current per channel,
COUT = 100 pF, VDD=15 V
3.0
mA
IVDDA,
IVDDB
VDDA and VDDB operating current
VCCI UVLO THRESHOLDS
VVCCI_ON
Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
Falling threshold VCCI_OFF
2.35
2.5
2.65
V
VVCCI_HYS
Threshold hysteresis
0.2
V
UCC21521ADW VDD UVLO THRESHOLDS (5-V UVLO VERSION)
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
5.2
5.8
6.3
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
4.9
5.5
6
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
0.3
V
UCC21521DW VDD UVLO THRESHOLDS (8-V UVLO VERSION)
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6.9 Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15 V(1) , 1-µF capacitor from VDDA and
VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
MIN
TYP
MAX
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
PARAMETER
TEST CONDITIONS
8
8.5
9
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
7.5
8
8.5
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
0.5
UNIT
V
UCC21521CDW VDD UVLO THRESHOLDS (12-V UVLO VERSION)
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
12.5
13.5
14.5
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
11.5
12.5
13.5
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
1.0
V
INA and INB
VINAH, VINBH
Input high voltage
1.6
1.8
2
V
VINAL, VINBL
Input low voltage
0.8
1
1.2
V
VINA_HYS,
VINB_HYS
Input hysteresis
VINA, VINB
Negative transient, ref to GND, 50 ns Not production tested, bench test
pulse
only
0.8
V
–5
V
EN THRESHOLDS
8
VENH
Enable high voltage
VENL
Enable low voltage
2.0
V
0.8
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6.9 Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15 V(1) , 1-µF capacitor from VDDA and
VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f =
1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f =
1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, TA = 25°C,
ROHA, ROHB do not represent drive
pull-up performance. See tRISE
in Switching Characteristics and
Output Stage for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 12 V, IOUT = –10
mA, TA = 25°C
11.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 12 V, IOUT = 10
mA, TA = 25°C
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
Pull DT pin to VCCI
DT pin is left open, min spec
characterized only, tested for
outliers
Dead time
RDT = 20 kΩ
(1)
Overlap determined by INA INB
0
160
-
8
15
ns
200
240
ns
VDDA=VDDB=12 V is used for the test condition of 5-V and 8-V UVLO, and VDDA=VDDB = 15 V is used for 12-V UVLO.
6.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15V(1), 1-µF capacitor from VDDA and
VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TYP
MAX
6
16
ns
7
12
ns
20
ns
19
30
ns
19
30
ns
Pulse width distortion |tPDLH – tPDHL|
6
ns
Propagation delays matching
between VOUTA, VOUTB
5
ns
tRISE
Output rise time, 20% to 80%
measured points
COUT = 1.8 nF
tFALL
Output fall time, 90% to 10%
measured points
COUT = 1.8 nF
tPWmin
Minimum pulse width
tPDHL
Propagation delay from INx to OUTx
falling edges
tPDLH
Propagation delay from INx to OUTx
rising edges
tPWD
tDM
tVCCI+ to OUT VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB (See Figure
7-5 )
MIN
Output off for less than minimum,
COUT = 0 pF
f = 100 kHz
40
UNIT
us
INA or INB tied to VCCI
tVDD+ to OUT VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB (See
INA or INB tied to VCCI
Figure 7-6)
50
100
us
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SLUSCO3B – SEPTEMBER 2016 – REVISED DECEMBER 2021
6.10 Switching Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15V(1), 1-µF capacitor from VDDA and
VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
|CMH|
High-level common-mode transient
immunity
INA and INB both are tied to VCCI;
VCM=1500 V; (See CMTI Testing.)
100
|CML|
Low-level common-mode transient
immunity
INA and INB both are tied to GND;
VCM=1500 V; (See CMTI Testing.)
100
(1)
TYP
MAX
UNIT
V/ns
VDDA=VDDB = 12 V is used for the test condition of 5 V and 8V UVLO, and VDDA=VDDB=15 V is used for 12-V UVLO.
6.11 Insulation Characteristics Curves
1.E+11
1.E+10
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (
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