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UCC24610
SLUSA87C – AUGUST 2010 – REVISED OCTOBER 2015
UCC24610 GREEN Rectifier™ Controller Device
1 Features
3 Description
•
This GREEN Rectifier™ controller
performance controller and driver for
logic-level N-channel MOSFET power
for
low-voltage
secondary-side
rectification.
1
•
•
•
•
•
•
•
•
•
•
•
•
Secondary-Side Controller Optimized for 5-V
Systems
Up to 600-kHz Operating Frequency
VDS MOSFET-Sensing
1.6-Ω Sink, 2.0-Ω Source Gate-Drive Impedances
Micro-Power Sleep Current for 90+ Designs
Automatic Light-Load Management
Synchronous Wake-Up From Sleep and LightLoad Modes
Protection Features on Programming Inputs
SYNC Input for CCM Operation
20-ns Typical Turnoff Propagation Delay
Improved Efficiency and Design Flexibility Over
Traditional Diode Solution
May Be Biased Directly From 5-V Output
Minimal Component Count
2 Applications
•
•
•
•
AC-to-DC 5-V Adapters
5-V Bias Supplies
Low Voltage Rectification Circuits
Flyback and LLC Converters
is a highstandard and
devices used
synchronous
The combination of controller and MOSFET emulates
a near-ideal diode rectifier. This solution not only
directly reduces power dissipation of the rectifier but
also indirectly reduces primary-side losses as well,
due to compounding of efficiency gains.
Using
drain-to-source
voltage
sensing,
the
UCC24610 is ideal for Flyback and LLC-resonant
power supplies but can also be used with other power
architectures. The UCC24610 is optimized for output
voltages from 4.5 V to 5.5 V, and is suitable for use
with lower and higher output voltages as well.
The UCC24610 offers a programmable falsetriggering
filter,
a
programmable
timer
to
automatically switch to light-load mode at light load,
and a SYNC input for optional use in continuous
conduction mode (CCM) systems. Protection features
on TON and EN/TOFF pins prevent run-away on-time
due to open-circuit or short-circuit fault conditions.
This device is available in an 8-pin SOIC package
and an 8-pin, 3.0-mm × 3.0-mm SON package with
an exposed thermal pad.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC24610DRB
SON (8)
3.00 mm × 3.00 mm
UCC24610D
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Flyback Topology
–
LLC-Resonant Half Bridge
+
5V
Out
8
5
7
VD
GATE
VS
3
2
6
TON EN/TOFF GND
UCC24610
1
SYNC
VCC
4
8
5
7
3
2
6
5V
VBULK
VD
GATE
VS
TON EN/TOFF GND
5V
UCC24610
1
SYNC
VCC
4
4
UDG-10079
1
VCC
SYNC
12 V
OUT
UCC24610
VD
GATE
VS
8
5
7
TON EN/TOFF GND
3
2
6
UDG-10096
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC24610
SLUSA87C – AUGUST 2010 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2010) to Revision C
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
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SLUSA87C – AUGUST 2010 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
SYNC
1
8
VD
EN/TOFF
2
7
VS
TON
3
6
GND
VCC
4
5
GATE
DRB Package
8-Pin SON With Exposed Thermal Pad
Top View
SYNC
1
8
VD
EN/TOFF
2
7
VS
TON
3
6
GND
VCC
4
5
GATE
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Pin Functions
PIN
NAME
NO.
EN/TOFF
2
I/O
DESCRIPTION
I
EN/TOFF (combined enable function and programmable off-time timer), when VCC falls below the
VCC(off) threshold, the UCC24610 is in UVLO mode, the EN/TOFF input is internally connected to
GND through a 10-kΩ resistance and the internal current source is turned off. When VCC exceeds
the VCC(on) threshold, the 10-kΩ resistance is removed and the current source is turned on.
Thereafter, when EN/TOFF exceeds VEN(on), the UCC24610 is in run mode and when EN/TOFF falls
below VEN(off), the UCC24610 is in sleep mode. The voltage level on EN/TOFF also programs the
minimum off-time (TOFF) for the controlled MOSFET. EN/TOFF is internally driven by a two-level
current source, so the voltage level on EN/TOFF can be set by connecting a resistor from EN/TOFF
to GND. The EN/TOFF current source initially drives twice as much current (IEN-START) to achieve the
enable threshold voltage VEN(on), and then drops to the normal run mode level (IEN-ON) to program the
TOFF time. Alternatively, the desired EN/TOFF voltage may be forced using an external source. The
TOFF time is programmed to suppress GATE output for a desired duration to avoid possible false
retriggering from resonant ringing or noise after turnoff. The TOFF timer is triggered when VD voltage
exceeds 1.5 V after GATE transitions from high to low.
GATE
5
O
GATE (controlled MOSFET gate drive), connect GATE to the gate of the controlled MOSFET through
a small series resistor using short PC board tracks to achieve optimal switching performance. The
GATE output can achieve >1-A peak source current when High and >2-A peak sink current when Low
into a large N-channel power MOSFET.
In sleep mode and UVLO, GATE impedance to GND is about 1.6 Ω.
GATE impedance to GND crests about 80 Ω, when VCC ≈ 1.1 V.
GND
6
–
GND (combined analog and power ground), this ground input is the reference potential for the GATE
driver, the UVLO comparator, the EN/TOFF comparator, the EN/TOFF timer, and the TON timer.
Connect a 0.1-µF or larger ceramic bypass capacitor from the VCC pin to the GND pin through very
short PC-board tracks.
I
SYNC (gate turnoff synchronization), a falling edge on SYNC immediately forces GATE low, turning
off the controlled MOSFET asynchronous to the voltage on the drain and source, and regardless of
the state of the TON timer. When a power converter is operated in continuous conduction mode
(CCM), it is necessary to turn off the controlled MOSFET under command of the switching converter.
Connect SYNC to a control signal on the primary side of the converter using a high-voltage isolation
capacitor or transformer, or other suitable coupling means. A continuous low level on the SYNC input
causes GATE to be driven low for the same duration.
I
TON (programmable on-time timer), program the minimum on time with a resistor from TON to GND.
When the controlled MOSFET gate is turned on, some ringing noise is generated. The minimum ontime timer blanks the VD-VS comparator, keeping the controlled MOSFET on for at least the
programmed minimum time. This time also determines the light-load shut-down point. If VD-VS falls
below the –5-mV threshold before TON time expires, the controller transitions into light-load mode on
the next switching cycle. When VD-VS falls below the –5-mV threshold after TON expires, the device
resumes run-mode operation on the next switching cycle.
I
VCC (positive power input), connect a DC power voltage to VCC. Bypass VCC to GND with a 0.1-µF
or larger ceramic capacitor using short PC board tracks. VCC supplies power to all circuits in the
UCC24610. Under-Voltage Lockout (UVLO) comparators prevent operation until VCC rises above
VCC(on). VCC can be used to safely turn off the UCC24610 by pulling VCC below VCC(off). In the event
that VCC drops below VCC(off), GATE immediately falls Low and EN/TOFF is internally connected to
GND with a 10-kΩ resistance.
SYNC
1
TON
3
VCC
4
VD
8
I
VD (drain-sense voltage), connect this pin as close as possible to the controlled MOSFET drain pad
through a short PC board track, to minimize the effects of trace inductance on VD. VD must be >1.5 V
and the TOFF timer must be expired before the device may be armed to allow the controlled
MOSFET to be turned on the next switching cycle. Once armed, the controlled MOSFET is turned on
(GATE goes High) when VD falls more than –150 mV below VS. At that threshold, the GATE output
goes High and the TON timer is triggered. GATE remains High at least as long as the programmed
TON time has not expired, unless a pulse at the SYNC input is detected. After TON has expired, the
GATE output is turned off when VD-VS voltage decreases to –5 mV. If VD-VS decreases to –5 mV
before TON expires, the controller enters light-load mode and the GATE pulse for the next switching
cycle is suppressed. When the VD voltage increases to 1.5 V, the TOFF timer is triggered and the
GATE output is prevented from turning on during the TOFF interval.
VS
7
I
VS (source-sense voltage), connect this pin as close as possible to the controlled MOSFET source
pad through a short PC-board track, to minimize the effects of trace inductance on VS.
–
Thermal Pad on SON package only, the exposed thermal pad on the bottom of the SON package
enhances the thermal performance of the device, and is intended to be soldered to a heat-dissipating
pad on the PCB. This pad should be connected to the GND pin, or may be left floating (unconnected
to any network). It is internally connected to GND through an indeterminate impedance and so may
not be used to carry current.
Thermal Pad
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VCC
EN/TOFF
Input voltage
(2)
(3)
MIN
MAX
UNIT
–0.3
6.5
V
–0.3
VCC
V
TON (4)
–0.3
VCC
V
VD for IVD ≤ –10 mA
–1.0
50
V
VS for IVS ≤ –10 mA
–1.0
0.5
V
Input current, peak
SYNC (5) pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1%
±100
mA
Output current, peak
GATE (6) pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1%
±3
A
TJ
Operating junction temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
(6)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input voltages more negative than indicated may exist on any listed pin without excess stress or damage to the device if the pin’s input
current magnitude is limited to less than -10mA. See separate ratings for SYNC and GATE pins.
EN/TOFF can be driven by a voltage within the specified absolute maximum range or connected to a resistor to ground. Either method
will program maximum off-time. When programmed by a resistor to GND, the voltage at the EN/TOFF terminal is internally limited to
1 mA
1.31
1.40
1.49
V
VENOFF
EN/TOFF turnoff threshold, falling
EN/TOFF driven, ICC < 200 µA
0.74
0.80
0.86
V
IEN-START
EN/TOFF input current, disabled
EN/TOFF = 1.3 V, rising from zero
–21.5
–20.0
–18.5
μA
IEN-ON
EN/TOFF input current, enabled
EN/TOFF = 2 V
–10.7
–10.0
–9.3
μA
UNDERVOLTAGE LOCKOUT (UVLO)
VCCON
VCC turnon threshold
Turnon detected by VEN > 1.0 V
4.15
4.40
4.65
V
VCCOFF
VCC turnoff threshold
Turnoff detected by VEN < 0.5 V
3.96
4.20
4.44
V
VCCHYST
UVLO hysteresis
VCCHYST = VCCON – VCCOFF
0.15
0.20
0.25
V
MOSFET VOLTAGE SENSING
VTHARM
GATE rearming threshold
VD to GND, rising
1.3
1.5
1.7
V
VTHON
GATE turnon threshold
(VD – VS) falling, VS = 0 V
–220
–150
–80
mV
VTHOFF
GATE turnoff threshold
(VD – VS) rising, VS = 0 V
–8
IDH
VD input bias current, high
VD = 50 V, VS = 0 V
IDL
VD input bias current, low
VD = -0.15 V, VS = 0 V
IS
VS input bias current
VD = 0 V, VS = 0 V
–5
–2
mV
0.05
2.00
μA
–250
–150
–50
μA
–250
–150
–50
μA
GATE DRIVER
rGUP
GATE pullup resistance, enabled
IGATE = –100 mA
2.0
3.6
Ω
rGDN
GATE pulldown resistance, enabled
IGATE = 100 mA
1.6
2.5
Ω
VOHG
GATE output high voltage
IGATE = –100 mA
VOLG
GATE output low voltage
IGATE = 100 mA
0.16
0.25
V
VOLGUV
GATE output low voltage, UV
IGATE = 25 mA, VCC = 0 V
0.70
0.90
V
VOLGOFF
GATE output low voltage, disabled
IGATE = 25 mA, VEN = 0 V
0.04
0.10
V
VCC – 2.4
VCC – 2.0
VCC – 1.6
V
1.6
2.0
2.4
kΩ
4.64
4.80
V
SYNCHRONIZATION
VTHSYNC
SYNC falling threshold
GATE output transitions from high to
low
rSYNC
SYNC pullup resistance
Internal resistance from SYNC to
VCC
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6.6 Timing Requirements
At VCC = 5 VDC, CGATE = 0 pF, RTON = 200 kΩ, REN/TOFF = 100 kΩ, −40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to
GND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at
TJ = +25°C.
MIN
NOM
MAX
UNIT
MOSFET VOLTAGE SENSING
tDON
GATE turnon propagation delay, from VTHON to GATE > 1 V
44
70
ns
tDOFF
GATE turnoff propagation delay, from VTHOFF to GATE < 4 V
16
35
ns
MINIMUM ON-TIME SETTING
tONLR
Minimum on-time, low resistance, RTON = 16.5 kΩ
0.17
0.25
0.33
μs
tONHR
Minimum on-time, high resistance, RTON = 200 kΩ
2.2
3.0
3.8
μs
MINIMUM OFF-TIME SETTING
tOFFLR
Minimum off-time, low resistance, REN/TOFF = 100 kΩ
4.94
7.80
9.86
μs
tOFFHR
Minimum off-time, high resistance, REN/TOFF = 261 kΩ
0.55
1.37
2.30
μs
tOFFLV
Minimum off-time, low voltage, EN/TOFF = 1.0 V
4.94
7.80
9.86
μs
tOFFHV
Minimum off-time, high voltage, EN/TOFF = 2.61 V
0.85
1.37
2.10
μs
tOFFOV
Minimum off-time, over voltage, 3 V < VEN < VCC
0.48
0.65
0.82
μs
GATE DRIVER
tfGATE
GATE rise time, from 1 V to 4 V, CGATE = 3300 pF
14
30
ns
trGATE
GATE fall time, from 4 V to 1 V, CGATE = 3300 pF
9
25
ns
tDIS
Disable delay, from EN falling to GATE falling
100
150
ns
20
60
ns
50
SYNCHRONIZATION
tSDLY
8
SYNC propagation delay, from SYNC falling to GATE falling 10%
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6.7 Typical Characteristics
4.6
10,000
No Gate Switching
EN > 1.6
VVCC - Threshold Voltage - V
IVCC - Bias Supply Current - mA
4.5
1,000
EN < 0.7
100
10
VCCON
4.4
4.3
VCCOFF
4.2
1
4.1
0
4.0
0
1
3
2
4
5
6
7
-50
-25
0
VCC - Bias Supply Voltage - V
Figure 1. Bias Supply Current vs. Bias Supply Voltage
75
100
125
150
60
EN > 1.6 V
CGATE = 10 nF
50
2000
IVCC - Supply Current - mA
IVCC - Bias Supply Current - mA
50
Figure 2. UVLO Threshold Voltage vs. Temperature
2500
VCC = 5.5 V, No Gate Switching
1500
1000
500
CGATE = 4.7 nF
CGATE = 3.3 nF
40
CGATE = 1 nF
CGATE = 0 nF
30
20
10
EN < 0.7 V
0
0
-50
-25
0
25
50
75
100
125
150
0
400
200
600
800
1000
TJ - Temperature - °C
fSW - Switching Frequency - kHz
Figure 3. Bias Supply Current vs. Temperature
Figure 4. Supply Current vs. Switching Frequency
1.6
-9.3
VENON
EN > 1.6 V
1.4
VEN - Threshold Voltage - V
-9.5
IEN-ON - Enable Current - mA
25
TJ - Temperature - °C
-9.7
-9.9
-10.1
-10.3
-10.5
1.2
1.0
VENOFF
0.8
0.6
0.4
0.2
-10.7
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 5. Enable Current vs. Temperature
Figure 6. Enable Threshold Voltage vs. Temperature
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Typical Characteristics (continued)
30
3.3
tSDLY - SYNC Propagation Delay Time - ns
VTHSYNC - SYNC Threshold Voltage - V
3.4
3.2
3.1
3.0
2.9
2.8
2.7
2.6
25
20
15
10
5
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 7. SYNC Threshold Voltage vs. Temperature
Figure 8. SYNC Propagation Delay Time vs. Temperature
-2
-0.10
VS = +0.1 V
-0.11
VS = -0.1 V
-0.12
-4
VTHON - Voltage - V
VTHOFF - Voltage - mV
-3
-5
-6
VS = 0 V
-0.13
-0.14
-0.15
-0.16
-0.17
-0.18
-7
-0.19
-8
-0.20
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 9. VDS Gate-Off Threshold Voltages vs. Temperature
Figure 10. VDS Gate-On Threshold Voltage vs. Temperature
60
20
tDON
GATE Rise and Fall Time - ns
GATE Propagation Delay Time - ns
18
50
40
30
20
tDOFF
16
trGATE
14
12
tfGATE
10
8
6
4
10
2
0
0
-50
10
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 11. Gate Propagation Delay Time vs. Temperature
Figure 12. Gate Rise And Fall Time vs. Temperature
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5.0
10
4.5
9
4.0
8
TOFF - Minimum OFF Time - ms
TON - Minimum ON Time - ms
Typical Characteristics (continued)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
7
6
5
4
3
2
1
0
0
0
0.10
0.05
0.15
0.20
0.25
0.30
0
0.10
0.05
0.15
0.20
0.25
0.30
0.35
RTON - TON Resistance - MW
REN/TOFF - TOFF Resistance - MW
Figure 13. Minimum On Time vs. tON Resistance
Figure 14. Minimum Off Time vs. tOFF Resistance
8
100
VS = 0 V
TOFF, REN/TOFF = 100 kW
7
0
IVD - Bias Current - mA
TON and TOFF - Time - ms
6
5
4
TON, RTON = 200 kW
3
2
TOFF, REN/TOFF = 261 kW
-100
-200
-300
1
TON, RTON = 16.5 kW
-400
0
-50
-25
0
25
50
75
100
125
-1
150
0
1
2
3
4
5
VD - Drain Sense Voltage - V
TJ - Temperature - °C
Figure 15. tON and tOFF Time vs. Temperature
Figure 16. VD Bias Current vs. Drain Sense Voltage
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7 Detailed Description
7.1 Overview
The UCC24610 synchronous rectifier (SR) controller uses drain-to-source voltage sensing to determine the SR
MOSFET conduction interval. The SR MOSFET is turned on when VDS exceeds –150 mV, and is turned off when
VDS diminishes to –5 mV or the SYNC input is triggered for CCM operation. Programmable minimum on-time and
off-time helps avoid false turnon and turnoff responses to switch voltage ringing and noise. To reduce light-load
switching losses, automatic light-load mode disables the GATE pulses when the actual on-time based on VDS
becomes less than the programmed minimum on-time. When the load increases such that the conduction time
exceeds the programmed minimum on-time, the controller resumes normal SR operation.
7.2 Functional Block Diagram
VCC
4
Sleep-Mode & Wake-Up
Synchronization
10 μA
UVLO
10 μA
EN/TOFF
2
+
1.4 V/0.8 V
VD
8
+
Q
...
S
R
5 mV
REFs
Minimum
Off-Time
1.5 V
S
5
Q
GATE
+
150 mV
R
VS
7
TON
3
R
+
Minimum
On-Time
Light-Load
Detect
+
VCC-2 V
2 kW
12
Fault
Protection
VCC
VCC
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1
6
SYNC
GND
UDG-10078
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7.3 Feature Description
7.3.1 Normal Operation
The UCC24610 GREEN rectifier synchronous-rectifier (SR) controller powers up into UVLO mode as VCC
increases from 0 V. Enable current (IEN) from the EN/TOFF pin is inhibited until VCC exceeds the VCC(on)
threshold, and remains active as long as VCC exceeds the VCC(off) threshold. The voltage on the EN/TOFF pin
determines whether the controller is enabled or not. The controller operates in the normal run mode when the
enable voltage (VEN) exceeds the enable threshold VEN(on) and remains enabled as long as VEN exceeds the
VEN(off) threshold.
After the controller is enabled, VEN programs the minimum off time inversely proportional to the voltage (see
Enabling and TOFF Programming). The two-state enable current allows a lower-value resistance for REN(off)
(necessary to program longer off time) to still generate sufficient voltage to exceed VEN(on) at start-up. A simple
resistor from EN/TOFF to GND generates VEN based on the level of IEN current flowing through it (see Figure 17).
Alternatively, VEN may be driven by an external voltage source provided this voltage exceeds VEN(on) for at least
100 ns before settling to its final programming level.
VCC, VEN
(V)
VCC
VCC Recommended Operating Range
5
VCCON
VCCOFF
4
3
EN/TOFF pin under
external control
2
VENON
~100 ns
VEN
1
VENOFF
(REN/TOFF = 100 kΩ)
0
t
IEN
(μA)
20
10
IEN-START
IEN-ON
~REN/TOFFCPIN
0
V10094
t
Figure 17. Behavior of IEN and VEN as VCC Varies (REN/TOFF = 100 kΩ)
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Feature Description (continued)
The UCC24610 SR controller determines the conduction time of the SR-MOSFET by comparing the drain-tosource voltage of the MOSFET against a turnon threshold and a turnoff threshold. The GATE output is driven
high when VDS of the MOSFET exceeds VTH(on) and is driven low when VDS decreases below VTH(off) as illustrated
in Figure 18.
(A), (V)
VDS
ISEC
VTHARM
VTHOFF
VTHON
(t)
VGATE
4V
4V
1V
1V
trGATE
tDON
tDOFF
tfGATE
V10095
Figure 18. GATE Output With Respect to VDS
NOTE
Because of finite propagation and rise times, the body diode of the SR-MOSFET may
conduct briefly after VTH(on) has been exceeded. Also, the body-diode conducts the
residual secondary current after VTH(off) has been crossed. A waveform similar to that of
VDS depicted in Figure 18 can be observed during SR operation in a simple flyback circuit.
14
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Feature Description (continued)
However, actual in-circuit waveforms are rarely as clean as shown in Figure 18. Instead, parasitic inductances
and capacitances set up resonant ringing at various inflection points in the waveforms. The UCC24610 has
control timing and programming options that help avoid interference from such ringing with proper operation.
Figure 19 shows more realistic waveforms and the internal control timing which accommodates them. The
waveforms affecting the SR-MOSFET in a typical flyback circuit are shown.
(A), (V)
Turn-on Ringing
ISEC
(t)
VDS
Resonant Ringing
GATE Output
TON Blanking
TOFF Blanking
ARMED
VDS < VTHON Detection
VDS > VTHOFF Detection
VDS > VTHARM Detection
V10093
Figure 19. Internal Signal Timing With Respect to Realistic DCM Waveforms
Minimum on-time TON is programmed with a resistor from TON, (pin 3) to GND to blank the response of the
turnoff detection circuit to prevent GATE from being turned off from spurious crossings of VTH(off) due to noise
and ringing. TON is triggered by the GATE turning on. Refer to TON Programming for details.
Minimum off-time TOFF is programmed with a resistor from pin 2 to GND to blank the response of the turnon
detection circuit to prevent GATE from being turned-on again from spurious crossings of VTH(on) due to excessive
COSS resonant ringing. TOFF is triggered by VDS crossing VTHARM after the GATE turns off. Refer to the Enabling
and TOFF Programming for details
The GATE output may only turn on when the controller has been armed for the switching cycle. The controller is
armed for each successive SR cycle only after TOFF expires. In high-frequency applications, an excessively long
TOFF may interfere with timely turn-on of GATE in the next switching cycle. GATE turn on will be delayed if
TOFF from the previous cycle has not yet expired.
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Feature Description (continued)
7.3.2 Light-Load Operation
During normal operation, the synchronous rectifier conduction time is longer than the programmed minimum ontime. If load current decreases enough that the SR conduction time becomes shorter than the programmed
minimum on-time, a light-load condition is detected. The light-load latch is set and the next GATE output pulse is
blanked, so only the body diode of the controlled MOSFET conducts. This comparison between SR conduction
time and minimum on time occurs every switching cycle, regardless of whether the GATE output pulse is enabled
or blanked. When load current increases enough that the body-diode conduction time becomes longer than the
programmed minimum on time, the light-load latch is cleared and the next GATE output pulse is enabled and the
controlled MOSFET resumes SR operation.
Figure 20 depicts the progression into light-load mode for a DCM flyback application as the load decreases, while
Figure 21 depicts the reverse progression back to run mode.
(A), (V)
VDS
VDS
VDS
VDS
ISEC
ISEC
ISEC
ISEC
(t)
VTHOFF
GATE Output
TON Blanking
Light-Load Mode
V10092
Figure 20. Decreasing Load Current Progression Leads to Light-Load-Mode Operation
(A), (V)
VDS
VDS
ISEC
ISEC
VDS
VDS
ISEC
ISEC
(t)
VTHOFF
GATE Output
TON Blanking
Light-Load Mode
V10091
Figure 21. Increasing Load Current Progression Returns to Run-Mode Operation
16
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7.4 Device Functional Modes
7.4.1 UVLO Mode
When the VCC voltage to the device has not yet reached the VCC(on) threshold, or has fallen below the UVLO
threshold VCC(off), the device operates in the low-power UVLO mode. In this mode, most internal functions are
disabled and ICC current is typically much less than 100 µA. While in this mode, the EN current source is shut
off, an internal 10-kΩ resistance is applied from the EN/TOFF pin to GND, the voltage on EN/TOFF is irrelevant,
and the GATE output is driven low continuously for all VCC > 1.2 V. The device passes out of UVLO mode when
VCC increases above the VCC(on) threshold. UVLO mode is very similar to Sleep mode, except VCC current is at
ICC(start) level.
7.4.2 Sleep Mode
Sleep mode is a low-power operating mode similar to UVLO mode, except that this mode is entered under
external control by forcing VEN below the VEN(off) threshold. Sleep mode may be used to reduce device operating
losses to less than 1 mW. VCC current reduces to ICC(stby) level. External control overrides any internal timing
conditions, and immediately forces the GATE output low and enters Sleep mode. Many internal circuits are
turned off to reduce power consumption. When VEN is restored to above the VEN(on) threshold, the device exits
Sleep mode synchronously into Light-load mode after a delay of approximately 25 µs to allow re-powered internal
circuits to settle.
7.4.3 Run Mode
Run mode is the normal operating mode of the controller when not in UVLO mode, sleep mode, or light-load
mode. In this mode, VCC current is higher because all internal control and timing functions are operating and the
GATE output is driving the controlled MOSFET for synchronous rectification. VCC current is the sum of ICC(on)
plus the average current necessary to drive the load on the GATE output. GATE output duty-cycle is dependent
upon system line and load conditions, programmed TON and TOFF times, and SYNC-pulse timing (if applicable).
7.4.4 Light-Load Mode
Light-load mode is a low-power operating mode similar to sleep mode, except that this mode is entered
automatically based on internal timing conditions. Light-load mode automatically reduces switching losses under
light-load conditions by suppressing GATE output pulses whenever the detected synchronous conduction time is
less than the programmed minimum on-time (TON). VCC current reduces to ICC(on) level. While in light-load
mode, the MOSFET body-diode conduction time is still continuously monitored. When this time is detected to
once again exceed TON, the device resumes run mode on the next switching cycle.
7.4.5 Fault Mode and Other Protections
Fault mode is a self-protection operating mode of the controller when certain types of single-fault conditions are
detected on certain pins. In this mode, the device enters a shut-down state (not sleep mode) and drives the
GATE output low. Specifically, Fault mode is entered if RTON > 301 kΩ or if RTON < 8.7 kΩ. Fault mode prevents
the conditions of excessive or indefinite on-time (such as from an open-pin) and of excessive TON current (such
as from a shorted-pin).
Similar protection is provided for the EN/TOFF pin. While not specifically detected as faults, if this pin becomes
open-circuited TOFF defaults to a minimum value of ≈0.65 µs, and if shorted-to-GND the device enters sleep
mode. Additionally, if the SYNC input is continuously held below its trigger threshold voltage, the GATE output is
held low for the entire duration that SYNC remains in that condition.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC24610 synchronous rectifier controller is optimized for 5-V only applications, but may be used for other
applications (such as LLC converters) where device stresses (such as VD voltage) are not exceeded, and a 5-V
VCC source is available.
The effects of lead inductance on the VDS-sensing turnoff threshold varies with the SR MOSFET package.
Compact packages such as SON, QFN, and similar packages have virtually no significant lead inductance in the
drain connection, very little in the source, and nominal bond-wire inductance in the gate path. Slightly larger
SOIC-derived packages may have 2-nH to 3-nH inductance in the source path. TO-220 and larger packages
have significant lead inductances, which can adversely affect the turnoff point of the SR MOSFET unless the
sensing is compensated for inductance. The falling dI/dt of the current through the SR lead inductance reduces
the sensed VDS voltage and prematurely triggers turnoff. Resistors in the VD and VS sense paths can be used to
compensate for this effect.
8.2 Typical Application
The following application information is applied to the UCC24610 Evaluation Module (EVM), which delivers 5 A at
5 V using an SR MOSFET in a TO-220 package. In this DCM flyback-topology application example, the SYNC
signal is not used. Performance data relevant to the operation of the UCC24610 SR controller are included in this
section for application reference. Refer to Using the UCC24610EVM-563 User's Guide (SLUU434) for additional
details on the overall performance of the EVM. The schematic diagram for the EVM, Figure 22, is provided as an
example of a typical application for the UCC24610.
+
+
+
+
+
+
Figure 22. UCC24610 Typical Application Example
18
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Typical Application (continued)
8.2.1 Design Requirements
Table 1. UCC24610 EVM Design Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
INPUT CHARACTERISTICS
VIN
Input voltage
IIN
Input current
VUVLO
Brown out
85
265
VRMS
VIN = 115 VRMS, IOUT = 5 A
0.6
ARMS
VIN = 115 VRMS, IOUT = 0 A
0.03
ARMS
69
VRMS
IOUT = 5 A
OUTPUT CHARACTERISTICS
VOUT
Output voltage, average
VIN = 85 VRMS to 265 VRMS, IOUT = 0 A to 5 A
VRIPPLE
Output voltage, ripple
VIN = 115 VRMS, IOUT = 5 A
IOUT
Output current
VIN = 85 VRMS to 265 VRMS
IOCP
Output overcurrent inception
point
VIN = 115 VRMS
VOVP
Output overvoltage protection
point
Transient response voltage
over-shoot
4.5
5
5.6
200
0
V
mVpp
5
A
7
A
IOUT = 0 A to 5 A
6.5
V
VIN = 115 VRMS, IOUT = 0 A to 5 A
600
mV
SYSTEM CHARACTERISTICS
fSW
Switching frequency
ηPEAK
Peak efficiency
ηAVG
Average efficiency
No-load power consumption
Operating temperature range
26.3
140.4
VIN = 115 VRMS, IOUT = 1.75 A
82.7%
VIN = 115 VRMS, IOUT = 25%, 50%, 75%, 100% of
rated output current
82.3%
VIN = 230 VRMS, IOUT = 25%, 50%, 75%, 100% of
rated output current
82.3%
kHz
VIN = 115 VRMS, IOUT = 0 A
181
mW
VIN = 230 VRMS, IOUT = 0 A
368
mW
25
°C
VIN = 85 VRMS to 265 VRMS, IOUT = 0 A to 5 A
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8.2.2 Detailed Design Procedure
8.2.2.1 VD and VS Detection
VD and VS are differential inputs used to sense the voltage across the SR-MOSFET to determine when to turn
on and off the GATE output. When the GATE is off, the controller will not drive the GATE on until VD has
exceeded 1.5 V at least once and TOFF has expired. Once these two conditions are met, the controller is armed
to allow the GATE to turn on the next time the drain voltage falls 150 mV below the source voltage (VD – VS =
–150 mV). While the GATE is off, the SR-MOSFET may be blocking reverse current, or forward current may be
building up in the MOSFET body diode. Normally this body-diode current would generate about 700 mV forward
voltage drop (–700 mVDS), but when –150 mV is detected the GATE is turned on to enhance the MOSFET into a
synchronous rectifier. The GATE stays on for at least the minimum on time TON or longer until the SR-MOSFET
current diminishes to near zero. When the current reduces sufficiently such that the VDS voltage drop is only
–5 mV, the GATE output is turned off. (It can be seen that the MOSFET RDS(on) determines the current level at
which the GATE is turned off, which then further factors into determining the light-load mode inception point.) At
the same time, the controller is disarmed to prevent spurious GATE output. Because the MOSFET current is not
yet zero at GATE turn off, the VDS will briefly increase back up to the body-diode drop, however the additional
power loss is very small. The disarmed state of the controller prevents repeated turn on of the GATE (even
though VDS ≤150 mV again). Once the current does decrease to zero, the drain voltage climbs past the 1.5-V
threshold, at which point the minimum off-time interval TOFF is triggered. Once VDS has exceeded 1.5 V and
TOFF has expired, the GATE circuit is rearmed to respond to the next turnon condition.
Because the VD and VS inputs are connected across the SR-MOSFET body diode by way of its package leads,
the high secondary-side dI/dt through the lead inductances can impress excessive negative voltage on the VD
pin. This negative voltage can disrupt normal controller operation and prevent the device from switching. This
problem can be avoided by limiting the current drawn out of the VD pin to less than 100 mA. A resistor placed in
series between VD and the SR-MOSFET drain can be sized to provide the proper current limiting.
This resistor value is calculated by Equation 1.
R VD
dISEC
æ
ö
ç LPKG dt - 0.3 V ÷
ø
³è
0.1A
where
•
•
LPKG is the total package inductance between the drain and source pads of the SR-MOSFET when mounted
on the PCB,
dISEC/dt is the rate of rise of the secondary current after the primary-side switch turns off.
(1)
Include any stray trace inductance if the device GND pin is not connected directly to the SR-MOSFET source
pad.
The bias current of the VD pin through RVD (if any) generates a small offset voltage that can cause an apparent
shift in the SR-MOSFET turnoff threshold, leading to earlier turn off than desired, depending on the value of RVD.
To counter this offset voltage, a resistor of equal value can be placed in series with the VS pin to balance the
VD–VS comparator inputs (RVS = RVD).
Larger MOSFET packages such as TO-220 and TO-247 generally have significant internal inductances (on the
order of 10 nH ≈ 20 nH), and are used in higher-power applications where dI/dt can be quite high. On the other
hand, low-power applications using smaller packages such as QFN style and even DPAK style or equivalent
MOSFETs can have a sufficiently low L × dI/dt product such that RVD and RVS may not be necessary. Refer to
the MOSFET datasheet or consult with the manufacturer to determine the total inductance for the specific
MOSFET being considered for a synchronous-rectifier application.
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8.2.2.2 Enabling and TOFF Programming
The controller must be out of UVLO mode, or the internal current source on EN/TOFF pin is shut off and the pin
is pulled low with an internal 10-kΩ resistor. Before the device is in the Enabled state, the current source on
EN/TOFF delivers 20 μA. Prudent design practice indicates that a minimum REN/TOFF value of 93 kΩ is necessary
to ensure the pin voltage exceeds the disable threshold. After being Enabled, the Enabled state is latched and
the source current reduces to 10 μA. This current level establishes the voltage that determines the TOFF time,
as shown in Equation 2 through Equation 5.
When both the VCC and EN/TOFF conditions are met to enable the device, an internal power-up sequence
ensures that the controller starts the SR-MOSFET synchronously with the system conduction conditions. This
avoids turnon of the SR-MOSFET into an inappropriate system state. After a ≈25-μs delay to allow internal
references to stabilize, SR operation commences in light-load mode and the load condition is monitored at the
first complete switching cycle after the delay to determine the next operating mode.
Because VDS of the SR-MOSFET may ring above 1.5 V and back below –150 mV one or more times (due to
circuit parasitic elements), TOFF time should be programmed to block GATE re-arming for the duration of this
ringing. In a system, the duration of this ringing may be unknown until actual prototypes are operational and
observable, so a longer TOFF time may be initially programmed and the final value adjusted after system
evaluation and optimization.
Nominal TOFF off time is programmed by Equation 2 through Equation 5, where TOFF is in μs and REN/TOFF is in
MΩ.
æ
ö
æ ms ö
TOFF(ms) = ç 11(ms) - 39 ç
REN / TOFF (MW) ÷ + 0.65(ms)(min)
÷
è MW ø
è
ø
(2)
valid for:
0.1 £ REN / TOFF (MW) £ 0.282
Conversely,
REN / TOFF (MW) =
(3)
(11(ms) + 0.65(ms)(min) - TOFF(ms))
æ ms ö
39 ç
÷
è MW ø
(4)
valid for:
0.65 £ TOFF(ms) £ 7.75
(5)
For any REN/TOFF > 282 kΩ, TOFF = 0.65 μs.
For any 70 kΩ < REN/TOFF < 80 kΩ, VEN toggles rapidly between 1.4 V and 0.8 V and the device remains
disabled. In this situation, average ICC is approximately half of the normal run-mode current, ICC(on).
For any REN/TOFF < 70 kΩ, VEN is < 1.4 V and the device is disabled, operating in sleep mode.
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8.2.2.3 TON Programming
The voltage on this pin is internally regulated to 2 V, and an external resistor to GND sets a current which
programs the minimum on time TON. If a noise-filter capacitor is deemed to be necessary on this pin, do not
exceed 100 pF to avoid instability of the 2-V regulator.
Because VDS of the SR-MOSFET may ring above –5 mV one or more times immediately after turn on (due to
circuit parasitic elements) TON time should be programmed to block GATE turn off for the duration of this
spurious ringing. In a system, the duration of this ringing may be unknown until actual prototypes are operational
and observable, so a longer TON time may be initially programmed and the final value adjusted after system
evaluation and optimization.
Nominal TON minimum on time is programmed by Equation 6 through Equation 9, where TON is in µs and RTON
is in MΩ.
æ ms ö
TON (ms ) = 15 ç
÷ RTON (MW )
è MW ø
(6)
Valid for:
0.010 £ RTON (MW) £ 0.301
(7)
Conversely,
TON(ms)
æ ms ö
15 ç
÷
è MW ø
(8)
0.15 £ TON(ms) £ 4.5
(9)
RTON (MW) =
Valid for:
For resistance values of RTON outside of the previous range given, the device may enter a fault-protection mode
as described in Fault Mode and Other Protections.
8.2.2.4 GATE Drive and RGATE Considerations
The GATE output driver is capable of sourcing >1-A peak current into the SR-MOSFET gate, and sinking >2 A
out of it. Standard low-inductance, low-loop-area design techniques should be employed to minimize stray
inductance, which slows the MOSFET turn on and increases gate-drive ringing.
A series resistance RGATE from the GATE output to the MOSFET gate is used to damp this ringing, and its value
is chosen based on the standard critical damping formula for a series-LCR resonant tank, see Equation 10.
RGATE ³ 2
Lg
Ciss
- rg
where
•
•
•
Lg is the total series gate-loop inductance,
Ciss is the total effective input capacitance of the MOSFET,
rg is the internal gate resistance of the MOSFET.
(10)
NOTE
The total series resistance in the gate-drive path may also limit the peak GATE currents
obtainable below the rated capabilities of the device’s GATE output driver stage.
22
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8.2.2.5 VCC Range and Bypassing Considerations
With a normal operating range of 4.5 V to 5.5 V, the device is well suited for 5-V nominal output applications and
can easily accommodate ±10% transient VCC excursions due to system line and load disturbances. When the
average VCC voltage approaches the VCC(off) threshold (UVLO), system ripple and noise on VCC may cross that
threshold and shut down the controller unless adequate decoupling is provided from VCC to GND at the
controller pins.
High peak gate-drive currents during the GATE turnon transition also require sufficient local capacitive bypassing
of the VCC pin to GND. For smaller SR-MOSFETs a minimum value of 0.1 μF may be sufficient, but larger
MOSFETs may require additional bypass capacitance to avoid excess ripple on the VCC voltage.
Suggested VCC bypass capacitance is 0.1 μF for each 2.2 nF of Ciss.
8.2.2.6 SYNC Input Considerations
In applications where the synchronous rectifier is used in continuous conduction mode (CCM) such as CCMFlyback and LLC converters, it is imperative that the SR-MOSFET be turned off as soon as the primary-side
switch turns on, to prevent reverse conduction of the SR-MOSFET. In these applications, a Y-type isolating
capacitor CSYNC can be used to convey a primary-side signal to the SR controller by coupling a negative-going
trigger voltage into the SYNC pin. Alternatively, an isolating pulse transformer may be used in situations where a
coupling capacitor is not practicable. When the SYNC voltage falls 2 V below VCC (the SYNC detection
threshold VTHSYNC), the GATE output is immediately turned off, regardless of the state of the TON timer. An
internal 2-kΩ pullup resistance (rSYNC) provides current to recharge the SYNC coupling capacitor. In the event
that the SYNC input voltage is continuously held below VTHSYNC, the GATE output is driven low for the same
duration.
The SYNC input has a maximum pulse current rating of ±100 mA, and a high-reliability design should reduce the
peak current further. This also reduces noise and signal losses in the system. A series resistor helps limit the
pulse current by reducing the effective dV/dt across CSYNC. Figure 23 illustrates a simple implementation of the
SYNC signal derived from the falling drain-source voltage of the primary-side MOSFET. In this example, a
synchronous-rectifier MOSFET is used in place of the free-wheeling diode in a single-transistor forward-mode
application. Note that primary-to-secondary common-mode capacitance CCM forms the return path for the SYNC
current.
Nominally, only –1 mA is required to develop –2 V across the internal 2-kΩ resistance and trigger the SYNC
function. This current is generated by a rapidly changing voltage across the SYNC coupling capacitor CSYNC. But
variations of this resistor, of CSYNC, and of the dV/dt across CSYNC require that worst-case tolerances be taken
into account when determining the minimum value of CSYNC. In addition, VSYNC must exceed the VTHSYNC
threshold for a minimum duration of 20 ns to ensure that the internal controller logic has reliably triggered.
Although the TON minimum on-time gate-drive function is overridden by the SYNC signal, the timer continues to
function otherwise. Light-load mode is entered if the proper conditions are met, as usual. The TOFF timer is
triggered when the SR-MOSFET VDS exceeds 1.5 V, as usual.
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5 V OUT
8
5
VD
GATE
7
3
2
6
VS
TON
EN/TOFF
GND
VCC
iSYNC_RESET
rSYNC
CSYNC
RSYNC
1
SYNC
VCC
4
To Control Logic
CPIN
iSYNC
UCC24610
UDG-10090
CCM
Figure 23. Driving the SYNC Input from the Primary-Side MOSFET Drain
CSYNC is the synchronization signal coupling capacitor, rated to cross the primary-to-secondary isolation
boundary. It is used to couple a negative-going voltage into the UCC24610 SYNC input (pin 1) to turn off the
GATE output to the SR-MOSFET when the primary-side MOSFET is turned on.
RSYNC is an optional external current-limiting resistor used to reduce the peak current into the SYNC input. It also
serves to reduce overall power loss, and reduce the common-mode noise current.
CCM is the main common-mode capacitance between the primary and the secondary sides of the system. This is
usually a discrete component, whose value ranges from 100 pF ≈2200 pF. Aside from any EMI-control purposes,
it also serves as the return path for the SYNC signal charging and discharging current pulses across the isolation
boundary.
Within the UCC24610 controller device is a 2-kΩ pullup resistor (rSYNC) to VCC. To trigger the SYNC function, a
negative-going signal must pull the SYNC input below the VTHSYNC threshold (nominally 2 V below VCC) for a
minimum duration of 20 ns. This requires a minimum 1-mA current to achieve, but prudent design will target a
higher current to allow for parameter variations.
Internal clamp diodes to VCC and GND also form parts of the charging and discharging current paths of the
SYNC signal. Finally, CPIN comprises stray internal and external pin and pad capacitances on the SYNC input,
and is modeled as ≈10 pF to GND. Although CPIN is physically unavoidable, it is wise to minimize any external
stray capacitance to keep its effect of additional delay on the SYNC function to a minimum.
24
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8.2.2.6.1 Determine the Minimum Change
Determine the minimum change in voltage ΔVSYNC-pri expected from the SYNC signal source. In this example, the
primary-side MOSFET drain-to-source voltage VDS_PRI is the signal source, and its minimum change is VBULK(min)
at low input line.
VSPIKE
VRESET
80%
VBULK
20%
Δtf
ΔVDS_PRI = VBULK at low-line
UDG-10089
Δtf = fall time for ΔVDS_PRI
between the 80% and 20% points
VSYNC-pri = ΔVDS_PRI
Figure 24. Primary MOSFET Drain Voltage
To allow for parameter and environmental variations, set the minimum peak SYNC current to 2 mA. With 2-mA
peak flowing through the internal 2-kΩ resistor, the SYNC voltage falls to 4-V below VCC. The maximum value
for current limiting resistor RSYNC is determined by Equation 11 and Equation 12.
RSYNC £
DVSYNC-pri
iSYNC (min)
- rSYNC
(11)
so in this case,
RSYNC £
VBULK (min)
- 2kW
2mA
(12)
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8.2.2.6.2 After the ΔVDS_PRI Transition
After the ΔVDS_PRI transition, the SYNC signal will begin to reset back to VCC by charging exponentially. This
allows the value of the SYNC coupling capacitor CSYNC to be determined by Equation 13.
CSYNC =
1.5 ´ tMIN
RSYNC + rSYNC
(13)
The value of CSYNC is chosen to ensure that the SYNC signal stays below the SYNC threshold for at least 20 ns.
Choose the minimum dwell time tMIN to be 40 ns to allow for parametric variations, shown in Equation 14.
CSYNC =
1.5 ´ 40ns
RSYNC + 2kW
(14)
8.2.2.6.3 The Value of CCM
The value of CCM should be much higher than that of CSYNC. If necessary, increase the value of CCM to ensure
that CCM >> CSYNC; do not decrease CSYNC.
8.2.2.6.4 Conservative Power-Loss Estimates
Conservative power-loss estimates for the internal and external SYNC resistances are:
é (VCC + 0.7 V)2 ù é æ DVSYNC-pri-max
PrSYNC £ ê
ú ´ êln çç
r
SYNC
ë
û ëê è DVSYNC-pri-min
ö ù
÷÷ + 1ú ´ [(RSYNC + rSYNC ) ´ CSYNC ´ fSW ]
ø ûú
(15)
and
é1
ù
PRSYNC £ 2 ´ ê ´ CSYNC ´ (VBULK + VRESET + VSPIKE )2 ´ fSW ú
ë2
û
where
•
fSW is the converter switching frequency.
(16)
These calculations can be used to predict the maximum thermal impact of the SYNC current on the device
junction temperature and to determine the external SYNC resistor power rating. Actual SYNC-related losses
generally are lower than these calculations predict and observations of actual circuit operation should be used to
determine true losses if more accuracy is required.
8.2.2.6.5 The Device Internal SYNC-to-GATE Delay Time
The device internal SYNC-to-GATE delay time tSDLY is a measure of how quickly the GATE output will turn off
after the SYNC signal has crossed the VTHSYNC threshold. However, stray pin capacitance CPIN introduces an
additional delay to the SYNC function by slowing the SYNC voltage falling 2-V below VCC. If CPIN is small, this
delay is relatively short and the SYNC current can be approximated as a constant current, allowing this
calculation to simplify to a simple linear equation given by:
tPIN _ DLY =
2 V ´ CPIN
iSYNC
(17)
Also, additional delay comes from the finite dV/dt of the signal source, in this case VDS_PRI, due to the finite
transition time from VBULK level to 0 V. This delay can be approximated by:
t dV _ DLY =
Dt f ´ RSYNC
RSYNC + rSYNC
(18)
These delay times should be added to the internal SYNC-to-GATE delay to determine the total delay time
expected between the falling of the primary-side MOSFET drain voltage and the turn off of the SR-FET gate
drive.
t OFF _ DLY = t SDLY + tPIN _ DLY + t dV _ DLY
26
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8.2.2.6.6 The CSYNC Capacitor Resets
The CSYNC capacitor resets during the off-time of the primary-side MOSFET, while the SR-FET is conducting.
The reset current iSYNC_RESET is similar to iSYNC. However, this reset current flows through the internal diode
between SYNC and VCC pins of the device.
ISEC
(A), (V)
(t)
VDS
Primary-Side PWM Output
SYNC Signal
GATE Output
TON Blanking
TOFF Blanking
ARMED
VDS < VTHON Detection
VDS > VTHOFF Detection
VDS > VTHARM Detection
UDG-10088
Figure 25. External and Internal Signal Timing Relationships with Respect to Realistic CCM Waveforms
8.2.2.7 Single-Fault Self-Protection Features
If RTON is less than 8.7 kΩ, the device may detect excess current and interpret this as a short-cir cuit and disable
the GATE output.
If RTON is greater than 301 kΩ, the device may detect insufficient current and interpret this as an open-circuit and
disable the GATE output, to avoid indefinite on-time.
Noise pick-up on excessive trace length may destabilize the internal 2-V source causing either insufficient or
excess current to RTON and triggering premature GATE shut off. This could cause GATE output to be less than
TON and lead to light-load mode even at heavy loads. Minimize RTON trace lengths.
If REN/TOFF is less than 93 kΩ, the device may detect insufficient voltage for Enable threshold and disable the
GATE output.
If REN/TOFF is greater than 284 kΩ, the device will internally clamp the programming voltage to deliver a minimum
TOFF of ≈0.65 µs, regardless of REN/TOFF value.
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8.2.3 Application Curves
The following oscilloscope screen-captures and performance data illustrate the operation of the UCC24610 SR
controller as applied in the UCC24610EVM-563 evaluation module, using, in part, the design method and
equations found in Detailed Design Procedure. These select figures are reproduced from Using the
UCC24610EVM-563 User's Guide (SLUU434).
115-VAC input
5-A load
115-VAC input
Figure 26. Primary and Secondary MOSFET Currents
115-VAC input
5-A load
115-VAC input
Figure 27. SR MOSFET Drain Current and SR GATE Signal
115-VAC input
Figure 28. SR MOSFET Gate and Drain Waveforms
5-A load
5-A load
Figure 29. Close-Up View of VD and SR GATE
115-VAC Input
Figure 30. Secondary-Side Waveforms
28
5-A load
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0-A load
green mode
Figure 31. Secondary-Side Waveforms
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0.85
0.80
0.75
85 VAC
115 VAC
K - Efficiency - %
0.70
0.65
230 VAC
0.60
0.55
0.50
265 VAC
0.45
0.40
0
115-VAC Input
0-A load
2
3
4
5
Load - A
green mode
Figure 32. Primary-Side Waveforms
1
Figure 33. Overall EVM Efficiency as a Function of Load
Current and Input Voltage
9 Power Supply Recommendations
The UCC24610 in nominally a 5-V only controller as regards to the VCC bias supply rating. Although the
absolute maximum rating for VCC is 6.5 V, it is recommended to operate the device with VCC < 5.5 V to allow
margin for voltage-rail transients and surges. Although the device may typically function with VCC down to 4.2 V,
it is recommended to operate the device at VCC ≥ 4.5 V to provide adequate gate-drive to the SR MOSFET. Use
a ceramic bypass capacitor from VCC to GND of suitable value to provide the total gate charge each switching
cycle.
10 Layout
10.1 Layout Guidelines
The printed circuit board (PCB) requires conscientious layout to minimize current loop areas and track lengths,
especially when using single-sided PCBs.
• Place a ceramic MLCC bypass capacitor as close as possible to VCC and GND.
• Avoid connecting VD and VS sense points at locations where stray inductance is added to the SR MOSFET
package inductance, as this will tend to turn off the SR prematurely.
• Run a track from the VD pin directly to the MOSFET drain pad to avoid sensing voltage across the stray
inductance in the SR drain current path. Include an RVD component option in series with the VD pin unless
previous testing has shown that it is not necessary.
• Run a track from the VS pin directly to the MOSFET source pad to avoid sensing voltage across the stray
inductance in the SR source current path. Do not simply connect VS to the controller GND pin. Include an
RVS component option in series with the VS pin unless previous testing has shown that it is not necessary.
• Run parallel tracks from GATE and GND to the SR MOSFET. Include a series gate resistance to dampen
ringing.
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10.2 Layout Example
Secondary Winding
RTOFF
EN/TOFF
RVD
VD
SYNC
U1
VS
RTON
Q1
RVS
UCC24610
TON
GND
VCC
GATE
RGATE
G
D
S
CVCC
L2
C10
C9
C8
C11
GND
VOUT+
Figure 34. Single-Sided PCB Layout Using a TO-220 MOSFET
30
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
GREEN Rectifier, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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31
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA01055DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4610
UCC24610D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
24610
UCC24610DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
24610
UCC24610DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4610
UCC24610DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4610
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC24610DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UCC24610DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
UCC24610DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
UCC24610DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC24610DR
SOIC
D
8
2500
340.5
338.1
20.6
UCC24610DRBR
SON
DRB
8
3000
370.0
355.0
55.0
UCC24610DRBT
SON
DRB
8
250
220.0
205.0
50.0
UCC24610DRBT
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.5 0.1
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
(0.65)
8X
0.37
0.25
0.1
0.05
C A B
C
0.5
0.3
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31) 1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.23)
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
8X (0.31)
4X
(0.725)
8
1
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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