UCC27322-EP
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SLUSAA1C – SEPTEMBER 2010 – REVISED MARCH 2013
SINGLE 9-A HIGH-SPEED LOW-SIDE MOSFET DRIVER WITH ENABLE
Check for Samples: UCC27322-EP
FEATURES
1
•
2
•
•
•
•
•
•
•
Industry-Standard Pinout With Addition of
Enable Function
High-Peak Current Drive Capability of ±9 A at
the Miller Plateau Region Using TrueDrive™
Efficient Constant Current Sourcing Using a
Unique Bipolar and CMOS Output Stage
TTL-/CMOS-Compatible Inputs Independent of
Supply Voltage
20-ns Typical Rise and 15-ns Typical Fall
Times With 10-nF Load
Typical Propagation Delay Times of 25 ns With
Input Falling and 35 ns With Input Rising
4-V to 15-V Supply Voltage
Pb-Free Finish (NiPdAu)
APPLICATIONS
•
•
•
•
•
•
Switch-Mode Power Supplies
DC/DC Converters
Motor Controllers
Line Drivers
Class D Switching Amplifiers
Pulse Transformer Driver
DGK PACKAGE
(TOP VIEW)
VDD
IN
ENBL
AGND
1
8
2
7
3
6
4
5
VDD
OUT
OUT
PGND
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Rated From –55°C to 125°C
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
The UCC27322 delivers 9 A of peak drive current in an industry standard pinout. These drivers can drive the
largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates
additional external circuits and can replace multiple components to reduce space, design complexity and
assembly cost.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
UCC27322-EP
SLUSAA1C – SEPTEMBER 2010 – REVISED MARCH 2013
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INPUT/OUTPUT TABLE
VDD
1
8
7
VDD
OUT
VDD
IN
2
ENBL
3
AGND
4
6
OUT
5
PGND
ENBL
IN
OUT
0
0
0
0
1
0
1
0
0
1
1
1
RENBL
100 kΩ
Using a design that inherently minimizes shoot-through current, the outputs of these can provide high gate drive
current where it is most needed at the Miller plateau region during the MOSFET switching transition. A unique
hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at low
supply voltages. With this drive architecture, UCC27322 can be used in industry standard 6-A, 9-A and many 12A driver applications. Latch up and ESD protection circuits are also included. Finally, the UCC27322 provides an
enable (ENBL) function to have better control of the operation of the driver applications. ENBL is implemented on
pin 3 which was previously left unused in the industry standard pin-out. It is internally pulled up to VDD for active
high logic and can be left open for standard operation.
ORDERING INFORMATION (1)
TA
PACKAGE
–40°C to 105°C
DGK
–55°C to 125°C
D
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VID NUMBER
Reel of 2500
UCC27322TDGKREP
QTK
V62/11601-01XE
Reel of 2500
UCC27322MDREP
27322M
V62/11601-02YE
Tube of 75
UCC27322MDEP
27322M
V62/11601-02YE-T
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Table 1. TERMINAL FUNCTIONS
TERMINAL
2
I/O
DESCRIPTION
NO.
NAME
4
AGND
—
3
ENBL
I
Enable input for the driver with logic compatible threshold and hysteresis. The driver output can be enabled
and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The
output state when the device is disabled will be low regardless of the input state.
2
IN
I
Input signal of the driver which has logic compatible threshold and hysteresis.
6, 7
OUT
O
Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak
drive current to the gate of a power MOSFET.
5
PGND
—
Common ground for output stage. This ground should be connected very closely to the source of the power
MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output
switching di/dt which can affect the input threshold.
1, 8
VDD
I
Common ground for input stage. This ground should be connected very closely to the source of the power
MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output
switching di/dt which can affect the input threshold.
Supply voltage and the power input connections for this device. Three pins must be connected together
externally.
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ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
IO
Output current, OUT
VI
–0.3 V to 16 V
0.6 A
IN
-0.3 V to 6 V or VDD + 0.3 V
(whichever is larger)
ENBL
-0.3 V to 6 V or VDD + 0.3 V
(whichever is larger)
Input voltage
Latch-up protection (3)
IN, OUT
500 mA
TJ
Junction operating temperature
–55°C to 150°C
Tstg
Storage temperature
–65°C to 150°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.
Specified by design
THERMAL INFORMATION
UCC27322
THERMAL METRIC
DGK
D
8 PINS
8 PINS
θJA
Junction-to-ambient thermal resistance (1)
161.8
116.3
θJCtop
Junction-to-case (top) thermal resistance (2)
56.2
70.8
θJB
Junction-to-board thermal resistance (3)
81.1
56.6
5.7
22.8
(4)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (5)
79.8
56.1
θJCbot
Junction-to-case (bottom) thermal resistance (6)
N/A
N/A
(1)
(2)
(3)
(4)
(5)
(6)
UNITS
°C/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
OVERALL ELECTRICAL CHARACTERISTICS
VDD = 4.5 V to 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DGK PACKAGE
D PACKAGE
TJ = TA = -40°C to 105°C
TJ = TA = -55°C to 125°C
MIN
IDD
Static operating current
TYP
MAX
IN = Low, ENBL = Low, VDD = 15 V
150
225
225
IN = High, ENBL = Low, VDD = 15 V
450
650
650
IN = Low, ENBL = High, VDD = 15 V
75
125
125
IN = High, ENBL = High, VDD = 15 V
675
1000
1000
Copyright © 2010–2013, Texas Instruments Incorporated
MIN
UNIT
MAX
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3
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INPUT (IN) ELECTRICAL CHARACTERISTICS
VDD = 4.5 V to 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DGK PACKAGE
D PACKAGE
TJ = TA = -40°C to 105°C
TJ = TA = -55°C to 125°C
MIN
VIH
Logic 1 input threshold
VIL
Logic 0 input threshold
TYP
MAX
MIN
2
2
V
1
0 V ≤ VIN ≤ VDD
Input current
UNIT
MAX
–10
0
10
–10
1
V
10
µA
OUTPUT (OUT) ELECTRICAL CHARACTERISTICS
VDD = 4.5 V to 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DGK PACKAGE
D PACKAGE
TJ = TA = -40°C to 105°C
TJ = TA = -55°C to 125°C
MIN
Peak output current (1)
(2)
VDD = 14 V
High-level output voltage
VOH = VDD – VOUT, IOUT = –10 mA
VOL
Low-level output voltage
Output resistance high (3)
Output resistance low (3)
(3)
MAX
MIN
UNIT
MAX
9
VOH
(1)
(2)
TYP
A
150
300
300
mV
IOUT = 10 mA
11
25
25
mV
IOUT = –10 mA, VDD = 14 V
15
25
25
Ω
IOUT = 10 mA, VDD = 14 V
1.1
2.5
2.5
Ω
Specified by design
The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
ENABLE (ENBL) ELECTRICAL CHARACTERISTICS
VDD = 4.5 V to 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DGK PACKAGE
D PACKAGE
TJ = TA = -40°C to 105°C
TJ = TA = -55°C to 125°C
UNIT
MIN
TYP
MAX
MIN
MAX
VEN_H
Enable rising threshold
voltage
Low to high transitions
1.7
2.2
2.7
1.5
3.4
V
VEN_L
Enable falling threshold
voltage
High to low transition
1.1
1.6
2
1.1
2.2
V
0.25
0.55
0.90
0.18
1.15
V
75
100
135
75
180
kΩ
Hysteresis
R(ENBL)
Enable impedance
VDD = 14 V, ENBL = Low
tD3
Propagation delay time
CLOAD = 10 nF (see Figure 3)
60
90
95
ns
tD4
Propagation delay time
CLOAD = 10 nF (see Figure 3)
60
90
95
ns
SWITCHING CHARACTERISTICS
VDD = 4.5 V to 15 V (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITIONS
DGK PACKAGE
D PACKAGE
TJ = TA = -40°C to 105°C
TJ = TA = -55°C to 125°C
MIN
TYP
MAX
MIN
UNIT
MAX
tR
Rise time (OUT)
CLOAD = 10 nF
20
70
77
ns
tF
Fall time (OUT)
CLOAD = 10 nF
20
30
35
ns
tD1
Delay time, IN rising (IN to OUT)
CLOAD = 10 nF
25
70
75
ns
tD2
Delay time, IN falling (IN to OUT)
CLOAD = 10 nF
35
70
75
ns
4
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SLUSAA1C – SEPTEMBER 2010 – REVISED MARCH 2013
10000.00
Wirebond Voiding
Fail Mode (D package)
1000.00
Estimated Life (Years)
Wirebond Voiding
Fail Mode (DGK package)
100.00
10.00
Electromigration Fail Mode
1.00
0.10
80
90
100
110
120
130
140
150
160
Continuous T J(°C)
Notes:
1.
See data sheet for absolute maximum and minimum recommended operating conditions.
2.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package
interconnect life).
3.
Enhanced plastic product disclaimer applies.
4.
Electromigration calculation is based on operating the part at 2.5 MHz at a 50% duty cycle.
Figure 1. UCC27322 Operating Life Derating Chart
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(a)
(b)
5V
IN
VTH
0V
tD1
VTH
IN
VTH
tD2
VTH
tD1
tD2
tF
VDD
80%
80%
80%
tR
OUT
80%
tR
OUT
20%
tF
20%
0V
A.
The 20% and 80% thresholds depict the dynamics of the Bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 2. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
5V
ENBL
VIN_L
VIN_H
0V
tD3
tD4
VDD
80%
80%
tR
OUT
tF
20%
0V
A.
The 20% and 80% thresholds depict the dynamics of the Bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 3. Switching Waveforms for Enable to Output
6
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TYPICAL CHARACTERISTICS
700
800
ENBL = HI
IN = HI
700
600
ENBL = 0 V
IN = 5 V
500
IDD − Input Current Idle − μA
IDD − Input Current Idle − µA
INPUT CURRENT IDLE
vs
TEMPERATURE (UCCx7322)
INPUT CURRENT IDLE
vs
SUPPLY VOLTAGE (UCCx7322)
400
ENBL = 0 V
IN = 0 V
300
ENBL = VDD
IN = 5 V
200
ENBL = VDD, IN = 0 V
600
ENBL = LO
IN = HI
500
400
ENBL = LO
IN = LO
300
ENBL = HI
IN = LO
200
100
100
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
0
16
−50
−25
Figure 4.
RISE TIME
vs
SUPPLY VOLTAGE
75
0
25
50
TJ − Temperature − °C
Figure 5.
100
125
FALL TIME
vs
SUPPLY VOLTAGE
70
70
CLOAD = 10 nF
CLOAD = 10 nF
60
60
tA = −55°C
50
tA = −40°C
40
tA = 125°C
Fall Time (ns)
Rise Time (ns)
50
tA = 105°C
tA = 25°C
30
40
tA = 105°C
tA = 125°C
30
tA = 25°C
20
20
10
tA = 0°C
10
tA = −40°C
tA = −55°C
tA = 0°C
0
0
4.5
6.2
8
9.8
11.5
Supply Voltage (V)
Figure 6.
Copyright © 2010–2013, Texas Instruments Incorporated
13.2
15
4.5
6.2
8
9.8
11.5
Supply Voltage (V)
13.2
15
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
0.1
1.0
0.1
70
Figure 8.
Figure 9.
tD1 DELAY TIME
vs
SUPPLY VOLTAGE
tD2 DELAY TIME
vs
SUPPLY VOLTAGE
70
CLOAD = 10 nF
60
tA = 125°C
tA = 25°C
tA = 25°C
tA = 105°C
40
tA = 105°C
50
Delay Time (ns)
Delay Time (ns)
50
30
20
40
30
tA = −55°C
tA = −40°C
20
tA = 125°C
tA = 0°C
tA = −55°C
10
CLOAD = 10 nF
tA = 0°C
60
10
tA = −40°C
0
0
4.5
6.2
8
9.8
11.5
Supply Voltage (V)
Figure 10.
8
1.0
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13.2
15
4.5
6.2
8
9.8
11.5
Supply Voltage (V)
13.2
15
Figure 11.
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UCC27322-EP
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SLUSAA1C – SEPTEMBER 2010 – REVISED MARCH 2013
TYPICAL CHARACTERISTICS (continued)
tD2 DELAY TIME
vs
LOAD CAPACITANCE
tD1 DELAY TIME
vs
LOAD CAPACITANCE
70
70
VDD = 5 V
60
50
tD2 − Delay Time − ns
tD1 − Delay Time − ns
60
VDD = 10 V
VDD = 5 V
40
30
20
50
40
30
VDD = 15 V
20
VDD = 15 V
10
10
0
1
10
0
100
1
CLOAD − Load Capacitance − nF
Figure 12.
10
CLOAD − Load Capacitance − nF
Figure 13.
PROPAGATION TIMES
vs
PEAK INPUT VOLTAGE
50
100
INPUT THRESHOLD
vs
TEMPERATURE
2
45
tD2
VDD = 15 V
CLOAD = 10 nF
TA = 25°C
1.9
40
VDD = 15 V
tRISE
1.8
35
Input Threshold Voltage (V)
Propagation Time − ns
VDD = 10 V
30
25
20
15
10
1.6
1.5
VDD = 4.5 V
1.4
tFALL
tD1
1.7
VDD = 10 V
1.3
5
0
0
5
10
VIN(peak) − Peak Input Voltage − V
Figure 14.
Copyright © 2010–2013, Texas Instruments Incorporated
15
1.2
−55
−25
5
35
65
Temperature (°C)
95
125
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
ENABLE THRESHOLD AND HYSTERESIS
vs
TEMPERATURE
ENABLE RESISTANCE
vs
TEMPERATURE
3.0
150
140
RENBL − Enable Resistance − Ω
Enable Threshold and Hysteresis − V
ENBL − ON
2.5
2.0
1.5
1.0
ENBL − OFF
130
120
110
100
0.5
ENBL − HYSTERESIS
90
80
70
60
0
50
−50
−25
75
0
25
50
TJ − Temperature − °C
Figure 16.
100
−50
125
−25
75
0
25
50
TJ − Temperature − °C
Figure 17.
IN = VDD
ENBL = VDD
IN = VDD
ENBL = VDD
VDD − Input Voltage − V
1 V/div
VDD − Input Voltage − V
1 V/div
125
OUTPUT BEHAVIOR
vs
VDD (UCC37322)
OUTPUT BEHAVIOR
vs
VDD (UCC37322)
VDD
OUT
0V
VDD
OUT
0V
10 nF Between Output and GND
50 µs/div
Figure 18.
10
100
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10 nF Between Output and GND
50 µs/div
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
IN = GND
ENBL = VDD
VDD
OUT
0V
VDD − Supply Voltage − V
1 V/div
VDD − Supply Voltage − V
1 V/div
IN = GND
ENBL = VDD
VDD
OUT
0V
10 nF Between Output and GND
50 µs/div
Figure 20.
Copyright © 2010–2013, Texas Instruments Incorporated
10 nF Between Output and GND
50 µs/div
Figure 21.
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APPLICATION INFORMATION
General Information
The UCC27322 driver serves as an interface between low-power controllers and power MOSFETs. It can also be
used as an interface between DSPs and power MOSFETs. High-frequency power supplies often require highspeed, high-current drivers such as the UCC27322. A leading application is the need to provide a high power
buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT
switching devices. In other cases, the device drives the power device gates through a drive transformer.
Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present
an extremely large load to the control circuitry.
MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device
directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive
capability required for the intended switching MOSFET, limiting the switching performance in the application. In
other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high
current driver physically close to the load. Also, newer devices that target the highest operating frequencies may
not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance
input to a driver such as the UCC27322. Finally, the control device may be under thermal stress due to power
dissipation, and an external driver can help by moving the heat from the controller to an external package.
Input Stage
The IN threshold has a 3.3-V logic sensitivity over the full range of VDD voltages; yet, it is equally compatible with
0 V to VDD signals. The inputs of UCC27322 driver is designed to withstand 500-mA reverse current without
either damage to the device or logic upset. In addition, the input threshold turn-off of the UCC27322 has been
slightly raised for improved noise immunity. The input stage of each driver should be driven by a signal with a
short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are
provided by a PWM controller or logic gates with fast transition times (