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UCC27423, UCC27424, UCC27425
SLUS545E – NOVEMBER 2002 – REVISED DECEMBER 2015
UCC2742x Dual 4-A High Speed Low-Side MOSFET Drivers With Enable
1 Features
3 Description
•
•
•
•
The UCC2742x family of high-speed dual MOSFET
drivers can deliver large peak currents into capacitive
loads. Three standard logic options are offered –
dual-inverting, dual-noninverting, and one-inverting
and one-noninverting driver. The thermally enhanced
8-pin PowerPAD™ MSOP package (DGN) drastically
lowers the thermal resistance to improve long-term
reliability. It is also offered in the standard SOIC-8 (D)
or PDIP-8 (P) packages.
1
•
•
•
•
•
•
•
Industry-Standard Pin-Out
Enable Functions for Each Driver
High Current Drive Capability of ±4 A
Unique BiPolar and CMOS True Drive Output
Stage Provides High Current at MOSFET Miller
Thresholds
TTL/CMOS Compatible Inputs Independent of
Supply Voltage
20-ns Typical Rise and 15-ns Typical Fall Times
with 1.8-nF Load
Typical Propagation Delay Times of 25 ns with
Input Falling and 35 ns with Input Rising
4-V to 15-V Supply Voltage
Dual Outputs Can Be Paralleled for Higher Drive
Current
Available in Thermally Enhanced MSOP
PowerPAD™ Package
Rated From –40°C to 125°C
Using a design that inherently minimizes shootthrough current, these drivers deliver 4A of current
where it is needed most at the Miller plateau region
during the MOSFET switching transition. A unique
BiPolar and MOSFET hybrid output stage in parallel
also allows efficient current sourcing and sinking at
low supply voltages.
The UCC2742x provides enable (ENB) functions to
have better control of the operation of the driver
applications. ENBA and ENBB are implemented on
pins 1 and 8 which were previously left unused in the
industry standard pin-out. They are internally pulled
up to VDD for active high logic and can be left open
for standard operation.
2 Applications
•
•
•
•
•
Switch Mode Power Supplies
DC/DC Converters
Motor Controllers
Line Drivers
Class D Switching Amplifiers
Device Information(1)
PART NUMBER
UCC27423
UCC27424
UCC27425
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
ENBB
UCC2742x
ENBA
1
ENBA
ENBB
8
INA
2
INA
OUTA
7
3
GND
VDD
6
4
INB
OUTB
5
V+
GND
INB
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27423, UCC27424, UCC27425
SLUS545E – NOVEMBER 2002 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 20
11.3 Thermal Considerations ........................................ 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2013) to Revision E
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision C (July 2011) to Revision D
Page
•
Added Pin Functions table note.............................................................................................................................................. 3
•
Added ABSOLUTE MAXIMUM RATINGS note...................................................................................................................... 4
•
Added additional ENABLE pin description. .......................................................................................................................... 12
Changes from Revision B (November 2004) to Revision C
Page
•
Changed temperature rating................................................................................................................................................... 1
•
Changed ORDERING INFORMATION temperature range, three instances. ........................................................................ 1
•
Changed Output current (OUTA, OUTB) DC from 0.3 A to 0.2 A.......................................................................................... 4
•
Changed ELECTRICAL CHARACTERISTICS temperature rating. ....................................................................................... 5
•
Changed Low-level output level from 40 mV max to 45 mV max. ......................................................................................... 5
2
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SLUS545E – NOVEMBER 2002 – REVISED DECEMBER 2015
5 Device Comparison Table
(1)
(2)
OUTPUT
CONFIGURATION
TEMPERATURE RANGE
TA = TJ
PACKAGED DEVICES
SOIC-8
(D) (1)
MSOP-8 PowerPAD
(DGN) (2)
PDIP-8
(P)
Dual inverting
–40°C to 125°C
UCC27423D
UCC27423DGN
UCC27423P
Dual nonInverting
–40°C to 125°C
UCC27424D
UCC27424DGN
UCC27424P
One inverting,
one noninverting
–40°C to 125°C
UCC27425D
UCC27425DGN
UCC27425P
D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR,
UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.
The PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
6 Pin Configuration and Functions
D Package, DGN Package, P Package
8-Pin SOIC, 8-PIn MSOP-PowerPAD, 8-Pin PDIP
Top View
UCC27425
UCC27424
UCC27423
ENBA 1
8 ENBB
ENBA 1
8 ENBB
ENBA 1
8 ENBB
INA 2
7 OUTA
INA 2
7 OUTA
INA 2
7 OUTA
6 VDD
GND 3
5 OUTB
INB 4
(DUAL INVERTING)
GND 3
INB 4
6 VDD
5 OUTB
GND 3
INB 4
(DUAL NON-INVERTING)
6 VDD
5 OUTB
(ONE INVERTING AND
ONE NON-INVERTING)
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
ENBA
1
I
Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with
this pin. It is internally pulled up to VDD with 100 kΩ resistor for active high operation. The output state when the device is
disabled will be low regardless of the input state.
ENBB
8
I
Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with
this pin. It is internally pulled up to VDD with 100 kΩ resistor for active high operation. The output state when the device is
disabled will be low regardless of the input state. (1)
GND
3
—
Common ground: this ground should be connected very closely to the source of the power MOSFET which the driver is driving.
INA
2
I
Input A: input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to
either VDD or GND. It should not be left floating. (1)
INB
4
I
Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to
either VDD or GND. It should not be left floating.
OUTA
7
O
Driver output A. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
OUTB
5
O
Driver output B. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
VDD
6
I
Supply. Supply voltage and the power input connection for this device.
(1)
Refer to Detailed Description for more details.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
–0.3
16
V
Output current (OUTA, OUTB) DC
0.2
A
Pulsed, (0.5 μs)
4.5
A
–5
6 or VDD + 0.3 (whichever is larger)
V
–0.3
6 or VDD + 0.3 (whichever is larger)
V
3
W
VDD
Supply voltage
IOUT_DC
IOUT_PULSED
VIN
Input voltage (INA, INB)
Enable voltage (ENBA, ENBB)
DGN package
Power dissipation at
TA = 25°C
TJ
D package
650
P package
350
Junction operating temperature
–55
Lead temperature (soldering, 10 s)
Tstg
(1)
(2)
Storage temperature
–65
mW
150
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
When VDD ≤ 6 V, EN rating max value is 6 V; when VDD > 6 V, EN rating max value is VDD + 0.3 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
INA and INB
Input voltage
ENA and ENB
Enable voltage
TJ
Operating junction temperature
NOM
MAX
UNIT
4
15
V
–2
15
V
0
15
V
–40
125
°C
7.4 Thermal Information
UCC2742x
THERMAL METRIC
(1)
D (SOIC)
DGN (MSOP)
P (PDIP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
107.3
56.6
55.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.2
52.8
45.3
°C/W
RθJB
Junction-to-board thermal resistance
47.3
32.6
32.6
°C/W
ψJT
Junction-to-top characterization parameter
10.2
1.8
23.0
°C/W
ψJB
Junction-to-board characterization parameter
46.8
32.3
32.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
5.9
–
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLUS545E – NOVEMBER 2002 – REVISED DECEMBER 2015
7.5 Electrical Characteristics
VDD = 4.5 V to 15 V, TA = –40°C to 125°C,TA = TJ, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INPUT (INA, INB)
VIN_H Logic 1 input threshold
2
VIN_L Logic 0 input threshold
1
0 V ≤ VIN ≤ VDD
Input current
–10
0
10
V
μA
OUTPUT (OUTA, OUTB)
(1)
Output current
VDD = 14 V
VOH
High-level output voltage
VOH = VDD – VOUT, IOUT = –10 mA
VOL
Low-level output level
IOUT = 10 mA
Output resistance high
4
TA = 25°C, IOUT = –10 mA, VDD = 14 V (2)
25
TA = full range, IOUT = –10 mA, VDD = 14 V (2)
18
TA = 25°C, IOUT = 10 mA, VDD = 14 V
Output resistance low
(2)
TA = full range IOUT = 10 mA, VDD = 14 V (2)
Latch-up protection
1.9
A
330
450
22
45
30
35
45
2.2
1.2
2.5
mV
Ω
4.0
500
mA
SWITCHING TIME
tr
Rise time (OUTA, OUTB)
CLOAD = 1.8 nF
20
40
tf
Fall time (OUTA, OUTB)
CLOAD = 1.8 nF
15
40
td1
Delay, IN rising (IN to OUT)
CLOAD = 1.8 nF
25
40
td2
Delay, IN falling (IN to OUT)
CLOAD = 1.8 nF
35
50
2.4
2.9
V
V
ns
ENABLE (ENBA, ENBB)
VIN_H High-level input voltage
LO to HI transition
VIN_L Low-level input voltage
HI to LO transition
Hysteresis
1.7
1.1
1.8
2.2
0.15
0.55
0.90
V
75
100
140
kΩ
RENB Enable impedance
VDD = 14 V, ENB = GND
tD3
Propagation delay time (see Figure 2)
CLOAD = 1.8 nF
30
60
ns
tD4
Propagation delay time (see Figure 2)
CLOAD = 1.8 nF
100
150
ns
INA = 0 V, INB = 0 V
900 1350
INA = 0 V, INB = HIGH
750 1100
INA = HIGH, INB = 0 V
750 1100
INA = HIGH, INB = HIGH
600
900
INA = 0 V, INB = 0 V
300
450
INA = 0 V, INB = HIGH
750 1100
INA = HIGH, INB = 0 V
750 1100
OVERALL
IDD
IDD
UCC27423
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V
UCC27424
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V
INA = HIGH, INB = HIGH
INA = 0 V, INB = 0 V
IDD
IDD
(1)
(2)
UCC27425
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V
All disabled, VDD = 15 V,
ENBA = ENBB = 0 V
INA = 0 V, INB = HIGH
μA
μA
1200 1800
600
900
1050 1600
INA = HIGH, INB = 0 V
450
700
INA = HIGH, INB = HIGH
900 1350
INA = 0 V, INB = 0 V
300
450
INA = 0 V, INB = HIGH
450
700
INA = HIGH, INB = 0 V
450
700
INA = HIGH, INB = HIGH
600
900
μA
μA
The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
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7.6 Dissipation Ratings
PACKAGE
SUFFIX
POWER RATING (mW)
TA = 70°C (1)
DERATING FACTOR ABOVE
70°C (mW/°C) (1)
SOIC-8
D
344–655 (2)
6.25–11.9 (2)
PDIP-8
P
500
9
DGN
1370
17.1
MSOP
(1)
(2)
(3)
(3)
125°C operating junction temperature is used for power rating calculations
The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best
and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order
to spread the heat away form the device more effectively. For information on the PowerPAD™ package, refer to Technical Brief,
PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) and Application Brief, PowerPad Made Easy, Texas
Instruments (SLMA004).
The PowerPAD™ is not directly connected to any leads of this package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
(a)
(b)
+5V
90%
90%
INPUT
INPUT
10%
0V
10%
t D1
tR
t D2
tF
16V
90%
90%
tF
tR
90%
t D1
OUTPUT
t D2
OUTPUT
10%
0V
10%
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
5V
ENBx
VIN_L
VIN_H
0V
tD3
tD4
VDD
90%
OUTx
90%
tR
tF
10%
0V
NOTE: The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output
6
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7.7 Typical Characteristics
100
100
80
10 nF
IDD - Supply Current - mA
IDD - Supply Current - mA
80
60
40
4.7 nF
2.2 nF
20
10 nF
4.7 nF
60
40
2.2 nF
1 nF
20
1 nF
470 pF
470 pF
0
0
500 K
1M
1.5 M
0
2M
0
500 K
f - Frequency - Hz
1M
1.5 M
2M
f - Frequency - Hz
Figure 3. Supply Current vs Frequency (VDD = 4.5 V)
Figure 4. Supply Current vs Frequency (VDD = 8.0 V)
IDD - Supply Current - mA
200
150
10 nF
4.7 nF
100
2.2 nF
50
1 nF
470 pF
0
0
500 K
1M
1.5 M
2M
f - Frequency - Hz
Figure 5. Supply Current vs Frequency (VDD = 12 V)
Figure 6. Supply Current vs Frequency (VDD = 15 V)
160
90
80
140
120
IDD - Supply Current - mA
IDD - Supply Current - mA
2 MHz
70
60
50
1 MHz
40
30
500 kHz
20
2 MHz
100
1 MHz
80
60
500 kHz
40
200 kHz
200 kHz
20
10
0
100 kHz
100/50 kHz
4
6
8
12
10
VDD - Supply Voltage - V
14
16
Figure 7. Supply Current vs Supply Voltage
(CLOAD = 2.2 nF)
0
50/20 kHz
4
9
14
19
VDD - Supply Voltage - V
Figure 8. Supply Current vs Supply Voltage
(CLOAD = 4.7 nF)
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Typical Characteristics (continued)
Figure 9. Supply Current vs Supply Voltage (UCC27423)
Figure 10. Supply Current vs Supply Voltage (UCC27424)
25
0.75
0.70
tr
20
tr/tf - Rise/Fall Time - ns
IDD - Supply Current - mA
0.65
Input = VDD
0.60
0.55
0.50
Input = 0 V
0.45
0.40
15
tf
10
5
0.35
0
0.30
4
6
8
10
12
14
-50
16
0
50
100
150
TJ - Temperature -°C
VDD - Supply Voltage - V
Figure 12. Rise Time and Fall Time
vs Temperature (UCC27423)
tf - Fall Time - ms
Figure 11. Supply Current vs Supply Voltage (UCC27425)
Figure 13. Rise Time vs Supply Voltage
8
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Figure 14. Fall Time vs Supply Voltage
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Typical Characteristics (continued)
30
38
28
36
24
22
4.7 nF
20
18
2.2 nF
16
32
4.7 nF
30
28
2.2 nF
26
470 pF
24
1 nF
470 pF
14
12
10 nF
34
10 nF
tD2 - Delay Time - ns
tD1 - Delay Time - ns
26
22
1 nF
4
6
8
10
12
20
14
16
4
6
VDD - Supply Voltage - V
Figure 15. Delay Time (tD1) vs Supply Voltage (UCC27423)
8
10
12
VDD - Supply Voltage - V
14
16
Figure 16. Delay Time (tD2) vs Supply Voltage (UCC27423)
3.0
kΩ
Enable threshold and hysteresis - V
ENBL - ON
2.5
2.0
1.5
1.0
ENBL - OFF
0.5
ENBL - HYSTERESIS
0
-50
-25
0
25
50
75
TJ - Temperature - °C
100
125
Figure 17. Enable Threshold and Hysteresis vs Temperature
Figure 18. Enable Resistance vs Temperature
50 ms/div
50 ms/div
Figure 19. Output Behavior vs Supply Voltage (Inverting)
Figure 20. Output Behavior vs Supply Voltage (Inverting)
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Typical Characteristics (continued)
VDD - Supply Voltage - V
1 V/div
IN = VDD
ENBL = VDD
VDD
OUT
0V
10 nF Between Output and GND
50 ms/div
50 ms/div
Figure 21. Output Behavior vs VDD (Inverting)
Figure 22. Output Behavior vs VDD (Inverting)
50 ms/div
50 ms/div
Figure 23. Output Behavior vs VDD (Noninverting)
Figure 24. Output Behavior vs VDD (Noninverting)
VDD - Supply Voltage - V
1 V/div
IN = GND
ENBL = VDD
VDD
OUT
0V
10
50 ms/div
10 nF Between Output and GND
50 ms/div
Figure 25. Output Behavior vs VDD (Noninverting)
Figure 26. Output Behavior vs VDD (Noninverting)
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Typical Characteristics (continued)
2.0
VON - Input Threshold Voltage - V
1.9
VDD = 15 V
1.8
1.7
1.6
1.5
VDD = 10 V
VDD = 4.5 V
1.4
1.3
1.2
-50
-25
0
25
50
75
100
125
TJ - Temperature - °C
Figure 27. Input Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The UCC2742x family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads.
Three standard logic options are offered – dual-inverting, dual-noninverting and one-inverting and onenoninverting driver. The thermally enhanced 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the
thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P)
packages. Using a design that inherently minimizes shoot-through current, these drivers deliver 4A of current
where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique Bipolar
and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply
voltages. Table 1 highlights more details about UCC2742x.
Table 1. UCC2742x Features and Benefits
FEATURE
BENEFIT
1-ns (typ) delay matching between channels
Ease of paralleling outputs for higher (2 times) current capability,
ease of driving parallel-power switches
Expanded VDD operating range of 4 to 15 V
Flexibility in system design
Outputs enabled when enable pins (ENx) in floating condition
Pin-to-pin compatibility with the UCC27324 device from Texas
Instruments and industry standard pinout, in designs where Pin 1
and Pin 8 are in floating condition
CMOS/TTL compatible input and enable threshold with wide
hysteresis
Enhanced noise immunity, while retaining compatibility with
microcontroller logic-level inputs signals (3.3 V, 5 V) optimized for
digital power
Ability to handle –5 VDC (max) at input pins (INA/B)
Increased robustness in noisy environments
8.2 Functional Block Diagram
8
ENBB
7
OUTA
6
VDD
5
OUTB
ENBA 1
INVERTING
INA 2
VDD
NON-INVERTING
INVERTING
GND 3
INB 4
NON-INVERTING
UDG-01063
8.3 Feature Description
8.3.1 Enable
UCC2742x provides dual Enable inputs for improved control of each driver channel operation. The inputs
incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100kΩ resistor
for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and
ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore
can be left open for standard operation. However, if the enable pin is left open, it is recommended to terminate
any PCB traces to be as short as possible to limit noise. If large noise is present due to non-optimal PCB layout,
it is recommended to tie the Enable pin to Vcc or to add a filter capacitor (0.1 µF) to the Enable pin. The output
states when the drivers are disabled is low regardless of the input state. See the truth table of Table 2 for the
operation using enable logic.
12
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Product Folder Links: UCC27423 UCC27424 UCC27425
UCC27423, UCC27424, UCC27425
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SLUS545E – NOVEMBER 2002 – REVISED DECEMBER 2015
Feature Description (continued)
Enable input are compatible with both logic signals and slow changing analog signals. They can be directly
driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and
ENBB control input A and input B respectively.
8.3.2 Input Stage
The input thresholds have 3.3 V logic sensitivity over the full range of VDD voltages; it is equally compatible with 0
to VDD signals. The inputs of the UCC2742x driver family are designed to withstand 500-mA reverse current
without damaging the IC for logic upset. The input stage of each driver should be driven by a signal with a short
rise or fall time. This condition is satisfied in typical power supply applications where the input signals are
provided by a PWM controller or logic gates with fast transition times (
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