UCC27424QDRQ1

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 UCC2742x-Q1 Dual 4-A High-Speed Low-Side MOSFET Drivers With Enable 1 Features 3 Description • • The UCC2742x-Q1 family of devices are high-speed dual MOSFET drivers capable of delivering large peak currents into capacitive loads. Two standard logic options are offered: dual inverting and dual noninverting drivers. They are offered in the standard 8-pin SOIC (D) package. The thermally enhanced 8pin PowerPAD Package MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. 1 • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 Industry-Standard Pinout Enable Functions for Each Driver High-Current Drive Capability of ±4 A Unique Bipolar and CMOS True Drive Output Stage Provides High Current at MOSFET Miller Thresholds Inputs Independent of Supply Voltage Compatible With TTL and CMOS 20-ns Typical Rise and 15-ns Typical Fall Times With 1.8-nF Load Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns With Input Rising 4-V to 15-V Supply Voltage Dual Outputs Can Be Paralleled for Higher Drive Current Available in Thermally Enhanced MSOP PowerPAD™ Package Rated From –40°C to +125°C The UCC2742x-Q1 provide enable (ENBL) functions to have better control of the operation of the driver applications. ENBA and ENBB are implemented on pins 1 and 8, which were previously left unused in the industry standard pinout. They are internally pulled up to VDD for active-high logic and can be left open for standard operation. Device Information(1) PART NUMBER PACKAGE SOIC (8) UCC2742x-Q1 BODY SIZE (NOM) 4.90 mm × 3.91 mm MSOP 3.00 mm × 3.00 mm With PowerPAD (8) (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • Using a design that inherently minimizes shootthrough current, these drivers deliver 4-A current where it is needed most, at the Miller plateau region, during the MOSFET switching transition. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. Switch Mode Power Supplies DC-DC Converters Motor Controllers Line Drivers Class D Switching Amplifiers Block Diagram 8 ENBB 7 OUTA 6 VDD 5 OUTB ENBA 1 INVERTING INA 2 VDD NONINVERTING INVERTING GND 3 INB 4 NONINVERTING Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 5 5 5 5 6 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Dissipation Ratings ................................................... Typical Characteristics .............................................. Detailed Description ............................................ 14 8.1 Overview ................................................................. 14 8.2 Functional Block Diagram ....................................... 14 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 16 9 Application and Implementation ........................ 17 9.1 Application Information............................................ 17 9.2 Typical Application .................................................. 17 10 Power Supply Recommendations ..................... 21 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Layout Example .................................................... 22 11.3 Thermal Considerations ........................................ 22 12 Device and Documentation Support ................. 23 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 23 23 13 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (May 2016) to Revision H Page • Changed the UCC27424-Q1 pinout drawing to show two, noninverting channels ................................................................ 4 • Changed the units of the capacitors in the Parallel Outputs figure from mF to µF .............................................................. 15 • Added the Receiving Notification of Documentation Updates section ................................................................................. 23 Changes from Revision F (September 2012) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Added MSOP package information to Features and Description sections ........................................................................... 1 Changes from Revision E (July, 2012) to Revision F Page • Changed the word terminal to pin per new standards............................................................................................................ 4 • Removed derating factor column in dissipation ratings table, and changed the θJC value from 4.7 to 11.9, the θJA value from 50–59 to 63, and the power rating TA = 70°C (mW) value from 1370 to 873 for the DGN package. ................. 8 2 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 5 Device Comparison Table (1) (2) TA –40°C to 125°C (1) (2) CONFIGURATION ORDERABLE PART NUMBER TOP-SIDE MARKING Dual Inverting UCC27423QDGNRQ1 EADQ Dual Noninverting UCC27424QDGNRQ1 EPJQ Dual Inverting UCC27423QDRQ1 27423Q Dual Noninverting UCC27424QDRQ1 27424Q One Inverting, One Noninverting UCC27425QDRQ1 27425Q For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 3 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 6 Pin Configuration and Functions UCC27423-Q1: D or DGN Package 8-Pin SOIC or MSOP With PowerPAD Top View ENBA 1 8 ENBB INA 2 7 OUTA GND 3 UCC27424-Q1: D or DGN Package 8-Pin SOIC or MSOP With PowerPAD Top View ENBA 1 8 ENBB INA 2 7 OUTA GND 3 6 VDD 6 VDD INB 4 5 OUTB INB 4 Dual Inverting 5 OUTB Dual Noninverting UCC27425-Q1: D or Package 8-Pin SOIC Top View ENBA 1 8 ENBB INA 2 7 OUTA GND 3 6 VDD INB 4 5 OUTB One inverting, one noninverting Pin Functions PIN I/O DESCRIPTION ENBA I Enable input for the driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state. 2 INA I Input A. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating. 3 GND — Common ground. This ground must be connected very closely to the source of the power MOSFET which the driver is driving. 4 INB I Input B. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating. 5 OUTB O Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. 6 VDD — Supply voltage and the power input connection for this device. 7 OUTA O Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. 8 ENBB I Enable input for the driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state. NO. NAME 1 4 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VDD Supply voltage IOUT Output current VIN Input voltage MIN MAX UNIT –0.3 16 V DC 0.3 Pulsed, 0.5 µs 4.5 INA, INB A 6 (3) or (VDD + 0.3) (3) –5 V (3) 650 mW PD Power dissipation 3 W TJ Junction operating temperature –55 150 °C Tstg Storage temperature –65 150 °C (2) (3) –0.3 V Enable voltage (1) ENBA, ENBB 6 or (VDD + 0.3) (3) VEN TA = 25°C (D package) TA = 25°C (DGN package) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of, the specified terminal. Whichever is larger. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±1500 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VDD MIN MAX 4 15 V –2 15 V 0 15 V –40 125 °C Supply voltage INA Input voltage INB ENA ENB TJ Enable voltage Operating junction temperature UNIT 7.4 Thermal Information UCC2742x-Q1 THERMAL METRIC (1) D (SOIC) DGN (MSOP With PowerPAD) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 112.6 63 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61.5 53.8 °C/W RθJB Junction-to-board thermal resistance 52.8 35.6 °C/W ψJT Junction-to-top characterization parameter 15.8 1.9 °C/W ψJB Junction-to-board characterization parameter 52.3 35.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 11.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 5 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 7.5 Electrical Characteristics VDD = 4.5 V to 15 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT (INA, INB) VIH Logic 1 input threshold VIL Logic 0 input threshold IIN Input current 2 VIN = 0 V to VDD –10 V 1 V 10 μA 330 450 mV 22 40 mV 30 35 0 OUTPUT (OUTA, OUTB) IOUT Output current VDD = 14 V (1) VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA, VDD = 14 V VOL Low-level output voltage IOUT = 10 mA, VDD = 14 V ROH Output resistance high ROL Output resistance low (2) 4 TA = 25°C, IOUT = –10 mA, VDD = 14 V (3) 25 TA = full range, IOUT = –10 mA, VDD = 14 V (3) 18 TA = 25°C, IOUT = 10 mA, VDD = 14 V (3) 1.9 TA = full range, IOUT = 10 mA, VDD = 14 V (3) 1.2 Latch-up protection (1) A 45 2.2 2.5 4 500 Ω Ω mA ENABLE (ENBA, ENBB) VIN_H High-level input voltage Low-to-high transition 1.7 2.4 2.9 V VIN_L Low-level input voltage High-to-low transition 1.1 1.8 2.2 V 0.15 0.55 0.9 V 75 100 145 kΩ INB = 0 V 900 1350 INB = High 750 1100 INB = 0 V 750 1100 INB = High 600 900 INB = 0 V 300 450 INB = High 750 1100 INB = 0 V 750 1100 INB = High 1200 1800 INB = 0 V 600 900 INB = High 1050 1600 INB = 0 V 450 700 INB = High 900 1350 INB = 0 V 300 450 INB = High 450 700 INB = 0 V 450 700 INB = High 600 900 Hysteresis RENBL Enable impedance VDD = 14 V, ENBL = GND OVERALL INA = 0 V UCC27423-Q1 INA = High INA = 0 V Static, VDD = 15 V, ENBA = ENBB = 15 V UCC27424-Q1 INA = High IDD Operating current INA = 0 V UCC27425-Q1 INA = High INA = 0 V Disabled, VDD = 15 V, ENBA = ENBB = 0 V All INA = High (1) (2) (3) 6 µA Specified by design The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SWITCHING TIME tr Rise time (OUTA, OUTB) CLOAD = 1.8 nF (1) 20 40 ns tf Fall time (OUTA, OUTB) CLOAD = 1.8 nF (1) 15 40 ns tD1 Delay time, IN rising (IN to OUT) CLOAD = 1.8 nF (1) 25 50 ns tD2 Delay time, IN falling (IN to OUT) CLOAD = 1.8 nF (1) UCC27423-Q1, UCC27424-Q1 35 60 UCC27425-Q1 35 70 ns ENABLE (ENBA, ENBB) tD3 Propagation delay time (2) CLOAD = 1.8 nF (1) (3) 30 60 ns tD4 Propagation delay time (2) CLOAD = 1.8 nF (1) (3) 100 150 ns (1) (2) (3) Specified by design See Figure 2 Not production tested (a) (b) +5V 90% 90% INPUT 0V INPUT 10% 10% td1 16V OUTPUT tf tf 90% 90% 0V tf td2 tf 90% td1 td2 OUTPUT 10% 10% The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 7 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 5V ENBx VIN_L VIN_H 0V td3 td4 VDD 90% 90% tf tr OUTx 10% 0V The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveform for Enable to Output 7.7 Dissipation Ratings (1) (2) (3) 8 PACKAGE θJC (°C/W) θJA (°C/W) POWER RATING TA = 70°C (mW) (1) D (SOIC-8) 42 84 to 160 (2) 344 to 655 (2) DGN (MSOP PowerPAD) (3) 11.9 63 873 125°C operating junction temperature is used for power rating calculations. The range of values indicates the effect of the PCB. These values are intended to give the system designer an indication of the bestand worst-case conditions. In general, the system designer should attempt to use larger traces on the PCB, where possible, to spread the heat away form the device more effectively. The PowerPAD is not directly connected to any leads of the package. However, it is electronically and thermally connected to the substrate which is the ground of the device. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 7.8 Typical Characteristics 100 100 80 10 nF IDD − Supply Current − mA IDD − Supply Current − mA 80 60 4.7 nF 40 2.2 nF 20 10 nF 4.7 nF 60 40 2.2 nF 1 nF 20 1 nF 470 pF 0 0 470 pF 0 500 K 1M 1.5 M 0 2M 1M 1.5 M VDD = 4.5 V VDD = 8 V Figure 3. Supply Current vs Frequency Figure 4. Supply Current vs Frequency 150 100 10 nF IDD − Supply Current − mA 200 4.7 nF 2.2 nF 50 1 nF 150 10 nF 4.7 nF 100 2.2 nF 50 1 nF 470 pF 470 pF 0 0 0 500 K 1M 1.5 M 0 2M 500 K 1M 1.5 M 2M f - Frequency − Hz f - Frequency − Hz VDD = 15 V VDD = 12 V Figure 6. Supply Current vs Frequency Figure 5. Supply Current vs Frequency 160 90 80 140 2 MHz 70 120 IDD − Supply Current − mA IDD − Supply Current − mA 2M f - Frequency − Hz f - Frequency − Hz IDD − Supply Current − mA 500 K 60 50 1 MHz 40 30 500 kHz 20 2 MHz 100 1 MHz 80 60 500 kHz 40 200 kHz 200 kHz 20 10 100 kHz 100/50 kHz 0 50/20 kHz 0 4 6 8 10 12 14 16 VDD − Supply Voltage − V CLOAD = 2.2 nF Figure 7. Supply Current vs Supply Voltage Copyright © 2008–2016, Texas Instruments Incorporated 4 9 14 19 VDD − Supply Voltage − V CLOAD = 4.7 nF Figure 8. Supply Current vs Supply Voltage Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 9 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Typical Characteristics (continued) 0.60 0.9 0.55 Input = V DD Input = VDD I DD − Supply Current − mA IDD − Supply Current − mA 0.8 0.7 0.6 0.5 0.50 Input = 0 V 0.45 0.40 0.35 0.4 Input = 0 V 0.30 0.3 4 6 8 10 12 14 4 16 VDD − Supply Voltage − V 6 8 10 12 VDD − Supply Voltage − V 14 16 Figure 10. Supply Current vs Supply Voltage (UCC27424) Figure 9. Supply Current vs Supply Voltage (UCC274323) 0.75 0.70 ns IDD - Supply Current - mA 0.65 Input = VDD 0.60 0.55 0.50 Input = 0 V 0.45 0.40 0.35 0.30 4 6 8 10 12 14 16 VDD - Supply Voltage - V Figure 11. Supply Current vs Supply Voltage (UCC27425-Q1) ns ns Figure 12. Rise Time and Fall Time Temperature (UCC27423) Figure 13. Rise Time vs Supply Voltage 10 Submit Documentation Feedback Figure 14. Fall Time vs Supply Voltage Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 Typical Characteristics (continued) 38 30 28 36 10 nF 34 10 nF 24 22 td2 − Delay Time − ns td1 − Delay Time − ns 26 4.7 nF 20 18 2.2 nF 16 32 4.7 nF 30 28 2.2 nF 26 470 pF 24 1 nF 470 pF 14 22 1 nF 12 20 4 6 8 10 12 14 16 4 6 10 12 14 16 Figure 16. Delay Time (tD2) vs Supply Voltage (UCC27423) Figure 15. Delay Time (tD1) vs Supply Voltage (UCC27423) 150 3.0 140 ENBL − ON 2.5 RENBL − Enable Resistance − W Enable threshold and hysteresis − V 8 VDD − Supply Voltage − V VDD − Supply Voltage − V 2.0 1.5 1.0 ENBL − OFF 130 120 110 100 90 80 70 0.5 60 ENBL − HYSTERESIS 0 −50 −25 0 25 50 75 TJ − Temperature − °C 100 50 −50 125 −25 0 25 50 75 125 Figure 18. Enable Resistance vs Temperature Figure 17. Enable Threshold and Hysteresis vs Temperature IN = GND ENBL = VDD VDD − Supply Voltage − V 1 V/div IN = GND ENBL = VDD VDD − Supply Voltage − V 1 V/div 100 TJ − Temperature − °C VDD VDD OUT 0V 0V 10 nF Between Output and GND 50 ms/div Figure 19. Output Behavior vs Supply Voltage (Inverting) Copyright © 2008–2016, Texas Instruments Incorporated OUT 10 nF Between Output and GND 50 ms/div Figure 20. Output Behavior vs Supply Voltage (Inverting) Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 11 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Typical Characteristics (continued) IN = VDD ENBL = VDD VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = VDD ENBL = VDD VDD OUT VDD OUT 0V 0V 10 nF Between Output and GND 50 ms/div 10 nF Between Output and GND 50 ms/div Figure 21. Output Behavior vs VDD (Inverting) Figure 22. Output Behavior vs VDD (Inverting) IN = VDD ENBL = VDD VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = VDD ENBL = VDD VDD VDD OUT OUT 0V 0V 10 nF Between Output and GND 50 ms/div 10 nF Between Output and GND 50 ms/div Figure 23. Output Behavior vs VDD (Noninverting) Figure 24. Output Behavior vs VDD (Noninverting) VDD OUT 0V 12 IN = GND ENBL = VDD VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = GND ENBL = VDD VDD OUT 0V 10 nF Between Output and GND 50 ms/div 10 nF Between Output and GND 50 ms/div Figure 25. Output Behavior vs VDD (Noninverting) Figure 26. Output Behavior vs VDD (Noninverting) Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 Typical Characteristics (continued) VON − Input Threshold Voltage − V 2.0 1.9 VDD = 15 V 1.8 1.7 1.6 1.5 VDD = 10 V VDD = 4.5 V 1.4 1.3 1.2 −50 −25 0 25 50 75 100 125 TJ − Temperature − °C Figure 27. Input Threshold vs Temperature Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 13 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The UCC2742x-Q1 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. The UCC27423-Q1 offers these standard logic options: dual-inverting drivers, dual noninverting drivers, and one inverting, one noninverting driver. The thermally enhanced 8-pin PowerPAD MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard 8-pin SOIC (D) package. Using a design that inherently minimizes shoot-through current, these drivers deliver 4 A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. 8.2 Functional Block Diagram 8 ENBB 7 OUTA 6 VDD 5 OUTB ENBA 1 INVERTING INA 2 VDD NONINVERTING INVERTING GND 3 INB 4 NONINVERTING Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Input Stage The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages; yet it is equally compatible with 0 to VDD signals. The inputs of UCC2742x-Q1 drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (< 200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in the Thermal Considerations section. 8.3.2 Output Stage Inverting outputs of the UCC2742x-Q1 are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC2742x-Q1 are intended to drive external N-channel MOSFETs. 14 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 Feature Description (continued) Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external Schottky-clamp diodes are not required. The UCC2742x-Q1 family delivers the 4-A gate drive where it is most needed during the MOSFET switching transition—at the Miller plateau region—providing improved efficiency gains. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages. 8.3.3 Enable UCC2742x-Q1 provide dual enable inputs for improved control of each driver channel operation. The inputs incorporate logic-compatible thresholds with hysteresis. They are internally pulled up to VDD with 100-kΩ resistor for active-high operation. When ENBA and ENBB are driven high, the drivers are enabled; when ENBA and ENBB are low, the drivers are disabled. The default state of the enable pin is to enable the driver and, therefore, can be left open for standard operation. The output states when the drivers are disabled is low, regardless of the input state. See Table 1 for operation using enable logic. Enable inputs are compatible with both logic signals and slowly-changing analog signals. They can be directly driven, or a power-up delay can be programmed with a capacitor between ENBA/ENBB and GND. ENBA and ENBB control input A and input B, respectively. 8.3.4 Parallel Outputs The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 28. VDD INPUT UCC27423-Q1 ENBA 1 ENBB 2 INA OUTA 3 GND 4 INB VDD OUTB 8 7 6 CLOAD 5 1 µF CER 2.2 µF Copyright © 2016, Texas Instruments Incorporated Figure 28. Parallel Outputs 8.3.5 Operational Waveforms and Circuit Layout Figure 29 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF load. The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 15 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Feature Description (continued) Figure 29. Pulse Response In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot or undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Use the upmost care in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the opposite side of the output, so the ground must be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections must also be made with a small enclosed loop area to minimize the inductance. 8.3.6 VDD Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 1. IOUT = Qg × f where • f is frequency (1) For the best high-speed circuit performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI highly recommends using surface-mount components. A 0.1-µF ceramic capacitor must be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1 µF) with relatively low ESR must be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors must present a low impedance characteristic for the expected current levels in the driver application. 8.4 Device Functional Modes With VDD power supply in the range of 4 V to 16 V, the output stage is dependent on the states of the HI and LI pins. Table 1 shows the UCC2742x-Q1 truth table. Table 1. Input and Output Logic Table ENBA ENBB H INPUTS (VIN_L, VIN_H) UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 INA INB OUTA OUTB OUTA OUTB OUTA H L L H H L L H OUTB L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L X X L L L L L L Importantly, if INA and INB are not used, they must be tied to either VDD or GND; they must not be left floating. 16 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information High-frequency power supplies often require high-speed, high-current drivers such as the UCC2742x-Q1 family. A leading application is the need to provide a high-power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is used to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. Driver ICs are used when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases, there may be a desire to minimize the effect of high-frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC2742xQ1. Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. 9.2 Typical Application ENBB UCC2742x-Q1 ENBA 1 ENBA ENBB 8 INA 2 INA OUTA 7 3 GND VDD 6 4 INB OUTB 5 V+ GND INB GND GND Copyright © 2016, Texas Instruments Incorporated Figure 30. UCC2742x-Q1 Driving Two Independent MOSFETs 9.2.1 Design Requirements To select proper device from UCC2742x-Q1 family, TI recommends first checking the appropriate logic for the outputs. The UCC27423-Q1 has dual inverting outputs, the UCC27424-Q1 has dual noninverting outputs, and the UCC27425-Q1 has an inverting channel A and noninverting channel B. Moreover, evaluate some considerations to make the most appropriate selection. Among these considerations are VDD, drive current, and power dissipation. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 17 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 Source and Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC2742x-Q1 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging and discharging of the draingate capacitance with current supplied or removed by the driver device. Two circuits are used to test the current capabilities of the UCC2742x-Q1 driver. In each case, external circuitry is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test, there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The circuit in Figure 31 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC2742x-Q1 is found to sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V. VDD UCC2742x-Q1 1 ENBA ENBB 8 DSCHOTTKY 2 INA OUTA 10 7 C2 1 F Signal generator producing 250-ns wide pulse 3 GND VDD C3 100 F + VADJ 5.5 V 6 VSNS 4 INB OUTB 5 RSNS 0.1 1 F CER 100 F AL EL Copyright © 2016, Texas Instruments Incorporated Figure 31. Current Sink Capability Test The circuit show in Figure 32 is used to test the current source capability with the output clamped around 5 V with a string of Zener diodes. The UCC2742x-Q1 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V. 18 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 Typical Application (continued) VDD UCC2742x-Q1 1 ENBA ENBB 8 2 INA OUTA 7 DSCHOTTKY Signal Generator 10 C2 1 F 3 GND VDD C3 100 F 4.5 V 6 VSNS 250 ns INB 4 OUTB 5 RSNS 0.1 1 F CER 100 F AL EL Copyright © 2016, Texas Instruments Incorporated Figure 32. Current Source Capability Test 9.2.2.2 Drive Current and Power Requirements The UCC2742x-Q1 family of drivers are capable of delivering 4 A of current to a MOSFET gate for a period of several hundred nanoseconds. High-peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. Reference 1 in the Related Documentation section discuss the current required to drive a power MOSFET and other capacitive-input switching devices. Reference 1 in includes information on the previous generation of bipolar IC gate drivers. When a driver IC is tested with a discrete, capacitive load, it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2. E + 1 CV 2 2 where • • C = load capacitor V = bias voltage (feeding the driver) (2) There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by Equation 3. P = CV2 × f where • f = switching frequency (3) This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as Equation 4. P = 10 nF × (12 V)2 × (300 kHz) = 0.432 W (4) With a 12-V supply, this would equate to a current of Equation 5. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 19 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com Typical Application (continued) I= P 0.432 W = = 36 mA V 12 V (5) The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, consider the IDD current that is due to the IC internal consumption. With no load, the IC current draw is 0.0027 A. Under this condition, the output rise and fall times are faster than with a load. This could lead to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high-frequency switching spikes, and are beyond the measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to that expected. The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the power loss in Equation 6. P = C × V2 × f = V × Qg × f (6) Equation 6 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. 9.2.3 Application Curves Figure 33 and Figure 34 show rising and falling time and turnon and turnoff propagation delay testing waveform in room temperature for UCC27424-Q1, and waveform measurement data (see the bottom part of the waveform). Each channel, INA/INB/OUTA/OUTB, is labeled and displayed on the left hand of the waveforms. The load capacitance testing condition is 1.8 nF, VDD = 12 V, and f = 300 kHz. HI and LI share one same input from function generator; therefore, besides the propagation delay and rising or falling time, the difference of the propagation delay between HO and LO gives the propagation delay matching data. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. CL = 1.8 nF, VDD = 12 V, f = 300 kHz Figure 33. Rising Time and Turnon Propagation Delay 20 Submit Documentation Feedback CL = 1.8 nF, VDD = 12 V, f = 300 kHz Figure 34. Falling Time and Turnoff Propagation Delay Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 10 Power Supply Recommendations The recommended bias supply voltage range for UCC2742x-Q1 is from 4 V to 15 V. The upper end of this range is driven by the absolute maximum voltage rating of the VDD (16 V). TI recommends keeping proper margin to allow for transient voltage spikes. A local bypass capacitor must be placed between the VDD and GND pins. And this capacitor must be placed as close to the device as possible. A low ESR, ceramic surface-mount capacitor is recommended. TI recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high-frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor (220 nF to 10 μF) for IC bias requirements. 11 Layout 11.1 Layout Guidelines Optimum performance of gate drivers cannot be achieved without taking due considerations during circuit board layout. The following points are emphasized: 1. Low ESR or ESL capacitors must be connected close to the IC between VDD and GND pins to support high peak currents drawn from VDD during the turnon of the external MOSFETs. 2. Grounding considerations: – The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This decreases the loop inductance and minimizes noise issues on the gate terminals of the MOSFETs. The gate driver must be placed as close as possible to the MOSFETs. – Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM controller at one, single point. The connected paths must be as short as possible to reduce inductance. – Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well. 3. In noisy environments, tying inputs of an unused channel of the UCC2742x-Q1 device to VDD or GND using short traces in order to ensure that the output is enabled and to prevent noise from causing malfunction in the output may be necessary. 4. Separate power traces and signal traces, such as output and input signals. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 21 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 11.2 Layout Example Ground plane UCC2742x-Q1 Figure 35. Recommended PCB Layout for UCC2742x-Q1 11.3 Thermal Considerations The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the IC package. For a power driver to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2742x-Q1 family of drivers is available in three different packages to cover a range of application requirements. As shown in the power dissipation rating table, the 8-pin SOIC (D) package has a power rating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the Dissipation Ratings table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus, only one load of this size could be driven using the D package, even if the two onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages. The 8-pin MSOP with PowerPAD (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As described in reference 2 of the Related Documentation section, the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PCB directly underneath the IC package, reducing the RθJC(bot) down to 5.9°C/W. Data is presented in reference 2 of Related Documentation to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PCB must be designed with thermal lands and thermal vias to complete the heat removal subsystem. This allows a significant improvement in heat sinking over that available in the D package, and is shown to more than double the power capability of the D package. Note that the PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. 22 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 www.ti.com SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: 1. Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits (SLUA105) 2. PowerPad Thermally Enhanced Package (SLMA002) 3. PowerPAD Made Easy (SLMA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY UCC27423-Q1 Click here Click here Click here Click here Click here UCC27424-Q1 Click here Click here Click here Click here Click here UCC27425-Q1 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 23 UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 SGLS274H – SEPTEMBER 2008 – REVISED OCTOBER 2016 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC27423QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 EADQ UCC27423QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27423Q UCC27424QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 EPJQ UCC27424QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27424Q UCC27425QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27425Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of