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UCC27523, UCC27524, UCC27525, UCC27526
SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
UCC2752x Dual 5-A High-Speed, Low-Side Gate Driver
1 Features
3 Description
•
•
•
•
•
The UCC2752x family of devices are dual-channel,
high-speed, low-side gate-driver devices capable of
effectively driving MOSFET and IGBT power
switches. Using a design that inherently minimizes
shoot-through current, UCC2752x can deliver highpeak current pulses of up to 5-A source and 5-A sink
into capacitive loads along with rail-to-rail drive
capability and extremely small propagation delay
(typically 13 ns). In addition, the drivers feature
matched internal propagation delays between the two
channels. These delays are very well suited for
applications requiring dual-gate drives with critical
timing, such as synchronous rectifiers. This also
enables connecting two channels in parallel to
effectively increase current-drive capability or driving
two switches in parallel with one input signal. The
input pin thresholds are based on TTL and CMOS
compatible low-voltage logic, which is fixed and
independent of the VDD supply voltage. Wide
hysteresis between the high and low thresholds offers
excellent noise immunity.
Industry-Standard Pinout
Two Independent Gate-Drive Channels
5-A Peak Source and Sink-Drive Current
Independent-Enable Function for Each Output
TTL and CMOS Compatible Logic Threshold
Independent of Supply Voltage
Hysteretic-Logic Thresholds for High Noise
Immunity
Inputs and Enable Pin-Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage
4.5-V to 18-V Single-Supply Range
Outputs Held Low During VDD-UVLO, (Ensures
Glitch-Free Operation at Power up and Power
Down)
Fast Propagation Delays (13-ns Typical)
Fast Rise and Fall Times (7-ns and 6-ns Typical)
1-ns Typical Delay Matching Between Two
Channels
Two Outputs are in Parallel for Higher Drive
Current
Outputs Held Low When Inputs Floating
PDIP (8), SOIC (8), MSOP (8) PowerPAD™ and
3-mm × 3-mm WSON-8 Package Options
Operating Temperature Range of –40°C to 140°C
1
•
•
•
•
•
•
•
•
•
•
•
PART NUMBER
Switched-Mode Power Supplies
DC-DC Converters
Motor Control, Solar Power
Gate Drive for Emerging Wide Band-Gap Power
Devices such as GaN
PACKAGE
BODY SIZE (NOM)
SOT-23 (8)
UCC27523
4.90 mm × 3.91 mm
HVSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
SOT-23 (8)
UCC27524
2 Applications
•
•
•
•
Device Information(1)
UCC27525
4.90 mm × 3.91 mm
HVSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
PDIP (8)
9.81 mm × 6.35 mm
SOT-23 (8)
4.90 mm × 3.91 mm
HVSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
UCC27526
WSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pin Configuration
Dual Inverting Inputs
Dual Non-Inverting Inputs
One Inverting and One
Non-Inverting Input
UCC27523
UCC27524
UCC27525
Dual Input Configuration
UCC27526
8
ENB
INA
2
7
OUTA
GND
3
6
VDD
INB
4
5
OUTB
ENA
1
8
ENB
INA
2
7
OUTA
GND
3
6
VDD
INB
4
5
OUTB
8
INA+
7
INB+
3
6
OUTA
4
5
VDD
ENA
1
8
ENB
INA
2
7
OUTA
INB-
2
GND
3
6
VDD
GND
INB
4
5
OUTB
OUTB
+
1
1
+
ENA
INA-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27523, UCC27524, UCC27525, UCC27526
SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
6
6
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagrams ..................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
11.3 Thermal Considerations ........................................ 27
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May, 2013) to Revision G
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed UCC2752X Gate Driver Output Structure image. ................................................................................................. 17
Changes from Revision E (June 2012) to Revision F
•
Page
Added 0.5 to PSW equation in Drive Current and Power Dissipation section ....................................................................... 24
Changes from Revision D (April 2012) to Revision E
Page
•
Added OUTA, OUTB voltage field and values. ...................................................................................................................... 6
•
Changed table note from "Values are verified by characterization and are not production tested." to "Values are
verified by characterization on bench."................................................................................................................................... 6
•
Added note, "Values are verified by characterization and are not production tested." .......................................................... 6
•
Changed Switching Time tPW values from 10 ns and 25 ns to 15 ns and 25 ns ns. .............................................................. 7
•
Changed Functional Block Diagrams images....................................................................................................................... 12
•
Changed Slow Input Signal Figure 33.................................................................................................................................. 18
2
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Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526
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SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
Changes from Revision C (March 2012) to Revision D
Page
•
Changed Inputs (INA, INB, INA+, INA–, INB+, INB-) section to include UCC2752X (D, DGN, DSD) information. ............... 7
•
Added Inputs (INA, INB, INA+, INA-, INB+, INB-) UCC27524P ONLY section. .................................................................... 7
•
Changed Enable (ENA, ENB) section to include UCC2752X (D, DGN, DSD) information.................................................... 7
•
Added ENABLE (ENA, ENB) UCC27524P ONLY section. .................................................................................................... 7
Changes from Revision B ( December 2011) to Revision C
Page
•
Added ROH note in the Outputs (OUTA, OUTB) section. ....................................................................................................... 7
•
Added an updated Output Stage section. ............................................................................................................................ 17
•
Added UCC2752X Gate Driver Output Structure image ...................................................................................................... 17
•
Added an updated Low Propagation Delays and Tightly Matched Outputs section. ........................................................... 18
•
Added Slow Input Signal Combined with Differences in Input Threshold Voltage image. ................................................... 18
•
Added updated Drive Current and Power Dissipation section. ............................................................................................ 23
•
Added a PSW... equation. .................................................................................................................................................... 24
Changes from Revision A (November 2011) to Revision B
Page
•
Changed Supply start threshold row to include two temperature ranges............................................................................... 7
•
Changed Minimum operating voltage after supply start min and max values from 3.6 V to 4.2 V to 3.40 V and 4.40 V. ..... 7
•
Changed Supply voltage hysteresis typ value from 0.35 to 0.30. .......................................................................................... 7
•
Changed UCC27526 Block Diagram drawing. ..................................................................................................................... 13
•
Changed UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration drawing. ............................... 21
Changes from Original (November 2011) to Revision A
•
Page
Changed data sheet status to Production Data...................................................................................................................... 1
Copyright © 2011–2015, Texas Instruments Incorporated
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3
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SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
www.ti.com
5 Description (continued)
The UCC2752x family provide the combination of three standard logic options — dual inverting, dual
noninverting, one inverting and one noninverting driver. UCC27526 features a dual input design which offers
flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN–
pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For
safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family
ensure that outputs are held LOW when input pins are in floating condition. The UCC27523, UCC27524, and
UCC27525 devices feature Enable pins (ENA and ENB) to have better control of the operation of the driver
applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard
operation.
UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm
WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is
only offered in 3-mm × 3-mm WSON (DSD) package.
6 Pin Configuration and Functions
D, DGN, or P Package UCC2752(3,4,5)
8-Pin SOT-23, HVSSOP, or PDIP
Top View
ENA 1
8
INA 2
7
GND 3
6
INB 4
5
DSD Package UCC2752(3,4,5)
8-Pin WSON
Top View
ENB
ENA
1
8
ENB
INA
2
7
OUTA
GND
3
6
VDD
INB
4
5
OUTB
OUTA
VDD
OUTB
DSD Package UCC27526
8-Pin WSON
Top View
4
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INA-
1
8
INA+
INB-
2
7
INB+
GND
3
6
OUTA
OUTB
4
5
VDD
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526
UCC27523, UCC27524, UCC27525, UCC27526
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SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
Pin Functions (UCC27523 / UCC27524 / UCC27525)
PIN
NO.
NAME
I/O
DESCRIPTION
1
ENA
I
Enable input for Channel A: ENA biased LOW Disables Channel A output regardless of INA state,
ENA biased HIGH or floating Enables Channel A output, ENA allowed to float hence the pin-to-pin
compatibility with UCC2732X N/C pin.
2
INA
I
Input to Channel A: Inverting Input in UCC27523, Non-Inverting Input in UCC27524, Inverting
Input in UCC27525, OUTA held LOW if INA is unbiased or floating.
3
GND
-
Ground: All signals referenced to this pin.
4
INB
I
Input to Channel B: Inverting Input in UCC27523, Non-Inverting Input in UCC27524, Non-Inverting
Input in UCC27525, OUTB held LOW if INB is unbiased or floating.
5
OUTB
O
Output of Channel B
6
VDD
I
Bias supply input
7
OUTA
O
Output of Channel A
8
ENB
I
Enable input for Channel B: ENB biased LOW Disables Channel B output regardless of INB state,
ENB biased HIGH or floating Enables Channel B output, ENB allowed to float hence the pin-to-pin
compatibility with UCC2732X N/C pin.
Pin Functions (UCC27526)
PIN
NO.
NAME
I/O
DESCRIPTION
1
INA–
I
Inverting Input to Channel A: When Channel A is used in Non-Inverting configuration, connect
INA– to GND in order to Enable Channel A output, OUTA held LOW if INA– is unbiased or floating.
2
INB–
I
Inverting Input to Channel B: When Channel B is used in Non-Inverting configuration, connect
INB– to GND in order to Enable Channel B output, OUTB held LOW if INB– is unbiased or floating.
3
GND
-
Ground: All signals referenced to this pin.
4
OUTB
I
Output of Channel B
5
VDD
O
Bias Supply Input
6
OUTA
I
Output of Channel A
7
INB+
O
Non-Inverting Input to Channel B: When Channel B is used in Inverting configuration, connect
INB+ to VDD in order to Enable Channel B output, OUTB held LOW if INB+ is unbiased or floating.
8
INA+
I
Non-Inverting Input to Channel A: When Channel A is used in Inverting configuration, connect
INA+ to VDD in order to Enable Channel A output, OUTA held LOW if INA+ is unbiased or floating.
Copyright © 2011–2015, Texas Instruments Incorporated
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
Supply voltage
OUTA, OUTB voltage
MIN
MAX
VDD
–0.3
20
DC
–0.3
VDD + 0.3
–2
VDD + 0.3
Repetitive pulse < 200 ns (3)
Output continuous source/sink
current
IOUT_DC
Output pulsed source/sink current
(0.5 µs)
IOUT_pulsed
A
5
–0.3
20
Operating virtual junction temperature, TJ
–40
150
Lead temperature
Soldering, 10 s
300
Reflow
260
Storage temperature, Tstg
(2)
(3)
(4)
V
0.3
INA, INB, INA+, INA–, INB+, INB–, ENA, ENB voltage (4)
(1)
UNIT
–65
V
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Mechanical, Packaging, and Orderable Information for thermal limitations and considerations of packages.
Values are verified by characterization on bench.
The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage, VDD
4.5
12
18
V
Operating junction temperature
–40
140
°C
Input voltage, INA, INB, INA+, INA–, INB+, INB–
0
18
V
Enable voltage, ENA and ENB
0
18
7.4 Thermal Information
UCC27523/4/5
THERMAL METRIC
RθJA
(1)
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
UCC27524
UCC27523/4/5/6
SOIC (D)
MSOP (DGN)
PDIP (P)
WSON (DSD)
8 PINS
8 PINS
8 PINS
8 PINS
130.9
71.8
62.1
46.7
80
65.6
52.7
46.7
RθJB
Junction-to-board thermal resistance
71.4
7.4
39.1
22.4
ψJT
Junction-to-top characterization parameter
21.9
7.4
31
0.7
ψJB
Junction-to-board characterization parameter
70.9
31.5
39.1
22.6
–
19.6
–
9.5
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1)
6
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
7.5 Electrical Characteristics
VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal (unless otherwise noted,)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
VDD = 3.4 V,
INA = VDD,
INB = VDD
55
110
175
VDD = 3.4 V,
INA = GND,
INB = GND
25
75
145
3.91
4.2
4.5
UNIT
BIAS CURRENTS
IDD(off)
Start-up current,
(based on UCC27524 Input
configuration)
μA
UNDERVOLTAGE LOCKOUT (UVLO)
TJ = 25°C
VON
Supply start threshold
3.7
4.2
4.65
VOFF
Minimum operating voltage
after supply start
3.4
3.9
4.4
VDD_H
Supply voltage hysteresis
0.2
0.3
0.5
1.9
2.1
2.3
1
1.2
1.4
0.7
0.9
1.1
TJ = –40°C to 140°C
V
INPUTS (INA, INB, INA+, INA–, INB+, INB–), UCC2752X (D, DGN, DSD)
VIN_H
Input signal high threshold
Output high for non-inverting input pins
Output low for inverting input pins
VIN_L
Input signal low threshold
Output low for non-inverting input pins
Output high for inverting input pins
VIN_HYS
Input hysteresis
V
INPUTS (INA, INB, INA+, INA–, INB+, INB–) UCC27524P ONLY
VIN_H
Input signal high threshold
Output high for non-inverting input pins
Output low for inverting input pins
VIN_L
Input signal low threshold
Output low for non-inverting input pins
Output high for inverting input pins
VIN_HYS
Input hysteresis
2.3
V
1
0.9
ENABLE (ENA, ENB) UCC2752X (D, DGN, DSD)
VEN_H
Enable signal high threshold
Output enabled
1.9
2.1
2.3
VEN_L
Enable signal low threshold
Output disabled
0.95
1.15
1.35
VEN_HYS
Enable hysteresis
0.7
0.95
1.1
V
ENABLE (ENA, ENB) UCC27524P ONLY
VEN_H
Enable signal high threshold
Output enabled
VEN_L
Enable signal low threshold
Output disabled
VEN_HYS
Enable hysteresis
2.3
0.95
V
0.95
OUTPUTS (OUTA, OUTB)
ISNK/SRC
Sink/source peak current (1)
CLOAD = 0.22 µF, FSW = 1 kHz
VDD-VOH
High output voltage
IOUT = –10 mA
0.075
VOL
Low output voltage
IOUT = 10 mA
0.01
ROH
Output pullup resistance (2)
IOUT = –10 mA
2.5
5
7.5
Ω
ROL
Output pulldown resistance
IOUT = 10 mA
0.15
0.5
1
Ω
(1)
(2)
±5
A
V
Ensured by design.
ROH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC2752X output stage.
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7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
tR
Rise time
CLOAD = 1.8 nF
7
18
tF
Fall time (1)
CLOAD = 1.8 nF
6
10
tM
Delay matching between 2 channels
INA = INB, OUTA and OUTB at 50%
transition point
1
4
tPW
Minimum input pulse width that
changes the output state
15
25
tD1, tD2
Input to output propagation delay
tD3, tD4
(1)
EN to output propagation delay
(1)
(1)
ns
CLOAD = 1.8 nF, 5-V input pulse
6
13
23
CLOAD = 1.8 nF, 5-V enable pulse
6
13
23
See timing diagrams in Figure 1, Figure 2, Figure 3, and Figure 4
High
High
Input
Input
Low
Low
High
High
Enable
Enable
Low
Low
90%
90%
Output
Output
10%
10%
tD3
tD4
tD3
UDG-11217
Figure 1. Enable Function
(For Non-Inverting Input Driver Operation)
tD4
UDG-11218
Figure 2. Enable Function
(For Inverting Input Driver Operation)
High
High
Input
Input
Low
Low
High
High
Enable
Enable
Low
Low
90%
90%
Output
Output
10%
10%
tD1
tD2
UDG-11219
Figure 3. Non-Inverting Input Driver Operation
8
UNIT
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tD1
tD2
UDG-11220
Figure 4. Inverting Input Driver Operation
Copyright © 2011–2015, Texas Instruments Incorporated
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SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015
7.7 Typical Characteristics
4
Operating Supply Current (mA)
Startup Current (mA)
0.14
Input=VDD
Input=GND
0.12
0.1
0.08
3.5
3
VDD = 12 V
fSW = 500 kHz
CL = 500 pF
VDD=3.4V
0.06
−50
0
50
Temperature (°C)
100
2.5
−50
150
Figure 5. Start-Up Current vs Temperature
UVLO Threshold (V)
Supply Current (mA)
150
G002
UVLO Rising
UVLO Falling
0.5
0.4
0.3
Enable=12 V
VDD = 12 V
0
50
Temperature (°C)
100
4.5
4
3.5
3
−50
150
0
G012
Figure 7. Supply Current vs Temperature (Outputs in DC
ON/OFF Condition)
2
2
Enable Threshold (V)
2.5
VDD = 12 V
1.5
1
50
Temperature (°C)
50
Temperature (°C)
100
Figure 9. Input Threshold vs Temperature
Copyright © 2011–2015, Texas Instruments Incorporated
150
G003
VDD = 12 V
1.5
1
Input High Threshold
Input Low Threshold
0
100
Figure 8. UVLO Threshold vs Temperature
2.5
0.5
−50
100
5
Input=GND
Input=VDD
Input Threshold (V)
50
Temperature (°C)
Figure 6. Operating Supply Current vs Temperature
(Outputs Switching)
0.6
0.2
−50
0
G001
Enable High Threshold
Enable Low Threshold
150
G004
0.5
−50
0
50
Temperature (°C)
100
150
G005
Figure 10. Enable Threshold vs Temperature
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Typical Characteristics (continued)
1
VDD = 12 V
IOUT = −10 mA
Output Pull−down Resistance (Ω)
Output Pull−up Resistance (Ω)
7
6
5
4
3
−50
0
50
Temperature (°C)
100
VDD = 12 V
IOUT = 10 mA
0.8
0.6
0.4
0.2
−50
150
Figure 11. Output Pullup Resistance vs Temperature
Fall Time (ns)
Rise Time (ns)
G007
8
8
7
7
6
6
0
50
Temperature (°C)
100
5
−50
150
0
G008
Figure 13. Rise Time vs Temperature
50
Temperature (°C)
100
150
G009
Figure 14. Fall Time vs Temperature
18
18
Turn−on
Turn−off
EN to Output Propagation Delay (ns)
Input to Output Propagation Delay (ns)
150
VDD = 12 V
CLOAD = 1.8 nF
9
16
14
12
10
VDD = 12 V
CLOAD = 1.8 nF
0
50
Temperature (°C)
100
150
Figure 15. Input to Output Propagation Delay vs
Temperature
10
100
9
VDD = 12 V
CLOAD = 1.8 nF
8
−50
50
Temperature (°C)
Figure 12. Output Pulldown Resistance vs Temperature
10
5
−50
0
G006
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G010
EN to Output High
EN to Output Low
16
14
12
10
VDD = 12 V
CLOAD = 1.8 nF
8
−50
0
50
Temperature (°C)
100
150
G011
Figure 16. EN to Output Propagation Delay vs Temperature
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Typical Characteristics (continued)
22
VDD = 4.5 V
VDD = 12 V
VDD = 15 V
50
Propagation Delays (ns)
Operating Supply Current (mA)
60
40
CLOAD = 1.8 nF
Both channels switching
30
20
Input to Output On delay
Input to Ouptut Off Delay
EN to Output On Delay
EN to Output Off Delay
18
14
10
10
0
CLOAD = 1.8 nF
0
6
100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
G013
Figure 17. Operating Supply Current vs Frequency
4
8
12
Supply Voltage (V)
G014
10
CLOAD = 1.8 nF
CLOAD = 1.8 nF
14
Fall Time (ns)
Rise Time (ns)
20
Figure 18. Propagation Delays vs Supply Voltage
18
10
6
16
4
8
12
Supply Voltage (V)
16
8
6
4
20
4
8
12
Supply Voltage (V)
G015
Figure 19. Rise Time vs Supply Voltage
16
20
G016
Figure 20. Fall Time vs Supply Voltage
2.5
VDD = 4.5 V
Enable Threshold (V)
Enable High Threshold
Enable Low Threshold
2
1.5
1
0.5
−50
0
50
Temperature (°C)
100
150
G017
Figure 21. Enable Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The UCC2752x family of products represent TI’s latest generation of dual-channel, low-side, high-speed gatedriver devices featuring 5-A source and sink current capability, industry best-in-class switching characteristics
and a host of other features listed in Table 1 all of which combine to ensure efficient, robust and reliable
operation in high-frequency switching power circuits.
Table 1. UCC2752x Family of Features and Benefits
FEATURE
BENEFIT
Best-in-class 13-ns (typ) propagation delay
Extremely low-pulse transmission distortion
1-ns (typ) delay matching between channels
Ease of paralleling outputs for higher (2 times) current capability,
ease of driving parallel-power switches
Expanded VDD Operating range of 4.5 to 18 V
Flexibility in system design
Expanded operating temperature range of –40°C to 140°C
(See Electrical Characteristics)
VDD UVLO Protection
Outputs are held Low in UVLO condition, which ensures predictable,
glitch-free operation at power-up and power-down
Outputs held Low when input pins (INx) in floating condition
Safety feature, especially useful in passing abnormal condition tests
during safety certification
Outputs enable when enable pins (ENx) in floating condition
Pin-to-pin compatibility with UCC2732X family of products from TI, in
designs where pin 1 and 8 are in floating condition
CMOS/TTL compatible input and enable threshold with wide
hysteresis
Enhanced noise immunity, while retaining compatibility with
microcontroller logic level input signals (3.3 V, 5 V) optimized for
digital power
Ability of input and enable pins to handle voltage levels not restricted System simplification, especially related to auxiliary bias supply
by VDD pin bias voltage
architecture
8.2 Functional Block Diagrams
VDD
200 kW
ENA
VDD
VDD
200 kW
200 kW
1
VDD
8
ENB
ENA
200 kW
1
8
ENB
VDD
VDD
VDD
200 kW
INA
INA
2
GND
3
7
OUTA
2
OUTA
VDD
7
400 kW
VDD
VDD
VDD
VDD
VDD
UVLO
UVLO
6
VDD
GND
6
3
VDD
VDD
200 kW
INB
INB
4
5
OUTB
OUTB
4
5
400 kW
UDG-11221
Figure 22. UCC27523 Block Diagram
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Figure 23. UCC27524 Block Diagram
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Functional Block Diagrams (continued)
VDD
VDD
INA+
200 kW
8
VDD
200 kW
400 kW
ENA
1
8
5
VDD
6
OUTA
4
OUTB
ENB
VDD
VDD
VDD
VDD
200 kW
200 kW
INA-
INA
2
7
1
OUTA
VDD
VDD
GND
VDD
GND
3
UVLO
UVLO
3
6
VDD
VDD
VDD
INB+
INB
4
5
7
OUTB
VDD
400 kW
400 kW
200 kW
UDG-11223
INB-
2
UDG-11222
Figure 24. UCC27525 Block Diagram
Figure 25. UCC27526 Block Diagram
8.3 Feature Description
8.3.1 VDD and Undervoltage Lockout
The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output LOW,
regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis
prevents chatter when low VDD supply voltages have noise from the power supply and also when there are
droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD.
The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging GaN power semiconductor devices.
For example, at power up, the UCC2752x driver-device output remains LOW until the VDD voltage reaches the
UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with VDD until steadystate VDD is reached. The non-inverting operation in Figure 26 shows that the output remains LOW until the
UVLO threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 27
shows that the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with
the input. With UCC27526 the output turns to high-state only if INX+ is high and INX– is low after the UVLO
threshold is reached.
Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI highly recommends using
surface-mount components. A 0.1-μF ceramic capacitor must be located as close as possible to the VDD to GND
pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be
connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load.
The parallel combination of capacitors presents a low impedance characteristic for the expected current levels
and switching frequencies in the application.
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Feature Description (continued)
VDD Threshold
VDD Threshold
VDD
VDD
EN
EN
IN
IN
OUT
OUT
UDG-11229
UDG-11228
Figure 26. Power up Non-Inverting Driver
Figure 27. Power up Inverting Driver
8.3.2 Operating Supply Current
The UCC2752x products feature very low quiescent IDD currents. The typical operating-supply current in UVLO
state and fully on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and
Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, refer
Figure 6) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully
operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current due to
switching and finally any current related to pullup resistors on the enable pins and inverting input pins. For
example when the inverting Input pins are pulled low additional current is drawn from VDD supply through the
pullup resistors (refer to Figure 22 though Figure 25). Knowing the operating frequency (fSW) and the MOSFET
gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated as product of QG
and fSW.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages
under 1.8-nF switching load in both channels is provided in Figure 17. The strikingly linear variation and close
correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device
attesting to its high-speed characteristics.
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Feature Description (continued)
8.3.3 Input Stage
The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic
that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically low threshold =
1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V
digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity compared to
traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. UCC2752x devices also
feature tight control of the input pin threshold voltage levels which eases system design considerations and
ensures stable operation across temperature (refer to Figure 9). The very low input capacitance on these pins
reduces loading and increases switching speed.
The UCC2752x devices feature an important safety feature wherein, whenever any of the input pins is in a
floating condition, the output of the respective channel is held in the low state. This is achieved using VDD pullup
resistors on all the Inverting inputs (INA, INB in UCC27523, INA in UCC27525 and INA–, INB– in UCC27526) or
GND pulldown resistors on all the non-inverting input pins (INA, INB in UCC27524, INB in UCC27525 and INA+,
INB+ in UCC27526), as shown in the device block diagrams.
While UCC27523/4/5 devices feature one input pin per channel, the UCC27526 features a dual input
configuration with two input pins available to control the output state of each channel. With the UCC27526 device
the user has the flexibility to drive each channel using either a non-inverting input pin (INx+) or an inverting input
pin (INx–). The state of the output pin is dependent on the bias on both the INx+ and INx– pins (where x = A, B).
Once an Input pin is chosen to drive a channel, the other input pin of that channel (the unused input pin) must be
properly biased in order to enable the output of the channel. The unused input pin cannot remain in a floating
condition because, as mentioned earlier, whenever any input pin is left in a floating condition, the output of that
channel is disabled using the internal pullup or pulldown resistors for safety purposes. Alternatively, the unused
input pin is used effectively to implement an enable/disable function, as explained below.
• In order to drive the channel x (x = A or B) in a non-inverting configuration, apply the PWM control input
signal to INx+ pin. In this case, the unused input pin, INx-, must be biased low (for example, tied to GND) in
order to enable the output of this channel.
– Alternately, the INx– pin can be used to implement the enable/disable function using an external logic
signal. OUTx is disabled when INx- is biased High and OUTx is enabled when INX– is biased low.
• In order to drive the channel x (x = A or B) in an Inverting configuration, apply the PWM control input signal to
INX– pin. In this case, the unused input pin, INX+, must be biased high (for example, tied to VDD) in order to
enable the output of the channel.
– Alternately, the INX+ pin can be used to implement the enable/disable function using an external logic
signal. OUTX is disabled when INX+ is biased low and OUTX is enabled when INX+ is biased high.
• Finally, it is worth noting that the UCC27526 output pin can be driven into high state only when INx+ pin is
biased high and INx- input is biased low.
Refer to the input/output logic truth table and typical application diagrams, (Figure 34, Figure 35, and Figure 35),
for additional clarification.
The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in
typical power supply applications, where the input signals are provided by a PWM controller or logic gates with
fast transition times (< 200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly
at a high frequency. While the wide hysteresis offered in UCC2752x definitely alleviates this concern over most
other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall
times to the power device is the primary goal, then TI highly recommends an external resistance between the
output of the driver and the power device. This external resistor has the additional benefit of reducing part of the
gate-charge related power dissipation in the gate-driver device package and transferring it into the external
resistor itself.
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Feature Description (continued)
8.3.4 Enable Function
The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications
such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative
current circulation and to improve light-load efficiency.
UCC27523/4/5 devices are provided with independent enable pins ENx for exclusive control of each driverchannel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus
when ENx pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are
disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible input-threshold
logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5V microcontrollers. The UCC2752X devices also feature tight control of the Enable-function threshold-voltage
levels which eases system design considerations and ensures stable operation across temperature (refer to
Figure 10). The ENx pins are internally pulled up to VDD using pullup resistors as a result of which the outputs of
the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for
standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27523/4/5
devices to be pin-to-pin compatible with TI’s previous generation drivers UCC27323/4/5 respectively, where pins
1, 8 are N/C pins. If the Channel A and Channel B inputs and outputs are connected in parallel to increase the
driver current capacity, ENA and ENB are connected and driven together.
The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an
enable/disable function is easily implemented in UCC27526 using the unused input pin. When INx+ is pulled
down to GND or INx– is pulled down to VDD, the output is disabled. Thus INx+ pin is used like an enable pin that
is based on active high logic, while INx– is used like an enable pin that is based on active low logic. Note that
while the ENA, ENB pins in UCC27523/4/5 are allowed to be in floating condition during standard operation and
the outputs will be enabled, the INx+, INx– pins in UCC27526 are not allowed to be floating because this will
disable the outputs.
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Feature Description (continued)
8.3.5 Output Stage
The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the
highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon
transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup structure
features a P-channel MOSFET and an additional N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is accomplished by
briefly turning-on the N-channel MOSFET during a narrow instant when the output is changing state from Low to
High.
VCC
ROH
RNMOS, Pull Up
Input Signal
Anti ShootThrough
Circuitry
Gate
Voltage
Boost
OUT
Narrow Pulse at
each Turn On
R OL
Figure 28. UCC2752x Gate Driver Output Structure
The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the onresistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC
condition and is turned-on only for a narrow instant when output changes state from low to high. Note that
effective resistance of UCC2752x pullup stage during the turnon instant is much lower than what is represented
by ROH parameter.
The pulldown structure in UCC2752x is simply composed of a N-Channel MOSFET. The ROL parameter (see
Electrical Characteristics), which is also a DC measurement, is representative of the impedance of the pulldown
stage in the device. In UCC2752x, the effective resistance of the hybrid pullup structure during turnon is
estimated to be approximately 1.5 × ROL, estimated based on design considerations.
Each output stage in UCC2752x can supply 5-A peak source and 5-A peak sink current pulses. The output
voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS-output stage which
delivers very low drop-out. The presence of the MOSFET-body diodes also offers low impedance to switching
overshoots and undershoots which means that in many cases, external Schottky-diode clamps may be
eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either
damage to the device or logic malfunction.
The UCC2752x devices are particularly suited for dual-polarity, symmetrical drive-gate transformer applications
where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven
complementary to each other. This situation is due to the extremely low drop-out offered by the MOS output
stage of these devices, both during high (VOH) and low (VOL) states along with the low impedance of the driver
output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance.
The low propagation delays also ensure accurate reset for high-frequency applications.
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Feature Description (continued)
For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often
occurs in synchronous rectifier applications because the body diode is generally conducting before power
MOSFET is switched on.
8.3.6 Low Propagation Delays and Tightly Matched Outputs
The UCC2752x driver devices feature a best in class, 13-ns (typical) propagation delay between input and output
which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency
switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven with very
low distortion when one driver device is used to drive both the SR MOSFETs. Further, the driver devices also
feature an extremely accurate, 1-ns (typ) matched internal-propagation delays between the two channels which
is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a
pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both
channels are driven by a common control signal from the PFC controller device. In this case the 1ns delay
matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turnon
delay difference. Yet another benefit of the tight matching between the two channels is that the two channels are
connected together to effectively increase current drive capability, for example A and B channels may be
combined into one driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs
together. Then, one signal controls the paralleled combination.
Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the
possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current
conduction as shown in Figure 29. While the two channels are inherently very well matched (4-ns Max
propagation delay), note that there may be differences in the input threshold voltage level between the two
channels which causes the delay between the two outputs especially when slow dV/dt input signals are
employed. TI recommends the following guidelines whenever the two driver channels are paralleled using direct
connections between OUTA and OUTB along with INA and INB:
• Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences
in input thresholds causing delays between the channels.
• INA and INB connections must be made as close to the device pins as possible.
Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with
OUTA and OUTB. This allows the option to use 0-Ω resistors for paralleling outputs directly or to add appropriate
series resistances to limit shoot-through current, should it become necessary.
VDD
VDD
200 kW
ENA
200 kW
1
8
ISHOOT-THROUGH
VDD
Slow Input Signal
INA
2
VIN_H
(Channel B)
7
400 kW
VIN_H
(Channel A)
VDD
INB
3
OUTA
VDD
UVLO
GND
ENB
VDD
6
VDD
4
5
OUTB
400 kW
Figure 29. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling
(Recommended dV/dT is 20 V/Μs or Higher)
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Feature Description (continued)
Figure 30. Turnon Propagation Delay
(CL = 1.8 nF, VDD = 12 V)
Figure 31. Turnon Rise Time
(CL = 1.8 nF, VDD = 12 V)
Figure 32. Turnoff Propagation Delay
(CL = 1.8 nF, VDD = 12 V)
Figure 33. Turnoff Fall Time
(CL = 1.8 nF, VDD = 12 V)
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8.4 Device Functional Modes
Table 2. Device Logic Table (UCC27523/4/5)
UCC27523/4/5
UCC27524
UCC27525
ENB
INA
INB
OUTA
OUTB
OUTA
OUTB
OUTA
OUTB
H
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
Any
Any
L
L
L
L
L
L
(1)
(1)
L
Any
Any
L
L
L
L
L
x (1)
x (1)
L
L
H
H
L
L
H
L
x (1)
x (1)
L
H
H
L
L
H
H
H
x (1)
x (1)
H
L
L
H
H
L
L
L
(1)
x (1)
H
H
L
L
H
H
L
H
x
(1)
UCC27523
ENA
x
x
Floating condition.
Table 3. Device Logic Table (UCC27526)
INx+ (x = A or B)
(1)
20
INx- (x = A or B)
OUTx (x = A or B)
L
L
L
L
H
L
H
L
H
H
H
L
x (1)
Any
L
Any
x (1)
L
x = Floating condition.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver
device employs between the PWM output of control devices and the gates of the power semiconductor devices.
Further, gate-driver devices are indispensable when having the PWM controller device directly drive the gates of
the switching devices is sometimes not feasible. With advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V)
in order to fully turn on the power device and minimize conduction losses. Traditional buffer-drive circuits based
on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, prove
inadequate with digital power because they lack level-shifting capability. Gate-driver devices effectively combine
both the level-shifting and buffer-drive functions. Gate-driver devices also find other needs such as minimizing
the effect of high-frequency switching noise by locating the high-current driver physically close to the power
switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation
and thermal stress in controller devices by moving gate-charge power losses into the controller.
Finally, emerging wide band-gap power-device technologies such as GaN based switches, which can support
very high switching frequency operation, are driving special requirements in terms of gate-drive capability. These
requirements include operation at low VDD voltages (5 V or lower), low propagation delays, tight delay matching
and availability in compact, low-inductance packages with good thermal capability.
In summary gate-driver devices are extremely important components in switching power combining benefits of
high-performance, low-cost, component-count, board-space reduction, and simplified system design.
9.2 Typical Application
ENB
UCC2752x
ENA
1
ENA
INA
2
INA
3
GND
4
INB
ENB
8
OUTA
7
VDD
6
OUTB
5
V+
GND
INB
GND
GND
UDG-11225
Figure 34. UCC2752x Typical Application Diagram (x = 3, 4, or 5)
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Typical Application (continued)
UCC27526
INA-
1
INA-
INA+
8
2
INB-
INB+
7
3
GND
OUTA
6
INB+
V+
GND
GND
4
OUTB
VDD
5
GND
UDG-11226
Figure 35. UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration (Enable
Function Not Used)
OUTA is
ENABLED when
ENA is HIGH
UCC27526
INA-
1
INA-
INA+
8
ENA
ENB
2
INB-
INB+
7
INB+
3
GND
OUTA
6
OUTB is
ENABLED when
ENB is LOW
V+
GND
GND
4
OUTB
VDD
5
GND
UDG-11227
Figure 36. UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration (Enable
Function Implemented)
9.2.1 Design Requirements
When selecting the proper gate-driver device for an end application, some design considerations must be
evaluated first in order to make the most appropriate selection. Among these considerations are input-to-output
logic, VDD, UVLO, Drive current and power dissipation.
9.2.2 Detailed Design Procedure
9.2.2.1 Input-to-Output Logic
The design should specify which type of input-to-output configuration should be used. The UCC27523 device can
provide dual inverting input to output with enable control. The UCC27524 device can provide dual non-inverting
input to output with enable control. The UCC27525 device can provide one inverting and one non-inverting input
to output control. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred,
then the non-inverting configuration must be selected. If turning off the power MOSFET or IGBT when the input
22
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Typical Application (continued)
signal is in high state is preferred, the inverting configuration must be chosen. UCC27526 has dual configuration
channel. Each Channel of UCC27526 device can be configured in either an inverting or non-inverting input-tooutput configuration using the INx– or INx+ pins respectively like in Figure 35 and Figure 36. To configure the
channel for use in inverting mode, tie the INx+ pin to VDD and apply the input signal to the INx– pin. For the noninverting configuration, tie the INx– pin to GND and apply the input signal to the INx+ pin.
9.2.2.2 Enable and Disable Function
Certain applications demand independent control of the output state of the driver. The UCC27523/4/5 device
offers two independent enable pins ENx for exclusive control of each driver channels as listed in Table 2.
The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an
enable/disable function can be easily implemented in UCC27526 using the unused input pin. When INx+ is
pulled-down to GND or INx– is pulled-down to VDD, the output is disabled as listed in Table 3. Thus INx+ pin can
be used like an enable pin that is based on active high logic, while INx– can be used like an enable pin that is
based on active low logic. It is important to note that while the ENA, ENB pins in the UCC27523/4/5 are allowed
to be in floating condition during standard operation and the outputs will be enabled, the INx+, INx– pins in
UCC27526 are not allowed to be floating because this will disable the outputs.
9.2.2.3 VDD Bias Supply Voltage
The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the
Recommended Operating Conditions. However, different power switches demand different voltage levels to be
applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage
may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias
supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC2752x device can
be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10 V, 12 V),
IGBTs (VGE = 15 V, 18 V).
9.2.2.4 Propagation Delay
The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC2752x device features fast 13-ns
(typical) propagation delays which ensures very little pulse distortion and allows operation at very highfrequencies. See the Switching Characteristics for the propagation and switching characteristics of the
UCC2752x device.
9.2.2.5 Drive Current and Power Dissipation
The UCC27523/4/5/6 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a period of
several-hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON quickly. Then,
to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the
operating frequency of the power device. The power dissipated in the gate-driver device package depends on the
following factors:
• Gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close
to input bias supply voltage VDD due to low VOH drop-out)
• Switching frequency
• Use of external gate resistors
Because UCC2752x features very low quiescent currents and internal logic to eliminate any shoot-through in the
output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be
negligible.
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias
supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given
by Equation 1.
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Typical Application (continued)
EG =
1
CLOAD VDD2
2
where
•
•
CLOAD is load capacitor
VDD is bias voltage feeding the driver.
(1)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by Equation 2.
PG = CLOAD VDD2 fSW
where
•
fSW is the switching frequency
(2)
With VDD = 12 V, CLOAD = 10 nF and ƒSW = 300 kHz the power loss is calculated as (see Equation 3):
PG = 10nF ´ 12 V 2 ´ 300kHz = 0.432 W
(3)
The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to
switch the device under specified conditions. Using the gate charge Qg, the power that must be dissipated when
charging a capacitor is determined which by using the equivalence Qg = CLOADVDD to provide Equation 4 for
power:
PG = CLOAD VDD2 fSW = Qg VDD fSW
(4)
Assuming that UCC2752x is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on
each output, the gate charge related power loss is calculated as (see Equation 5):
PG = 2 x 60nC ´ 12 V ´ 300kHz = 0.432 W
(5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half
of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated
when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the
driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external
gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate
resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component).
Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see
Equation 6):
æ
ö
ROFF
RON
PSW = 0.5 ´ QG ´ VDD ´ fSW ´ ç
+
÷
è ROFF + RGATE RON + RGATE ø
where
•
•
ROFF = ROL
RON (effective resistance of pullup structure) = 1.5 x ROL
(6)
In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the
power associated with the quiescent bias current consumed by the device to bias all internal circuits such as
input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in Figure 6, the quiescent
current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated easily with
Equation 7.
PQ = IDD VDD
(7)
Assuming , IDD = 6 mA, the power loss is:
PQ = 0.6 mA ´ 12 V = 7.2mW
(8)
Clearly, this power loss is insignificant compared to gate charge related power dissipation calculated earlier.
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Typical Application (continued)
With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the
quiescent consumption:
P
0.432 W
IDD ~ G =
= 0.036 A
VDD
12 V
(9)
9.2.3 Application Curves
Figure 37 and Figure 38 show the typical switching characteristics of the non-inverting input driver operation for
UCC27523/4/5/6 device. CL = 1.8 nF, VDD = 12 V
Figure 37. Typical Turnon Waveform
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Figure 38. Typical Turnoff Waveform
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10 Power Supply Recommendations
The bias supply voltage range for which the UCC2752X device is rated to operate is from 4.5 V to 18 V. The
lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD
pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VON
supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of
this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress
rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the
VDD pin is 18 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage, device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD_H.
Therefore, ensuring that, while operating at or near the 4.2-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below
the VOFF threshold which must be accounted for while evaluating system shutdown timing design requirements.
Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above
the VON threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied
through the VDD pin. It is important to recognize that the charge for source current pulses delivered by the
OUTA/B pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the
output pins, a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that
local bypass capacitors are provided between the VDD and GND pins and located as close to the device as
possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI
recommends having two capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close
to the pins of the device and another surface-mount capacitor of few microfarads added in parallel.
11 Layout
11.1 Layout Guidelines
Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27523/4/5/6 family of gate drivers incorporates short propagation
delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at
the gate of power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current
capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if the
trace lengths and impedances are not well controlled. TI strongly recommends the following circuit layout
guidelines when designing with these high-speed drivers.
• Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the Output pins and the Gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace
length to improve the noise filtering. These capacitors support high peak current being drawn from VDD during
turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip
capacitors is highly recommended.
• The turnon and turnoff current loop paths (driver device, power MOSFET and VDD bypass capacitor) should
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at 2 instances during turnon and turnoff transients, which will induce significant
voltage transients on the output pin of the driver device and Gate of the power MOSFET.
• Wherever possible, parallel the source and return traces, taking advantage of flux cancellation
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM
controller at one, single point. The connected paths must be as short as possible to reduce inductance and
be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well
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Layout Guidelines (continued)
•
•
In noisy environments, tying inputs of an unused channel of UCC27526 to VDD (in case of INx+) or GND (in
case of INX–) using short traces in order to ensure that the output is enabled and to prevent noise from
causing malfunction in the output may be necessary.
Exercise caution when replacing the UCC2732x/UCC2742x devices with the UCC2752x:
– UCC2752x is a much stronger gate driver (5-A peak current versus 4-A peak current).
– UCC2752x is a much faster gate driver (13-ns/13-ns rise/fall propagation delay versus 25-ns/35-ns rise/fall
propagation delay).
11.2 Layout Example
Figure 39. Layout Example for UCC27523/4/5 (D, DGN)
11.3 Thermal Considerations
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a gate-driver device to be useful over a particular temperature
range the package must allow for the efficient removal of the heat produced while keeping the junction
temperature within rated limits. The UCC27523/4/5/6 family of drivers is available in four different packages to
cover a range of application requirements. The thermal metrics for each of these packages are summarized in
Thermal Information. For detailed information regarding the thermal information table, refer to Application Note
from Texas Instruments entitled, IC Package Thermal Metrics (SPRA953).
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Thermal Considerations (continued)
Among the different package options available in the UCC2752x family, of particular mention are the DSD and
DGN packages when it comes to power dissipation capability. The MSOP PowerPAD-8 (DGN) package and 3mm × 3-mm WSON (DSD) package offer a means of removing the heat from the semiconductor junction through
the bottom of the package. Both these packages offer an exposed thermal pad at the base of the package. This
pad is soldered to the copper on the printed-circuit-board directly underneath the device package, reducing the
thermal resistance to a very low value. This allows a significant improvement in heat-sinking over that available in
the D or P packages. The printed-circuit-board must be designed with thermal lands and thermal vias to
complete the heat removal subsystem. Note that the exposed pads in the MSOP-8 (PowerPAD) and WSON-8
packages are not directly connected to any leads of the package, however, it is electrically and thermally
connected to the substrate of the device which is the ground of the device. TI recommends to externally connect
the exposed pads to GND in PCB layout for better EMI immunity.
28
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC27523
Click here
Click here
Click here
Click here
Click here
UCC27524
Click here
Click here
Click here
Click here
Click here
UCC27525
Click here
Click here
Click here
Click here
Click here
UCC27526
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC27523D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27523
UCC27523DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 140
27523
UCC27523DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 140
27523
UCC27523DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27523
UCC27523DSDR
ACTIVE
SON
DSD
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27523
UCC27523DSDT
ACTIVE
SON
DSD
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27523
UCC27524D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27524
UCC27524DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 140
27524
UCC27524DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 140
27524
UCC27524DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27524
UCC27524DSDR
ACTIVE
SON
DSD
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
SBA
UCC27524DSDT
ACTIVE
SON
DSD
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
SBA
UCC27524P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 140
27524
UCC27525D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27525
UCC27525DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 140
27525
UCC27525DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 140
27525
UCC27525DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 140
27525
UCC27525DSDR
ACTIVE
SON
DSD
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27525
UCC27525DSDT
ACTIVE
SON
DSD
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
27525
UCC27526DSDR
ACTIVE
SON
DSD
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
SCB
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
RoHS & Green
NIPDAU
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC27526DSDT
ACTIVE
SON
DSD
8
250
Level-2-260C-1 YEAR
-40 to 140
SCB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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