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UCC27714
SLUSBY6B – AUGUST 2015 – REVISED MARCH 2017
UCC27714 High-Speed, 600-V High-Side Low-Side Gate Driver
with 4-A Peak Output
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
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•
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High-Side, Low-Side Configuration, with
Independent Inputs
Fully Operational up to 600 V (HS Pin)
Floating Channel Designed for Bootstrap
Operation
Peak Output Current Capability of 4-A Sink 4-A
Source at VDD = 15 V
Best-In-Class Propagation Delay (125-ns
Maximum)
Best-In-Class Delay Matching (20-ns Maximum)
TTL and CMOS Compatible Input Logic
VDD Bias Supply Range of 10 V to 20 V
Bias UVLO Protection for Both Channels
Rail-to-Rail Drive
Robust Operation Under Negative Voltage
Transients
High dv/dt Immunity (HS Pin)
Separated Grounds for Logic (VSS) and Driver
(COM) with Capability to Sustain Voltage
Difference
Optional Enable Function (Pin 4)
Outputs Held in LOW when Inputs Floating
Inputs and Enable Pin Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage
High and Low Voltage Pins Separated for
Maximum Creepage and Clearance
Negative Voltage Handling Capability on Input and
Enable Pins
Simplified Schematic
•
•
Half-Bridge and Full-Bridge Converters in Offline
AC and DC Power Supplies
High-Density Switching Power Supplies for
Server, Telecom, IT and Industrial Infrastructure
Solar Inverters, Motor Drive and UPS
3 Description
UCC27714 is a 600-V high-side, low-side gate driver
with 4-A source and 4-A sink current capability,
targeted to drive power MOSFETs or IGBTs. The
device comprises of one ground-referenced channel
(LO) and one floating channel (HO) which is designed
for operating with bootstrap supplies. The device
features excellent robustness and noise immunity
with capability to maintain operational logic at
negative voltages of up to –8 VDC on HS pin (at VDD
= 12 V).
The device accepts a wide range bias supply input
from 10 V to 20 V and offers UVLO protection for
both the VCC and HB bias supply pins. UCC27714 is
available in SOIC-14 package and rated to operate
from –40°C to 125°C.
Device Information (1)
PART NUMBER
(1)
DBOOT
CVDD
UCC27714
7
VDD
HB 13
CBOOT
Controller
RHI
RHO
PWM1
1 HI
Q1
HO 12
10 k:
RLI
PWM2
2
LI
HS 11
Load
CLI CHI
Typical Propagation Delay Comparison
230
Competitor
210
TI
190
170
150
130
110
90
70
Q2
RLO
VSS
EN
3.91 mm × 8.65 mm
250
Up to 600 V
Propagation Delay (ns)
RBOOT
BODY SIZE (NOM)
SOIC (14)
For all available packages, see the orderable addendum at
the end of the datasheet.
Bias
RBIAS
PACKAGE
UCC27714
3 VSS
LO
6
±40
10 k:
4
EN/NC COM
50
±20
0
20
40
60
Temperature (ƒC)
80
100
120
C037
5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27714
SLUSBY6B – AUGUST 2015 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
5
5
5
6
7
8
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application ................................................. 27
9 Power Supply Recommendations...................... 35
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
36
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Revision A (August 2015) to Revision B
Page
•
Changed MAX Supply voltage from 18 V to 17 V. ................................................................................................................. 5
•
Changed MAX Driver bootstrap voltage from 18 V to 17 V. .................................................................................................. 5
•
Changed MAX Bootstrap pin voltage from 18 V to 17 V........................................................................................................ 5
•
Changed MAX Input voltage with respect to VSS from 18 V to 17 V. .................................................................................. 5
•
Added 40 ns NOM to tON Timing Requirements. .................................................................................................................... 7
•
Added 40 ns NOM to tOFF Timing Requirements. .................................................................................................................. 7
•
Deleted 18-V reference from all Typical Characteristics images............................................................................................ 8
•
Changed Negative Voltage Chart Time vs Negative Voltage image. .................................................................................. 26
•
Added Increase RHO and RLO, Reduce HS dV/dt image and description. ........................................................................... 31
•
Added LO and HO Overshoot and Undershoot section. ...................................................................................................... 32
Changes from Original (August, 2015) to Revision A
•
Page
Changed marketing status from Product preview to Final. ................................................................................................... 1
`
2
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SLUSBY6B – AUGUST 2015 – REVISED MARCH 2017
5 Pin Configuration and Functions
D Package
14-Pin SOIC
Top View
HI
1
14
NC
LI
2
13
HB
VSS
3
12
HO
EN/NC
4
11
HS
COM
5
10
NC
LO
6
9
NC
VDD
7
8
NC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
COM
5
–
Return for low-side driver output.
EN/NC
4
I
Enable input for high-side and low-side driver. This pin biased LOW, disables both HO and
LO regardless of HI and LI state, This pin biased high or floating enables both HO and LO.
HB
13
I
High-side floating supply. Bypass this pin to HS with a suitable capacitor to sustain bootstrap circuit operation in the desired application, typically 10× bigger than gate capacitance.
HI
1
I
Logic input for high-side driver. If HI is unbiased or floating, HO is held low.
HO
12
O
High-side driver output.
HS
11
–
Return for high-side floating supply.
LI
2
I
Logic input for low-side driver. If LI is unbiased or floating, LO is held low.
LO
6
O
Low-side driver output.
NC
8, 9, 10, 14
–
No connection.
VDD
7
I
Bias supply input. Power supply for the input logic side of the device and also low-side driver
output. Bypass this pin to VSS with typical 1-µF SMD capacitor (typically CVDD needs to be
10 × CBOOT). If shunt resistor used between COM and VSS, then also bypass this pin to
COM with 1-µF SMD capacitor.
VSS
3
–
Logic ground.
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SLUSBY6B – AUGUST 2015 – REVISED MARCH 2017
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6 Specifications
6.1 Absolute Maximum Ratings (1)
(2)
Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise
noted), currents are positive into and negative out of the specified terminal. (1)
HI, LI, EN (3) with respect to VSS
VIN
Input voltage range
Output voltage range, HO
VOUT
Output voltage range, LO
MIN
MAX
UNIT
–5
20
V
VDD supply voltage
–0.3
20
V
HB
–0.3
640
V
HB-HS
–0.3
20
V
HS – 0.3
HB + 0.3
V
HS – 2
HB + 0.3
V
–0.3
VDD + 0.3
V
–2
VDD + 0.3
V
–7
6
V
–0.3
20
V
±4
A
DC
Transient, less than 100 ns
(4)
DC
Transient, less than 100 ns (4)
Logic ground, With respect to COM
Logic ground, VDD-VSS
IOUT
Output current, HO, LO, IOUT_PULSED (100 ns)
IOUT
Output current, HO, LO, IOUT_DC
dVHS/dt
Allowable offset supply voltage transient
–50
Lead temperature (soldering, 10 second)
0.25
A
50
V/ns
300
°C
TJ
Junction temperature range
–40
150
°C
Tstg
Storage temperature range
-65
150
°C
(1)
(2)
(3)
(4)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See Packaging Section of the datasheet for thermal limitations and considerations of packages.
The maximum voltage on the Input pins is not restricted by the voltage on the VDD pin.
Values are verified by characterization on bench.
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SLUSBY6B – AUGUST 2015 – REVISED MARCH 2017
6.2 ESD Ratings
V(ESD) (1) Electrostatic discharge
(1)
VALUE
UNIT
Human body model, HBM
±1400
V
Charge device model, CDM
±500
V
These devices are sensitive to electrostatic discharge; follow proper device handing procedures
6.3 Recommended Operating Conditions
All voltages are with respect to COM, –40°C < TJ < 125°C, currents are positive into, negative out of the specified terminals
MIN
MAX
UNIT
17
V
10
17
V
–8
600
V
HS + 10
HS + 17
V
–4
17
V
VDD
Supply voltage
10
HB-HS
Driver bootstrap voltage
HS
Source terminal voltage (1)
HB
Bootstrap pin voltage
HI, LI, EN
Input voltage with respect to VSS
(2)
VSS
Logic ground
–6
TJ
Junction temperature
–40
(1)
(2)
(3)
NOM
5
(3)
125
V
°C
Logic operational for HS of –8 V to 600 V at HB – HS = 12 V
At VDD – COM = 10 V
At VDD – COM = 15 V
6.4 Thermal Information
UCC27714
THERMAL METRIC (1)
D (SOIC)
UNIT
PINS
RθJA
Junction-to-ambient thermal resistance
72.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.8
°C/W
RθJB
Junction-to-board thermal resistance
26.5
°C/W
ψJT
Junction-to-top characterization parameter
3.6
°C/W
ψJB
Junction-to-board characterization parameter
26.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At VDD = VHB = 15 V, VSS = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < 125°C,
current are positive into and negative out of the specified terminal, over operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY BLOCK
VVDD(on)
turn-on threshold voltage of VDD
8.4
9.1
9.8
V
VVDD(off)
turn-off threshold voltage of VDD
7.9
8.6
9.3
V
VVDD(hys)
Hysteresis of VDD
0.4
0.5
-
V
VVHB(on)
turn-on threshold voltage of VHBVHS
7.7
8.3
9.0
V
VVHB(off)
turn-off threshold voltage of VHBVHS
6.7
7.25
8.05
V
VVHB(hys)
Hysteresis of VHB-VHS
0.5
1.0
-
V
IQDD
Total quiescent VDD to VSS and
COM supply current
HI = LI = 0 V or 5 V, DC on/off state
750
1050
µA
IQCOM
Quiescent VDD-COM supply current HI = LI = 0 V or 5 V, DC on/off state
175
350
µA
IQVSS
Quiescent VDD-VSS supply current
HI = LI = 0 V or 5 V, DC on/off state
550
750
µA
IQBS
Quiescent HB-HS supply current
HI = 0 V or 5 V, HO in DC on/off
state
120
300
µA
IBL
Bootstrap Supply Leakage Current
HB = HS = 600 V
20
µA
INPUT AND ENABLE BLOCK
VINH, VENH
Input pin (HI or LI) and enable pin
(EN) High threshold
1.7
2.3
2.7
V
VINL, VENL
Input pin (HI or LI) and enable pin
(EN) low threshold
1.2
1.6
2.1
V
VINHYS,
VENHYS
Input pin (HI or LI) and enable pin
(EN) threshold hysteresis
IINL
HI, LI input low bias current
HI, LI = 0 V
-5
5
µA
IINH
HI, LI input high bias current
HI, LI = 5 V
3
65
µA
IENL
EN input low bias current
VEN = 0 V
-90
-50
µA
IENH
EN input high bias current
VEN = 5 V
-65
-25
µA
RHI
Pull-down resistor on HI input pin
400
kΩ
RLI
Pull-down resistor on LI input pin
400
kΩ
REN
Pull-up resistor on enable pin
200
kΩ
0.7
0
V
OUTPUT BLOCK
VDD-VLOH
LO output high voltage
LI = 5 V, ILO = –20 mA
70
120
mV
VHB-VHOH
HO output high voltage
HI = 5 V, IHO = –20 mA
70
120
mV
VLOL
LO output low voltage
LI = 0 V, ILO = 20 mA
15
35
mV
VHOL
HO output low voltage
HI = 0 V, IHO = 20 mA
20
40
mV
RLOL,
RHOL (1)
LO, HO output pull down resistance
ILO = 20 mA, IHO = 20 mA
RLOH,
RHOH
LO, HO output pull up resistance
ILO = –20 mA, IHO= –20 mA
3.75
1.45
Ω
5.8
Ω
IGPK-
(2)
HO. LO output low short circuit
pulsed current
HI = L = 0 V, HO = LO = 15 V, PW <
10 µs
4
A
IGPK+
(2)
HO. LO output high short circuit
pulsed current
H I= LI = 5 V, HO = LO = 0 V, PW <
10 µs
4
A
(1)
(2)
6
ROH represents on-resistance of only the P-Channel MOSFET device in pull-up structure of UCC27714 output stage. Refer to Output
Stage
Ensured by Design, Not tested in production
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
DYNAMIC CHARACTERISTICS
tPDLH
Turn-on propagation delay, LI to LO, HI to HO, HS = COM = 0 V or
HS = 600 V
90
125
ns
tPDHL
Turn-off propagation delay, LI to LO, HI to HO, HS = COM = 0 V or
HS = 600 V
90
125
ns
tPDRM
Low-to-high delay matching, HS = COM = 0 V
20
ns
tPDFM
High-to-low delay matching, HS = COM = 0 V
20
ns
tRISE
Turn-on rise time, 10% to 90%, HO/LO with 1000-pF load
15
30
ns
tFALL
Turn-off fall time, 90% to 10%, HO/LO with 1000-pF load
15
30
ns
tON
Minimum HI/LI ON pulse that changes output state, 0-V to 5-V input
signal on HI and LI pins
40
100
ns
tOFF
Minimum HI/LI OFF pulse that changes output state, 5-V to 0-V input
signal on HI and LI pins
40
100
ns
50%
HI, LI
50%
HI, LI
tPDLH tRISE
tPDHL tFALL
LO
90%
90%
10%
10%
HO, LO
HO
tPDRM
tPDFM
Figure 1. Typical Test Timing Diagram
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110
110
100
100
Low side tPDHL (ns)
Low Side tPDLH (ns)
6.7 Typical Characteristics
90
80
90
80
70
70
VDD=10V
VDD = 10 V
VDD = 15 V
60
-40
±40
-20
0
20
40
60
Temperature (qC)
80
100
0
±20
120
90
90
High Side tPDHL (ns)
100
70
40
60
80
-20
0
20
40
60
Temperature (qC)
80
100
80
70
VDD=10 V
VDD= 15 V
60
-40
120
Figure 4. High-Side, Turn-On Propagation Delay vs
Temperature
0
20
40
60
Temperature (qC)
80
100
120
30
VDD = 10 V
VDD = 15 V
27
24
21
18
15
12
9
6
3
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 6. Turn-On Delay Matching vs Temperature
Turn OFF Delay Matching t PDRM (ns)
Turn ON Delay Matching t PDRM (ns)
-20
Figure 5. High-Side, Turn-Off Propagation Delay vs
Temperature
30
8
120
C00
VDD = 10 V
VDD = 15 V
60
-40
100
Figure 3. Low-Side, Turn-Off Propagation Delay vs
Temperature
100
80
20
Temperature (ƒC)
Figure 2. Low-Side, Turn-On Propagation Delay vs
Temperature
High Side tPDLH (ns)
VDD=15V
60
VDD = 10 V
VDD = 15 V
27
24
21
18
15
12
9
6
3
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 7. Turn-Off Delay Matching vs Temperature
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120
120
110
110
100
100
High Side tPDHL (ns)
High Side tPDLH (ns)
Typical Characteristics (continued)
90
80
70
90
80
70
HS = 0 V
HS = 400 V
HS = 600 V
60
50
-40
-20
0
20
40
60
Temperature (qC)
80
100
50
-40
120
80
100
120
D031
8
7
6
VDD=10 V
VDD=15 V
9
LO tFALL (ns)
LO tRISE (ns)
20
40
60
Temperature (qC)
10
VDD=10 V
VDD=15 V
9
5
8
7
6
5
-20
0
20
40
60
Temperature (qC)
80
100
4
-40
120
Figure 10. LO Rise Time with 1000-pF Load vs Temperature
10
9
9
8
8
7
6
5
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 11. LO Fall Time with 1000-pF Load vs Temperature
10
HO tFALL (ns)
HO tRISE (ns)
0
Figure 9. High-Side, Turn-Off Propagation Delay vs
Temperature
10
VDD=10 V
VDD=15 V
7
6
5
4
3
-40
-20
D030
Figure 8. High-Side, Turn-On Propagation Delay vs
Temperature
4
-40
HS = 0 V
HS = 400 V
HS = 600 V
60
VDD=10 V
VDD=15 V
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 12. HO Rise Time with 1000-pF Load vs Temperature
4
3
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 13. HO Fall Time with 1000-pF Load vs Temperature
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Typical Characteristics (continued)
9.5
9.5
VVDD_OFF (V)
10.0
VVDD_ON (V)
10.0
9.0
8.5
9.0
8.5
UVLO ON of VDD
UVLO OFF of VDD
8.0
8.0
±40
±20
0
20
40
60
80
100
120
Temperature (ƒC)
40
0
20
40
60
9.0
8.5
8.5
VVHB_OFF (V)
9.0
8.0
120
C012
8.0
7.5
HB_UVLO_ON
HB_UVLO_OFF
7.0
7.0
40
20
0
20
40
60
80
100
Temperature (ƒC)
120
40
20
0
20
40
60
80
100
120
Temperature (ƒC)
C014
C015
Figure 16. VHB-VHS UVLO On Threshold vs Temperature
Figure 17. VHB-VHS UVLO Off Threshold vs Temperature
1.5
1.5
1.2
1.2
VVHB_HYS (V)
VVDD_HYS (V)
100
Figure 15. VDD UVLO Off Threshold vs Temperature
7.5
0.9
0.6
0.3
0.9
0.6
0.3
VDD_UVLO_HYS
HB_UVLO_HYS
0.0
0.0
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
40
20
0
20
40
60
80
100
120
Temperature (ƒC)
C013
Figure 18. VDD UVLO Hysteresis vs Temperature
10
80
Temperature (ƒC)
Figure 14. VDD UVLO On Threshold vs Temperature
VVHB_ON (V)
20
C011
C016
Figure 19. VHB-VHS UVLO Hysteresis vs Temperature
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Typical Characteristics (continued)
2.5
1.8
2.4
VINL, VENL (V)
VINH, VENH (V)
1.7
2.3
2.2
HI
HI
LI
EN
1.5
LI
2.1
1.6
EN
2.0
1.4
±40
±20
0
20
40
60
80
100
120
Temperature (ƒC)
±40
±20
0
20
40
60
80
Figure 20. HI/LI/EN Pin High Threshold vs Temperature
120
C019
Figure 21. HI/LI/EN Pin Low Threshold vs Temperature
50
1.0
VDD= 10 V
VDD= 15 V
45
40
0.8
VLOL (mV)
VINHYS, VENHYS (V)
100
Temperature (ƒC)
C017
0.6
35
30
HI
25
LI
20
EN
15
0.4
40
20
0
20
40
60
80
100
120
Temperature (ƒC)
10
-40
C020
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 22. HI/LI/EN Pin Hysteresis vs Temperature
Figure 23. LO Output Low Voltage with 20-mA Load vs
Temperature
50
110
VDD=10 V
VDD=15 V
45
100
VHOL (mV)
VDD-VLOH (mV)
40
90
80
70
35
30
25
20
60
VDD=10V
15
VDD=15V
50
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
C02
Figure 24. LO Output High Voltage with 20-mA Load vs
Temperature
10
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 25. HO Output Low Voltage with 20-mA Load vs
Temperature
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Typical Characteristics (continued)
90
1
80
0.8
RLOL (:)
1.2
VHB - VHOH (mV)
100
70
60
0.6
0.4
50
0.2
VDD= 10 V
VDD= 15 V
40
-40
-20
0
20
40
60
Temperature (qC)
80
100
VDD=10 V
VDD=15 V
0
-40
120
Figure 26. HO Output High Voltage with 20-mA Load vs
Temperature
-20
0
20
40
60
Temperature (qC)
80
100
120
Figure 27. LO Output Pull-Down Resistance vs Temperature
1.2
6.0
5.5
1.0
5.0
RLOH (Ÿ)
RHOL (Ÿ)
0.8
0.6
0.4
4.5
4.0
3.5
3.0
0.2
VDD=10V
VDD=10V
2.5
VDD=15V
0.0
±20
0
20
40
60
80
100
120
Temperature (ƒC)
40
20
0
4.5
100
EN_ON_Delay (ns)
110
3.5
3.0
2.5
40
60
80
90
80
70
VDD=10V
VDD=15V
2.0
20
0
20
40
60
Temperature (ƒC)
80
100
120
±40
±20
0
20
40
60
Temperature (ƒC)
C02
Figure 30. HO Output Pull-Up Resistance vs Temperature
12
VDD=15V
50
40
120
C02
60
VDD=10V
100
Figure 29. LO Output Pull-Up Resistance vs Temperature
5.0
4.0
20
Temperature (ƒC)
C02
Figure 28. HO Output Pull-Down Resistance vs Temperature
RHOH (Ÿ)
VDD=15V
2.0
±40
80
100
120
C02
Figure 31. EN ON Response Time vs Temperature
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Typical Characteristics (continued)
110
800
770
740
710
90
IQDD (µA)
EN_OFF_Delay (ns)
100
80
650
620
590
70
560
530
60
VDD=10 V
VDD=15 V
50
-40
-20
0
20
40
60
Temperature (qC)
80
100
±40
±20
0
20
40
60
80
100
120
Temperature (ƒC)
120
C032
Figure 33. Total Quiescent VDD to VSS and COM Supply
Current vs Temperature
200
600
180
580
560
160
540
IQVSS (µA)
140
120
100
520
500
480
80
460
60
440
40
420
Quiescent VDD to COM current
Quiescent VDD to VSS current
400
20
±40
±20
0
20
40
60
80
100
±40
120
Temperature (ƒC)
±20
0
20
40
60
80
100
120
Temperature (ƒC)
C033
C034
Figure 35. Quiescent VDD to VSS Supply Current vs
Temperature
Figure 34. Quiescent VDD to COM Supply Current vs
Temperature
20.0
300
Bootstrap Supply Leakage Current
18.0
Quiescent HB to HS current
280
16.0
260
14.0
240
12.0
220
IQBS (µA)
IBL (µA)
Quiescent VDD to VSS & COM
500
Figure 32. EN OFF Response Time vs Temperature
IQCOM (µA)
680
10.0
8.0
200
180
6.0
160
4.0
140
2.0
120
0.0
100
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
Figure 36. Bootstrap Supply Leakage Current vs
Temperature
±20
0
20
40
60
80
100
120
Temperature (ƒC)
C035
C036
Figure 37. Total Quiescent HB to HS Supply Current
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7 Detailed Description
7.1 Overview
High-current, gate-driver devices are required in switching power applications for a variety of reasons. In order to
implement fast switching of power devices and reduce associated switching power losses, a powerful gate-driver
device is employed between the PWM output of control devices and the gates of the power semiconductor
devices. Further, gate-driver devices are indispensable when having the PWM controller device directly drive the
gates of the switching devices is sometimes not feasible. In the case of digital power supply controllers, this
situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal
which is not capable of effectively turning on a power switch.
In bridge topologies, like hard-switch half bridge, hard-switch full bridge, half-bridge and full-bridge LLC, phaseshift full bridge, 2-transistor forward, the source and emitter pin of the top-side power MOSFET and IGBT switch
is referenced to a node whose voltage changes dynamically; that is, not referenced to a fixed potential, so
floating-driver devices are necessary in these topologies.
The UCC27714 is a high-side and low-side driver dedicated for offline AC-to-DC power supplies and inverters.
The high side is a floating driver that can be biased effectively using a bootstrap circuit, and can handle up to
600-V. The driver includes an enable and disable function, and can be used with 100% duty cycle as long as HBHS can be above UVLO of the high side.
The device features industry best-in-class propagation delays and delay matching between both channels aimed
at minimizing pulse distortion in high-frequency switching applications. Each channel is controlled by its
respective input pins (HI and LI), allowing full and independent flexibility to control on and off state of the output.
The UCC27714 includes protection features wherein the outputs are held low when inputs are floating or when
the minimum input pulse width specification is not met. The driver inputs are CMOS and TTL compatible for easy
interface to digital power controllers and analog controllers alike. An optional enable and disable function is
included in Pin 4 of the UCC27714. The pin is internally pulled to VDD for active-high logic and can be left open
(NC) for standard operation when outputs are enable by default. If the pin is pulled to GND, then outputs are
disabled.
7.2 Functional Block Diagram
VDD
HI
4
R R
R
Q
S
VSS/HS Level
Shift
1
40 ns
Delay
VDD-VSS
UVLO
VSS/COM Level
Shift
2
12
HO
11
HS
7
VDD
6
LO
5
COM
VSS/HS Level
Shift
400 k
LI
HB
VHB
UVLO
200 k
EN/NC
13
40 ns
Delay
VSS
400 k
VSS
3
Figure 38. UCC27714 Block Diagram
14
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7.3 Feature Description
7.3.1 VDD and Under Voltage Lockout
The UCC27714 has an internal under voltage-lockout (UVLO) protection feature on the supply circuit blocks
between VDD and VSS pins, as well as between HB and HS pins. When VDD bias voltage is lower than the
VVDD(on) threshold at device start-up or lower than VVDD(off) after start-up, the VDD UVLO feature holds both the
LO and HO outputs LOW, regardless of the status of the HI and LI inputs. On the other hand, if HB-HS bias
supply voltage is lower than the VVHB(on) threshold at start-up or VVHB(off) after start-up, the HB-HS UVLO feature
only holds HO to LOW, regardless of the status of the HI. The LO output status is not affected by the HB-HS
UVLO feature (see Table 1 and Table 2). This allows the LO output to turn-on and re-charge the HB-HS
capacitor using the boot-strap circuit and thus allows HB-HS bias voltage to surpass the VVHB(on) threshold.
Both the VDD and VHB UVLO protection functions are provided with a hysteresis feature. This hysteresis
prevents chatter when there is ground noise from the power supply. Also this allows the device to accept a small
drop in the bias voltage which is bound to happen when the device starts switching and quiescent current
consumption increases instantaneously, as well as when the boot-strap circuit charges the HB-HS capacitor
during the first instance of LO turn-on causing a drop in VDD voltage.
The UVLO circuit of VDD-VSS and HB-HS in UCC27714 generate internal signals to enable/disable the outputs
after UVLO_ON/UVLO_OFF thresholds are crossed respectively (please refer to Figure 39). Design
considerations indicate that the UVLO propagation delay before the outputs are enabled and disabled can vary
from 10 μs to 70 μs.
Special attention must be paid to the situation when the VDD-VSS voltage drops rapidly, during abnormal
condition tests such as pin-to-pin shorting. If VDD-VSS voltage drops from VDD(OFF) to a 4-V level in a time that
is less than the propagation delay, then there is a chance for the HO and LO outputs to be latched in the
incumbent state prior to the UVLO incident. For UVLO_OFF logic block to be effective in turning off the outputs,
the VDD-VSS bias voltage must be at least 4 V. Hence, it is recommended that VDD pin voltage is not allowed to
dip from VDD(OFF) to 4 V in 70 μs or less.
Table 1. VDD UVLO Feature Logic Operation
CONDITION (VHB-VHS>VVHB, ON FOR ALL CASES
BELOW)
HI
LI
HO
LO
VDD-VSS < VVDD(on) during device start up
H
L
L
L
VDD-VSS < VVDD(on) during device start up
L
H
L
L
VDD-VSS < VVDD(on) during device start up
H
H
L
L
VDD-VSS < VVDD(on) during device start up
L
L
L
L
VDD-VSS < VVDD(off) after device start up
H
L
L
L
VDD-VSS < VVDD(off) after device start up
L
H
L
L
VDD-VSS < VVDD(off) after device start up
H
H
L
L
VDD-VSS < VVDD(off) after device start up
L
L
L
L
LI
HO
LO
Table 2. VHB UVLO Feature Logic Operation
CONDITION (VDD-VSS > VVDD,ON FOR ALL CASES
BELOW)
HI
VHB-VHS < VVHB(on) during device start up
H
L
L
L
VHB-VHS < VVHB(on) during device start up
L
H
L
H
VHB-VHS < VVHB(on) during device start up
H
H
L
H
VHB-VHS < VVHB(on) during device start up
L
L
L
L
VHB-VHS < VVHB(off) after device start up
H
L
L
L
VHB-VHS < VVHB(off) after device start up
L
H
L
H
VHB-VHS < VVHB(off) after device start up
H
H
L
H
VHB-VHS < VVHB(off) after device start up
L
L
L
L
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VVDD(on)
VVDD(off)
4V
VDD
LI
tDelay
tDelay
LO
VVHB(on)
HB-HS
HI
tDelay
HO
Figure 39. Power-Up Driver
7.3.2 Input and Output Logic Table
UCC27714 features independent inputs, HI and LI, for controlling the state of the outputs, HO and LO,
respectively. The device does not include internal cross-conduction prevention logic and allows both HO and LO
outputs to be turned on simultaneously (refer to Table 3). This feature allows it to be used topologies such as 2transistor forward.
Table 3. Input/Output Logic Table (1)
(Assuming no UVLO fault condition exists for VDD and VHB)
(1)
16
EN/NC
HI
LI
HO
H
H
H
H
LO
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
Any
Any
L
L
Any
×
×
L
L
×
L
L
L
L
×
L
H
L
H
×
H
L
H
L
×
H
H
H
H
× = floating condition
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7.3.3 Input Stage
The input pins of UCC27714 are based on a TTL and CMOS compatible input-threshold logic that is independent
of the VDD supply voltage. With typical high threshold (VINH) of 2.3 V and typical low threshold (VINL) of 1.6 V,
along with very little temperature variation as summarized in Figure 20 and Figure 21, the input pins are
conveniently driven with logic level PWM control signals derived from 3.3-V and 5-V digital power-controller
devices. Wider hysteresis (typically 0.7 V) offers enhanced noise immunity compared to traditional TTL logic
implementations, where the hysteresis is typically less than 0.5 V. UCC27714 also features tight control of the
input pin threshold voltage levels which eases system design considerations and ensures stable operation across
temperature.
The UCC27714 includes an important feature: wherein, whenever any of the input pins is in a floating condition,
the output of the respective channel is held in the low state. This is achieved using GND pull-down resistors on
all the input pins (HI, LI), the input impedance of the input pins (HI, LI) is 400-kΩ typically, as shown in the device
block diagrams.
The UCC27714 input pins are capable of sustaining voltages higher than the bias voltage applied on the VDD
pin of the device, as long as the absolute magnitude is less than the recommended operating condition's
maximum ratings. This features offers the convenience of driving the PWM controller at a higher VDD bias
voltage than the UCC27714 helping to reduce gate charge related switching losses. This capability is envisaged
in UCC27714 by way of two ESD diodes tied back-to-front as shown in Figure 40.
Additionally, the input pins are also capable of sustaining negative voltages below VSS, as long as the
magnitude of the negative voltage is less than the recommended operating condition minimum ratings. A similar
diode arrangement exists between the input pins and VSS as illustrated in Figure 40.
The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied
in typical power supply applications, when the input signals are provided by a PWM controller or logic gates with
fast transition times. With a slow changing input voltage, the output of driver may switch repeatedly at a high
frequency. While the wide hysteresis offered in UCC27714 definitely alleviates this concern over most other TTL
input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall times to the
power device is the primary goal, then an external resistance is highly recommended between the output of the
driver and the power device. This external resistor has the additional benefit of reducing part of the gate-charge
related power dissipation in the gate-driver device package and transferring it into the external resistor itself. If an
RC filter is to be added on the input pins for reducing the impact of system noise and ground bounce, the time
constant of the RC filter must be 20 ns or less, for example, 50 Ω with 220 pF is an acceptable choice.
VDD
7
20 V
HI
1
LI
2
EN/NC
4
20 V
7V
3
VSS
Figure 40. Diode Structure of Input Stage
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7.3.4 Output Stage
The UCC27714 device output stage features a unique architecture on the pull up structure which delivers the
highest peak-source current when it is most needed during the Miller plateau region of the power-switch turn on
transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up
structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the
N-Channel MOSFET is to provide a brief boost in the peak sourcing current enabling fast turn on. This is
accomplished by briefly turning-on the N-Channel MOSFET during a narrow instant when the output is changing
state from low to high.
The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the onresistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC
condition and is turned on only for a narrow instant when output changes state from low to high.
NOTE
The effective resistance of UCC27714 pull-up stage during the turn-on instant is much
lower than what is represented by ROH parameter.
The pull-down structure in UCC27714 is simply composed of a N-Channel MOSFET. The ROL parameter (see
Electrical Characteristics), which is also a DC measurement, is representative of the impedance of the pull-down
stage in the device.
Each output stage in UCC27714 is capable of supplying 4-A peak source and 4-A peak sink current pulses. The
output voltage swings between (VDD and COM) / (HB and HS) providing rail-to-rail operation, thanks to the
MOS-out stage which delivers very low drop-out. The low drop-out voltage is summarized in Figure 23,
Figure 24, Figure 25 and Figure 26
VDD
7
ROH
Input
Voltage
Anti ShootThrough
Circuitry
R NMOS
7 LO
Pull Up
R OL
5
COM
Figure 41. Output Stage Structure
18
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7.3.5 Level Shift
The level shift circuit (refer to the Functional Block Diagram) is the interface from the high-side input to the highside driver stage which is referenced to the switch node (HS). It is a pulsed generated level shifter. With an input
signal the pulse generator generates "on" pulses based on the rising edge of the signal and "off" pulses based
on the falling edge. On pulses and off pulses turn on each branch of the level shifter so that current flows in each
branch to generate different voltages, which is transferred to the set and reset signal in the high side. The signal
is rebuilt by the RS latch in the high side domain. The level shift allows control of the HO output referenced to the
HS pin and provides excellent delay matching with the low-side driver. The delay matching of UCC27714 is
summarized in Figure 6 and Figure 7.
The level shifter in UCC27714 offers best-in-class capability while operating under negative voltage conditions on
HS pin. The level shifter is able to transfer signals from the HI input to HO output with only 4-V headroom
between HB and COM. Refer to Operation Under Negative HS Voltage Condition for detailed explanations.
7.3.6 Low Propagation Delays and Tightly Matched Outputs
The UCC27714 features a best in class, 90-ns (typical) propagation delay (refer to Figure 2, Figure 3, Figure 4
and Figure 5 ) between input and output in high voltage 600-V driver, which goes to offer the lowest level of
pulse-transmission distortion available in the industry for high frequency switching applications.
Figure 42. Turn-On Propagation Delay
Figure 43. Turn-Off Propagation Delay
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7.3.7 Parasitic Diode Structure in UCC27714
Figure 44 illustrates the multiple parasitic diodes involved in the ESD protection components of UCC27714
device. This provides a pictorial representation of the absolute maximum rating for the device.
VDD
HB
7
13
20 V
20 V
HI
1
LI
2
EN/NC
4
20 V
20 V
700 V
20 V
12 HO
11 HS
20 V
7V
7V
20 V
20 V
7V
3
5
VSS
COM
7
VDD
6
LO
Figure 44. ESD Structure
20
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7.4 Device Functional Modes
7.4.1 Enable Function
The enable function is an extremely beneficial feature in applications where the DC-to-DC controller is located on
the secondary side, which is very common with digital controllers. In these applications, it is easy to turn off the
driver signal in a very short time when critical faults such as primary-side overcurrent occurs. The Enable
Function response time is typically around 80 ns, refer to Figure 31, Figure 32 and Figure 45.
The enable pin controls both the high-side and low-side driver-channel operation. The enable pin is based on a
non-inverting configuration (active-high operation). Thus, when EN pin is driven high the driver is enabled and
when EN pin is driven low the driver outputs are low. The EN pin is internally pulled up to VDD using 200-kΩ,
pull-up resistor as a result of which the outputs of the device are enabled in the default state. The EN pin is left
floating or Not Connected (N/C) for standard operation, where the enable feature is not needed. Care must be
taken not to connect the EN pin to ground, which permanently disables the device. Like the input pins, the enable
pin is also based on a TTL and CMOS compatible input-threshold logic that is independent of the supply voltage
and is effectively controlled using logic signal from 3.3-V and 5-V microcontrollers. The UCC27714 also features
tight control of the enable-function-threshold voltage levels which eases system design considerations and
ensures stable operation across temperature (refer to Figure 20 and Figure 21).
Figure 45. EN Function Response Time
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Device Functional Modes (continued)
7.4.2 Minimum Input Pulse Operation
The UCC27714 device has a minimum turn-on, turn-off pulse transfer function to the output pin from the input
pin. This function ensures UCC27714 is in the correct state when the input signal is very narrow. The function is
summarized in Figure 46 and Figure 47. The 100 ns shown in Figure 46 and Figure 47 is ensured by design.
The tON and tOFF parameters in the electrical table are characterized by applying a 100-ns wide input pulses and
monitoring for a corresponding change of state in the outputs.
