UCC28061
UCC2
8060
www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
Natural Interleaving™ Transition-Mode PFC Controller With Improved Audible Noise
Immunity
NATURAL INTERLEAVING FEATURES
SYSTEM FEATURES
• Phase Management Capability
• FailSafe OVP with Dual Paths Prevents Output
Over-Voltage Conditions Caused by
Voltage-Sensing Failures
• Sensorless Current Shaping Simplifies Board
Layout and Improves Efficiency
• Inrush Safe Current Limiting:
– Prevents MOSFET conduction during
inrush
– Eliminates reverse recovery events in
output rectifiers
•
•
•
•
1
23
400 VDC
EMI
Filter
–
+
VCC
85-265VAC
ZCDA
GDA
CS
VINAC ZCDB
UCC28061
GDB
TSET
PWMCNTL
VSENSE
COMP
PHB
•
•
•
•
•
•
Improved Audible Noise Performance
Soft Start on Overvoltage
Integrated Brownout
Improved Efficiency and Design Flexibility
over Traditional, Single-Phase Continuous
Conduction Mode (CCM)
Input Filter and Output Capacitor Current
Cancellation:
– Reduced current ripple for higher system
reliability and smaller bulk capacitor
– Reduced EMI filter size
Enables Use of Low-Cost Diodes without
Extensive Snubber Circuitry
Improved Light-Load Efficiency
Improved Transient Response
Complete System-Level Protection
1-A Source/1.8-A Sink Gate Drivers
APPLICATIONS
Power Good to
downstream converter
VREF
HVSEN
•
•
•
•
•
•
100-W to 800-W Power Supplies
Gaming
D to A Set Top Boxes
Adapters
LCD, Plasma and DLP™ TVs
Home Audio Systems
5
Typical Application Circuit
Capacitor Ripple Current (A)
AGND PGND
POUT = 600 W
VOUT = 400 V
4
1-Phase TM
3
1-Phase CCM
2
2-Phase TM Interleave
1
70
120
170
220
270
Input Voltage (V)
Ripple Current Reduction
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a trademark of Texas Instruments.
Natural Interleaving is a trademark of Texas Instuments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
CONTENTS
•
•
•
•
•
•
•
•
Ordering Information 2
Electrical Characteristics 4
Device Information 7
Functional Block Diagram 9
Typical Characteristics 10
Application Information 16
Design Example 22
Additional References 29
DESCRIPTION
Optimized for consumer applications concerned with audible noise elimination, this solution extends the
advantages of transition mode—high efficiency with low-cost components—to higher power ratings than
previously possible. By utilizing a Natural Interleaving technique, both channels operate as masters (that is, there
is no slave channel) synchronized to the same frequency. This approach delivers inherently strong matching,
faster responses, and ensures that each channel operates in transition mode.
Complete system-level protections feature input brownout, output over-voltage, open-loop, overload, soft-start,
phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection (OVP) feature
protects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic device failure.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
2
PART NUMBER
PACKAGE (2)
OPERATING TEMPERATURE RANGE, TA
UCC28061D
SOIC 16-Pin (D)
–40°C to +125°C
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
SOIC (D) package is available taped and reeled by adding R to the above part number. Reeled quantities for UCC28061DR are 2500
devices per reel.
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ABSOLUTE MAXIMUM RATINGS (1)
All voltages are with respect to GND, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
UCC28061
Input voltage range
VCC (2)
–0.5 to +21
PWMCNTL
–0.5 to +20
COMP (3), CS, PHB, HVSEN (4), VINAC (4), VSENSE (4)
–0.5 to +7
ZCDA, ZCDB
–0.5 to +4
Continuous input current
VCC
20
Input current
PWMCNTL
10
Input current range
ZCDA, ZCDB, VSENSE
Output current
VREF
–10
Continuous gate current
GDA, GDB (5)
±25
Junction temperature, TJ
Lead temperature, TSOL
(1)
(2)
(3)
(4)
(5)
UNIT
V
–5 to +5
mA
Operating
–40 to +125
Storage
–65 to +150
Soldering, 10s
°C
+260
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
Voltage on VCC is internally clamped. VCC may exceed the absolute maximum input voltage if the source is current limited below the
absolute maximum continuous VCC input current level.
In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
In normal use, VINAC, VSENSE, and HVSEN are connected to resistors and are internally limited in voltage swing. Although not
recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as ±10 mA from high voltage
sources.
No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp ringing due to stray inductance. See Figure 12 and Figure 13 for details.
DISSIPATION RATINGS
(1)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = +25°C POWER RATING
TA = +85°C POWER RATING
SOIC 16-Pin (D)
140°C/W (1)
890 mW (1)
460 mW (1)
Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermal
resistance. This number is only a general guide; see TI document SPRA953 device Thermal Metrics.
RECOMMENDED OPERATING CONDITIONS
All voltages are with respect to GND, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
MIN
MAX
VCC input voltage from a low-impedance source
14
21
VCC input current from a high-impedance source
8
18
VREF load current
0
–2
VINAC Input voltage
0
6
ZCDA, ZCDB series resistor
TSET resistor to program PWM on-time
HVSEN input voltage
PWMCNTL pull-up resistor to VREF
UNIT
V
mA
V
20
80
66.5
400
0.8
4.5
V
1
10
kΩ
kΩ
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
RATING
UNIT
Human body model (HBM)
2000
V
Charged device model (CDM)
500
V
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ELECTRICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC BIAS SUPPLY
VCC(shunt)
VCC shunt voltage (1)
IVCC = 10 mA
24
26
V
IVCC(stby)
VCC current, disabled
VSENSE = 0 V
100
200
µA
IVCC(on)
VCC current, enabled
VSENSE = 6 V
5
8
mA
22
UNDERVOLTAGE LOCKOUT (UVLO)
VCC(on)
VCC turn-on threshold
11.5
12.6
13.5
VCC(off)
VCC turn-off threshold
9.5
10.35
11.5
1.85
2.25
2.65
5.82
UVLO Hysteresis
V
REFERENCE
VREF
VREF output voltage, no load
IVREF = 0 mA
6.00
6.18
VREF change with load
0 mA ≤ IVREF ≤ –2 mA
1
6
VREF change with VCC
12 V ≤ VCC ≤ 20 V
1
10
5.85
6.00
6.15
5.82
6.00
6.18
V
mV
ERROR AMPLIFIER
VSENSE input regulation voltage
TA = +25°C
VSENSE input regulation voltage
gm
VOVP
VSENSE input bias current
In regulation
125
300
800
COMP high voltage, clamped
VSENSE = 5.8 V
4.70
4.95
5.10
COMP low voltage, saturated
VSENSE = 6.2 V
0.03
0.125
VSENSE to COMP transconductance
COMP = 3 V,
5.94 V < VSENSE < 6.06 V
75
96
110
COMP source current, overdriven
VSENSE = 5 V, COMP = 3 V
–120
–160
–190
COMP sink current
VSENSE = 6.2 V, COMP = 3 V
7
20
32
VSENSE threshold for COMP offset enable, down
from VREF
Voltage below VREF
135
185
235
6.7
VSENSE over-voltage threshold, rising
6.25
6.45
VSENSE over-voltage hysteresis
0.1
0.2
0.4
VSENSE enable threshold, rising
1.15
1.25
1.35
VSENSE enable hysteresis
0.02
0.05
0.2
2.50
2.65
V
nA
V
µS
µA
mV
V
OUTPUT MONITORING
VPWMCNTL
(1)
4
HVSEN threshold to PWMCNTL
HVSEN rising
2.35
HVSEN input bias current, high
HVSEN = 3 V
–0.5
HVSEN input bias current, low
HVSEN = 2 V
28
36
HVSEN rising threshold to over-voltage fault
4.64
4.87
5.1
HVSEN falling threshold to over-voltage fault
4.45
4.67
4.80
8
12
20
ms
1
µA
0.2
0.5
V
Phase Fail filter time to PWMCNTL high
PHB = 5 V,
ZCDA switching, ZCDB = 0.5 V
PWMCNTL leakage current high
HVSEN = 2 V, PWMCNTL = 15 V
PWMCNTL output voltage low
HVSENS = 3 V, IPWMCNTL = 5 mA
0.5
–1
41
V
µA
V
Excessive VCC input voltage and current will damage the device. This clamp does not protect the device from an unregulated supply. If
an unregulated supply is used, a Fixed Positive Voltage Regulator such as the UA78L15A is recommended. See the Absolute Maximum
Ratings table for the limits on VCC voltage and current.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
15
UNIT
GATE DRIVE (2)
GDA, GDB output voltage high
IGDA, IGDB = –100 mA
11.5
13
GDA, GDB output voltage high, clamped
VCC = 20 V, IGDA, IGDB = –5 mA
12
13.5
15
GDA, GDB output voltage high, low VCC
VCC = 12 V, IGDA, IGDB = –5 mA
10
10.5
11.5
GDA, GDB on-resistance high
IGDA, IGDB = –100 mA
8
14
GDA, GDB output voltage low
IGDA, IGDB = 100 mA
0.15
0.3
V
GDA, GDB on-resistance low
IGDA, IGDB = 100 mA
2
3
Ω
Rise time
1 V to 9 V, CLOAD = 1 nF
18
30
Fall time
9 V to 1 V, CLOAD = 1 nF
12
25
GDA, GDB output voltage UV
IGDA, IGDB = 2.5 mA
1.6
2
V
Ω
ns
V
ZERO CURRENT DETECTOR
ZCDA, ZCDB voltage threshold, falling
0.8
1.0
1.2
ZCDA, ZCDB voltage threshold, rising
1.5
1.68
1.88
3.0
3.4
ZCDA, ZCDB clamp, high
IZCDA = +2 mA, IZCDB = +2 mA
2.6
ZCDA, ZCDB input bias current
ZCDA = 1.4 V, ZCDB = 1.4 V
–0.5
ZCDA, ZCDB clamp, low
IZCDA = –2 mA, IZCDB = –2 mA
–0.4
ZCDA, ZCDB delay to GDA, GDB outputs
(2)
Respective gate drive output rising 10%
from zero crossing input falling to 1 V
V
0.5
µA
–0.2
0
V
45
100
ns
µA
CURRENT SENSE
CS input bias current
–150
–250
CS current limit rising threshold
At rising threshold
–0.18
–0.20
–0.22
CS current limit falling threshold
–0.005
–0.015
–0.029
60
100
ns
0.5
µA
V
CS current limit response time (2)
From CS exceeding threshold –0.05 V to
GDx dropping 10%
VINAC input bias current
VINAC = 2 V
–0.5
VINAC brownout threshold
VINAC falling
1.34
1.39
1.44
V
VINAC brownout current
VINAC = 1 V
5
7
9
µA
VINAC brownout filter time
VINAC fails to exceed the brownout
threshold for the brownout filter time
340
440
540
ms
MAINS INPUT
BROWNOUT
(2)
Refer to Figure 12, Figure 13, Figure 14, and Figure 15 in the Typical Characteristics for typical gate drive waveforms.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PULSE-WIDTH MODULATOR
KTL
KTLS
T(min)
On-time factor, phases A and B
VINAC = 3.2 V, VSENSE = 5.8 V (3)
3.6
4.0
4.4
On-time factor, single-phase, A
VINAC = 3.2 V, VSENSE = 5.8 V,
PHB = 0 V (3)
7.2
8
8.9
Phase B to phase A on-time matching
VSENSE = 5.8 V, VINAC = 3.2 V
–6%
Zero-crossing distortion correction additional on
time
COMP = 0.25 V, VINAC = 1 V
PHB threshold falling, to single-phase operation
PHB threshold rising, to two-phase operation
Minimum switching period
RTSET = 133 kΩ (3)
1.7
2.2
2.5
PWM restart time
ZCDA = ZCDB = 2 V (4)
165
200
265
6%
1.2
2
2.7
12.6
20
29
To GDB output shutdown VINAC = 1.5 V
0.7
0.8
0.9
To GDB output running VINAC = 1.5 V
0.9
1.0
1.1
COMP = 0.25 V, VINAC = 0.1 V
µs/V
µs
V
µs
THERMAL SHUTDOWN
(3)
(4)
(5)
6
Thermal shutdown temperature
TJ, temperature rising (5)
+160
Thermal restart temperature
TJ, temperature falling (5)
+140
°C
Gate drive on-time is proportional to VCOMP – 125 mV. The on-time proportionality factor, KT, is different in two-phase and single-phase
modes. The on-time factor, KT, scales linearly with the value of RTSET. The minimum switching period is proportional to RTSET.
An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart
time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating
temperature is not specified or assured.
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DEVICE INFORMATION
UCC28061D
SOIC 16-Pin (D)
Top View
ZCDB
1
16
ZCDA
VSENSE
2
15
VREF
TSET
3
14
GDA
PHB
4
13
PGND
COMP
5
12
VCC
AGND
6
11
GDB
VINAC
7
10
CS
HVSEN
8
9
PWMCNTL
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
I/O
AGND
6
—
Analog ground: Connect analog signal bypass capacitors, compensation components, and analog
signal returns to this pin. Connect the analog and power grounds at a single point to isolate high-current
noise signals of the power components from interference with the low-current analog circuits.
O
Error amplifier output: The error amplifier is a transconductance amplifier, so this output is a
high-impedance current source. Connect voltage regulation loop compensation components from this
pin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minus
an offset of approximately 125 mV. During soft-start events (undervoltage, brownout, disable or output
over voltage), COMP is pulled low. Normal operation only resumes after the soft-start event clears and
COMP has been discharged below 0.5 V, making sure that the circuit restarts with a low COMP voltage
and a short on-time. Do not connect COMP to a low-impedance source that would interfere with COMP
falling below 0.5 V.
Current sense input: Connect the current sense resistor and the negative terminal of the diode bridge
to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As
input current increases, the voltage on CS goes more negative. This cycle-by-cycle over-current
protection limits input current by turning off both gate driver (GDx) outputs when CS is more negative
than the CS rising threshold (approximately –200 mV). The GD outputs remain low until CS falls to the
CS falling threshold (approximately –15 mV). Current sense is blanked for approximately 100 ns
following the falling edge of either GD output. This blanking filters noise that occurs when current
switches from a power FET to a boost diode. In most cases, no additional current sense filtering is
required. If filtering is required, the filter series resistance must be under 100 Ω to maintain accuracy. To
prevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensing
resistor to the CS pin through a low value external resistor.
COMP
5
CS
10
I
GDA
14
O
GDB
11
O
Channel A and channel B gate drive output: Connect these pins to the gate of the power FET for
each phase through the shortest connection practical. If it is necessary to use a trace longer than 0.5
inch (12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringing
can be reduced by adding a 5-Ω to 10-Ω resistor in series with GDA and GDB.
High voltage output sense: The UCC28061 incorporates FailSafe OVP so that any single failure does
not allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and
HVSEN and shuts down the PWM if either pin exceeds the appropriate over-voltage threshold. Using
two pins to monitor for over-voltage provides redundant protection and fault tolerance. HVSEN can also
be used to enable a downstream power converter when the voltage on HVSEN is within the operating
region. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Select
the HVSEN divider impedance for the desired power-good hysteresis. During operation, HVSEN must
never fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28061 into a special test mode, used
only for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise and
prevent false over-voltage shutdown.
HVSEN
8
I
PGND
13
—
Power ground for the integrated circuit: Connect this pin to AGND through a separate short trace to
isolate gate driver noise from analog signals.
I
Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time for
channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage
constant during the phase management transient. The PHB pin allows the user to add external phase
management circuitry if they desire. To disable phase management, connect the PHB pin to the VREF
pin.
PHB
4
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TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O
PWMCNTL
9
O
PWM enable logic output: This open-drain output goes low when HVSEN is within the HVSEN good
region and the ZCDA and ZCDB inputs are switching correctly if operating in two-phase mode (see PHB
Pin). Otherwise, PWMCNTL is high impedance.
TSET
3
I
Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the
on-time versus COMP voltage and the minimum period at the gate drive outputs.
VCC
12
—
Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect
a 0.1-µF ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This
supply powers all circuits in the device and must be capable of delivering 6 mA dc plus the transient
power MOSFET gate charging current.
VINAC
7
I
Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified
input power mains. When the voltage on VINAC remains below the brownout threshold for more than
the brownout filter time, the device enters a brownout mode and both output drives are disabled. Select
the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the
desired brownout hysteresis.
VREF
15
O
Voltage reference output: Connect a 0.1-µF ceramic bypass capacitor from this pin to AGND. VREF
turns off during VCC undervoltage and VSENSE disable to save supply current and increase efficiency.
This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
I
Output dc voltage sense: Connect this pin to a voltage divider across the output of the power
converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the
desired output voltage. Connect the ground side of this divider to ground through a separate short trace
for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drain
logic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduce
VCC current. If VSENSE is disconnected, open-loop protection provides an internal current source to
pull VSENSE low, turning off the gate drivers.
I
Zero current detection inputs: These inputs expect to see a negative edge when the inductor current
in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupled
through a series resistor that limits the clamping current to less than ±3 mA. Connect these pins through
a current limiting resistor to the zero crossing detection windings of the appropriate boost
I
inductor. The inductor winding must be connected so that this voltage drops when inductor current
decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling
threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off,
the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for another
falling ZCD edge.
VSENSE
ZCDA
ZCDB
8
DESCRIPTION
NAME
2
16
1
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BLOCK DIAGRAM
Overcurrent
CS
HVSENOV
OV
TSD
OC
Burst Operation
SinglePhase
10
OC
-0.2V/-0.015V
+
1.4V
+
440ms Delay
VINAC
STOPA
STOPB
Brownout
7
Thermal
ShutDown
TJ
12.6V
10.35V
+
UV
+
TSD
160C
7mA
12
VCC
14
GDA
11
GDB
13
PGND
8
HVSEN
24V
STOPA
13.5V
Crossover
Notch
Reduction
TSET
3
ZCDA
16
PGND
Interleave
Control
ZCA
13.5V
+
1.68V/1V
ZCDB
Phase A
On Time Control
Phase B
On Time Control
ZCB
1
+
1.68V/1V
222mV
+
STOPB
VREF
6V
15
Brownout
UV
EN
OV
UV
HVSEN OV
+
4.87V
EN
+
gm
VSENSE
+
2
0.8V
4.95V
96ms
2.5V
+
Single
Phase
EN
1.25V
36mA
+
Phase Fail
Detector
6.45V
OV
Phase
OK
+
300nA
5
4
6
9
COMP
PHB
AGND
PWMCNTL
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TYPICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
BIAS SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE
BIAS SUPPLY CURRENT
vs
TEMPERATURE
5.5
6.0
5.0
5.8
4.5
IVCC - Bias Supply Current - mA
IVCC - Bias Supply Current - mA
Operating
4.0
3.5
3.0
2.5
VCC Turn-Off
VCC Turn-On
2.0
1.5
1.0
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
0.5
4.0
0
0
2
4
6
8
10
12
14
16
18
20
-40
-20
0
20
40
60
80
100
120
TJ - Temperature - °C
VVCC - Bias Supply Voltage - V
Figure 1.
Figure 2.
BIAS SUPPLY CURRENT
vs
TEMPERATURE
ERROR AMPLIFIER TRANSFER FUNCTION
40
140
20
Transconductance 96 mS
0
ICOMP - Output Current - mA
IVCC - Bias Supply Current - mA
120
100
80
60
40
20
-20
Input Regulation Voltage
0 mA at 6.0 V
-40
-60
-80
COMP Offset Enable
165 mV Down from
Regulation Voltage
-100
-120
-140
-160
Disabled
Source Current Overdriven -160 mA
0
-180
-40
-20
0
20
40
60
80
100
120
5.5
TJ - Temperature - °C
5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4
6.5
VVSENSE - Input Voltage - V
Figure 4.
Figure 3.
10
Sink Current
25 mA
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ERROR AMPLIFIER TRANSCONDUCTANCE
vs
TEMPERATURE
ERROR AMPLIFIER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
11
110
5.94 V < VSENSE < 6.06 V
10
9
ICOMP - Output Current - mA
gm - Transconductance - ms
105
100
95
90
8
7
6
5
4
3
2
85
1
VSENSE = 6.1 V
80
0
-40
-20
0
20
40
60
80
100
120
0
1
TJ - Temperature - °C
Figure 5.
ERROR AMPLIFIER INPUT BIAS CURRENT
vs
INPUT VOLTAGE
3
4
5
CURRENT SENSE INPUT BIAS CURRENT
vs
TEMPERATURE
150
ICS - Current Sense Input Bias Current - mA
440
400
IVSENSE - Input BiasCurrent - nA
2
VCOMP - Output Voltage - V
Figure 6.
360
320
280
240
200
160
120
80
40
145
140
135
130
125
0
0
0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4
6.0
-40
VVSENSE - Input Voltage - V
Figure 7.
-20
0
20
40
60
80
100
120
TJ - Temperature - °C
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ZERO CURRENT DETECT CLAMP CURRENT
vs
HIGH INPUT VOLTAGE
ZERO CURRENT DETECT CLAMP CURRENT
vs
LOW INPUT VOLTAGE
5
0
-0.5
IZCD - Clamp Current - mA
IZCD - Clamp Current - mA
4
3
2
-1.0
-1.5
-2.0
-2.5
1
-3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-3.5
-0.4
4.0
-0.3
BROWNOUT FILTER DELAY TIME
vs
TEMPERATURE
0.2
0.3
0.4
GATE DRIVE RISING
vs
TIME
500
14
3.0
VCC = 20 V and 12 V
CLOAD = 4.7 nF
490
12
480
2.5
470
10
460
Gate Drive Output - V
Brownout Filter Delay Time - ms
0.1
VZCD - Input Voltage - V
Figure 10.
Figure 9.
450
440
430
420
410
400
390
2.0
GD Voltage:
VCC = 20 V
VCC = 12 V
8
GD Source Current:
VCC = 20 V
VCC = 12 V
6
1.5
1.0
4
0.5
2
0
0
-0.5
380
370
360
350
-2
-1.0
0
-40
-20
0
20
40
60
80
100
50
120
TJ - Temperature - °C
Figure 11.
12
0
-0.2 -0.1
VZCD - Input Voltage - V
Gate Drive Source Current - A
0
100
150
200
250
300
350
Time - ns
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
GATE DRIVE FALLING
vs
TIME
GATE DRIVE RISING
vs
TIME AND DELAY FROM ZCD INPUT
10
8
1.5
6
1.0
4
0.5
2
0
GD Voltage:
VCC = 20 V
VCC = 12 V
0
6
2.5
2.0
GD Sink Current:
VCC = 20 V
VCC = 12 V
40
5
10
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
4
3
6
2
4
1
2
0
60
80
100
120
-1
140
-2
50
-25 0
100
Time - ns
Figure 13.
300
RLOAD = 2.7 kW
12
300
10
200
8
6
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
4
-100
2
-200
0
-300
-2
14
Gate Drive Voltage - V
400
Gate Drive Output - V
Current Sense Input - mV
250
15
14
CLOAD = 4.7 nF
0
200
GATE DRIVE OUTPUT HIGH
vs
VCC
500
CS Input
Voltage
150
Time - ns
Figure 14.
GATE DRIVE FALLING
vs
TIME AND DELAY FROM CS INPUT
100
8
ZCD Input Voltage
-1.0
20
12
0
-0.5
-2
0
14
CLOAD = 4.7 nF
Gate Drive Source Current - A
ZCD Input - V
12
Gate Drive Output - V
7
3.0
VCC = 20 V and 12 V
CLOAD = 4.7 nF
Gate Drive Output - V
14
TJ = -40°C
13
TJ = +25°C
TJ = +125°C
12
11
10
9
-25 0
50
100
150
200
Time - ns
250
300
8
10
11
12
13
14
15
16
17
18
19
20
VVCC - Bias Supply Voltage - V
Figure 16.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
GATE DRIVE OUTPUT IN UVLO
vs
SINK CURRENT
GATE DRIVE HIGH VOLTAGE
vs
TEMPERATURE
2.5
15
14
13
TJ = -40°C
Gate Drive Voltage - V
Gate Drive Voltage - V
2.0
1.5
TJ = +25°C
1.0
TJ = +125°C
0.5
Clamped VCC ³ 15 V
12
11
Unclamped VCC = 12 V
10
9
8
7
6
RLOAD = 2 kW
0
5
0
1
2
3
4
5
6
7
8
9
10
-40
-20
0
ON-TIME FACTOR
vs
TIME SETTING RESISTOR
10
9
9
8
60
60
100
120
RTSET = 266 kW
KTL
7
6
5
4
3
2
KTL - On-Time Factor - ms/V
KT - On-Time Factor - ms/V
40
ON-TIME FACTOR PHASE A AND B
vs
TEMPERATURE
8
7
6
5
RTSET = 133 kW
4
3
2
RTSET = 66 kW
1
1
0
0
60
80 100 120 140 160 180 200 220 240 260 280
-40
RTSET - Time Setting Resistor - kW
Figure 19.
14
20
TJ - Temperature - °C
Figure 18.
Gate Drive Sink Current - mA
Figure 17.
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-20
0
20
40
60
80
100
120
TJ - Temperature - °C
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ON-TIME FACTOR
vs
PHASE SHIFT
PWM RESTART TIME
vs
TEMPERATURE
300
110
GDA
108
GDB
RTSET = 266 kW
275
RTSET = 133 kW
106
KT/KT0 - %
PWM Restart Time - ms
250
104
RTSET = 66 kW
102
100
98
96
225
200
175
150
94
KT0 =
92
2(KTA ´ KTB)
125
KTA + KTB
100
90
150
160
170
180
190
200
-40
210
-20
0
20
40
60
80
100
120
TJ - Temperature - °C
Figure 22.
Phase Shift of GDA Relative to GDB - Degrees
Figure 21.
ADDITIONAL ON-TIME
vs
VINAC ZERO-CROSSING DISTORTION CORRECTION
100
RTSET = 266 kW
Additional On-Time - ms
RTSET = 133 kW
RTSET = 66 kW
10
1
0.1
0
0.5
1.0
1.5
2.0
2.5
3.0
VVINAC - Input AC Voltage Sense - V
Figure 23.
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APPLICATION INFORMATION
Theory of Operation
The UCC28061 contains the control circuits for two boost pulse-width modulation (PWM) power converters. The
boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on
the error amplifier output. Each power converter then turns off the power MOSFET until current in the boost
inductor decays to 0, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductor
current decays to 0, the power converter starts another cycle. This on/off cycling produces a triangle wave of
current, with peak current set by the on-time and power mains input voltage, as shown in Equation 1.
VINAC (t) ´ TON
IPEAK (t) =
L
(1)
The average line current is exactly equal to half of the peak line current, as shown in Equation 2.
VINAC (t) ´ TON
IAVG (t) =
2´L
(2)
With TON and L being essentially constant during an ac line period, the resulting triangular current waveform
during each switching cycle has an average value proportional to the instantaneous value of the rectified ac line
voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a
near-unity power factor.
The outputs of the two PWMs operate 180° out-of-phase so that power-line ripple current for the two PWMs is
greatly reduced from the ripple current of each individual PWM. This design reduces ripple current at the input
and output, allowing the reduction in size and cost of input and output filters.
Optimal phase balance occurs if the individual power stages and the on-times are well-matched. Mismatches in
inductor values do not affect the phase relationship.
On-Time Control, Maximum Frequency Limiting, and Restart Timer
Gate drive on-time varies with the error amplifier output voltage by a factor called KT, as shown in Equation 3.
TON = KT (VCOMP - 125 mV)
(3)
Where:
VCOMP is the output of the error amplifier, and 125 mV is a modulator offset.
To provide smooth transition between two-phase and single-phase operation, KT increases by a factor of two in
single-phase mode:
• KTLS = 2 × KTL; active in single-phase operation
The clamped maximum output of the error amplifier is limited to 4.95 V. This value, less the 125 mV modulator
offset, limits on-time to Equation 4.
TON(max) = KT ´ 4.825 V
(4)
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage level.
The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before the
minimum period timer elapses, turn-on is delayed, resulting in discontinuous phase current.
The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD input
has not transitioned high-to-low for approximately 200 µs. To prevent the circuit from operating in continuous
conduction mode (CCM), the restart time does not trigger turn-on until both phase currents return to 0.
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The on-time factors (KTH, KTHS, KTL, KTLS) and the minimum switching period TMIN are proportional to the time
setting resistor RTSET, the resistor from the TSET pin to ground, and they can be calculated by Equation 5
through Equation 6:
ms
RTSET
KTL =
´ 4.0
V
133 kW
(5)
RTSET
TMIN =
´ 2.2ms; Minimum Switching Period
133 kW
(6)
The proper value of RTSET results in the clamped maximum on-time, TON(max), required by the converter operating
at the minimum input line and maximum load.
Natural Interleaving
Under normal operating conditions, the UCC28061 regulates the relative phasing of the channel A and channel B
inductor currents to be very close to 180°, minimizing the ripple currents seen at the line source and output
capacitor. The phase control function differentially modulates the on-times of the A and B channels based on the
phase and frequency relationship. This natural interleaving method allows the converter to achieve 180° phase
shift and transition mode operation for both phases without the requirements on boost inductor tolerance. As a
result, the current sharing of the A and B channels are proportional to the inductor tolerance. The best current
sharing is achieved when both inductors are exactly the same value.
Phase Management
At light load, it can improve efficiency to shut down one phase. Although conduction losses increase in
one-phase operation, switching losses decrease. At certain power levels, the reduction of switching losses is
greater than the increase in conduction losses. Turning off one phase at light load is especially valuable for
meeting light-load efficient standards.
To operate in two-phase (normal) mode, pull PHB high or connect PHB to VREF. To operate in one-phase
mode, connect PHB to ground.
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Zero Crossing Detection and Valley Switching
In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current crosses 0. Because of the
resonance between the boost inductor and the parasitic capacitor at the MOSFET drain node, part of the energy
stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore, when the
rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET junction
capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate delay,
the MOSFET can be turned on at the valley of its resonating drain voltage (valley switching). In this way, the
energy recovery can be maximized and switching loss is minimized.
The RC time constant is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 24.
Because the ZCD pin is internally clamped, a more accurate delay can also be realized by using Figure 25.
R
R1
ZCD
ZCD
CT
C
CT
Figure 24. Simple RC Delay Circuit
C
R2
Figure 25. More Accurate Time Delay Circuit
Brownout Protection
As the power line RMS voltage decreases, RMS input current increases to maintain the output voltage constant
for a specific load. Brownout protection prevents the RMS input current from exceeding a safe operating level.
Power line RMS voltage is sensed at VINAC. When the voltage applied to VINAC fails to exceed the brownout
threshold for the brownout filter time, a brownout condition is detected and both gate drive outputs immediately
pull low. During brownout, COMP is actively pulled low. Gate drive outputs remain low until the voltage on VINAC
rises above the brownout threshold. After a brownout, the power stage soft-starts as COMP rises.
The brownout detection threshold and its hysteresis are set by the voltage divider ratio and resistor values.
Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on line peak
voltage. The peak VINAC voltage can be easily translated into RMS value. Suggested resistor values for the
voltage divider are 3 MΩ ±1% from the rectified input voltage to VINAC and 46.4 kΩ ±1% from VINAC to ground.
These resistors set the typical thresholds for RMS line voltages, as shown in Table 1.
Table 1. Brownout Thresholds
THRESHOLD
BROWNOUT (RMS)
Falling
65 V
Rising
79.8 V
Failsafe OVP—Output Over-Voltage Protection
FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input
senses an over-voltage condition. The output voltage can still maintain a safe level with either loop failure. The
device is re-enabled when both sense inputs fall back into the normal range. At that time, the gate drive outputs
resume switching under PWM control. Output over-voltage does not cause soft-start and the COMP pin is not
discharged during an output over-voltage event.
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Over-Current Protection
Under certain conditions (such as inrush, brownout recovery, and output overload), the PFC power stage sees
large currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current sensing method uses a shunt resistor in series with the MOSFET source to sense the
converter current, resulting in multiple ground points and high power dissipation. Furthermore, since no current
information is available when the MOSFETs are off, the source resistor current sensing method requires
repeated turn-ons of the MOSFETs during over-current conditions. As a result, the converter may temporarily
operate in continuous current mode (CCM) and experience failures induced by excessive reverse recovery
currents in the boost diode.
The UCC28061 uses a single resistor to continuously sense the total inductor (input) current. This way, turn-on of
the MOSFETs is completely avoided when the inductor currents are excessive. The drive to the MOSFETs is
inhibited until total inductor current drops to near zero, precluding reverse recovery induced failures (these
failures are most likely to occur when the ac line recovers from a brownout condition).
Following an over-current condition, both MOSFETs are turned on in phase when the input current drops to near
0. Because two phase currents are temporarily operating in phase, set the over-current protection threshold to
more than twice of each phase maximum current ripple value in order to allow a return to normal operation after
an over-current event.
Phase Fail Protection
The UCC28061 detects failure of one phase by monitoring the sequence of ZCD pulses. During normal
two-phase operation, if one ZCD input remains idle for longer than approximately 14 ms while the other ZCD
input switches normally, PWMCNTL goes high, indicating that the power stage is not operating correctly. During
normal single-phase operation, phase failure is not monitored. On the UCC28061, phase failure is not monitored
if COMP is below approximately 222 mV.
Distortion Reduction
Because of the resonance between the capacitance present across the drain-source of the switching MOSFET
and the boost inductor, conventional transition mode power factor correction circuits may not be able to absorb
power from the input line when the input voltage is around 0 V. This limitation results in waveform distortion and
increased harmonic distortion. To reduce line current distortion to the lowest possible level, the UCC28061
increases switching MOSFET on-time when input voltage is around 0 V to increase the power absorption and
compensate for this effect.
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Improved Error Amplifier
The voltage error amplifier is a transconductance amplifier. Voltage loop compensation is connected from the
error amplifier output, COMP, to analog ground, AGND. The recommended compensation network is shown in
Figure 26.
REF
COMP
+
VSENSE
CZ
CP
4.95 V
RZ
Figure 26. Typical Error Amplifier Compensation
To improve the transient response, the error amplifier output current is increased by 100 µA when the error amp
input is below 5.8 V, as shown in Figure 27. This increase allows faster charging of the compensation
components following sudden load current increases (also refer to Figure 4 in the Typical Characteristics).
100mA
OV
PWM
Shutdown
+
6.45V
+
5.8V
VSENSE
+g
6V
m
COMP
Soft Start
0.5V
+
Brownout
UV
EN
OV
R
Q
S
Q
Figure 27. Error Amplifier Block Diagram Showing Speed-Up and Latched Soft-Start
The UCC28061 asserts soft start when output over-voltage is detected, pulling COMP to ground. This improves
response to a change from heavy load to light load.
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Open-Loop Protection
If the feedback loop is disconnected from the device, a current source internal to the UCC28061 pulls the
VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device is disabled. When disabled,
supply current decreases, and both gate drive outputs and COMP are actively pulled low. The device is
re-enabled when VSENSE rises above 1.25 V. At that time, the gate drive outputs begin switching under PWM
control.
The device can be externally disabled by grounding the VSENSE pin with an open-drain or open-collector driver.
When disabled, device supply current drops and COMP is actively pulled low. When VSENSE is released, the
device soft-starts. This disable method forces the device into standby mode and minimizes its power
consumption. This feature is particularly useful when standby power is a key design aspect.
If the feedback loop is disconnected from ground, the VSENSE voltage goes high. When VSENSE rises above
the over-voltage protection threshold, both gate drive outputs go low, and COMP is actively pulled low. The
device is re-enabled when VSENSE falls back into range. At that time, the gate drive outputs begin switching
under PWM control. The VSENSE pin is internally clamped to protect the device from damage under this
condition.
Soft-Start
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to
AGND charges from a low level to the final value. This process implements a soft-start, with a time constant set
by the output current of the error amplifier and the value of the compensation capacitors. In the event of a
brownout, logic disable, or VCC undervoltage fault, COMP is actively pulled low so the PWM soft-starts after this
event is cleared. The UCC28061 also asserts soft start when output over-voltage is detected. Even if a fault
event happens very briefly, soft-start fully discharges the compensation components before resuming operation,
ensuring soft-starting. See Figure 27 for details.
Light-Load Operation
As load current decreases, the error amplifier commands less input current by lowering the COMP voltage. If
PHB (normally connected to COMP) falls below 0.8 V at low input line (or 1.1 V at high input line), channel B
stops switching and channel A on-time doubles to compensate. If COMP falls below 150 mV, channel A also
stops switching and the loop enters a hysteretic control mode. The PWM skips cycles to maintain regulation.
Instead of skipping cycles, the UCC28061 allows on-time reduction smoothly to zero as load decreases.
However, maximum switching frequency is limited, so at very light load, discountinuous operation is possible.
Command for the Downstream Converter
In the UCC28061, the PWMCNTL pin is used to coordinate the PFC stage with a downstream converter.
Through the HVSEN pin, the output voltage is sensed. When the output voltage is within the desired range, the
PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. The enable
threshold and hysteresis can be adjusted independently through the voltage divider ratio and resistor values. The
HVSEN pin is also used for the FailSafe over-voltage protection. When designing the voltage divider, make sure
this FailSafe over-voltage protection level is set above normal operating levels.
VCC Undervoltage Protection
VCC must rise above the undervoltage threshold for the PWM to begin functioning. If VCC drops below the
threshold during operation, both gate drive outputs and COMP are actively pulled low. VCC must rise above the
threshold for PWM function to restart.
VCC
VCC is connected to a bias supply of between 13 V and 21 V. When powered from a poorly-regulated supply, an
external zener diode is recommended to prevent excessive current into VCC.
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DESIGN EXAMPLE
An example of the UCC28061 PFC controller in a two-phase transition mode interleaved PFC pre-regulator is
shown in Figure 28.
Bridge
F1
–
+
D3
16V
CIN
CF4
L1
CA
2.2 mF
22 pF
RZA
VCC
ZCDA
CS
GDA
10 nF
COMP
ZCDB
22 pF
COUT
RG2
Q2
5W
HVSEN
CB
RT
CP
RLOAD
RA
VINAC
GDB
VSENSE
2.2 mF
CZ
RC
D2
16 V
50 kW
VREF
L2
20 kW
TSET PWMCNTL
RZ
Q1
5W
RZB
PWMCNTL
RP
PHB
RG1
20 kW
CF5
UCC28061
RS
VOUT
D1
R
100 W
RF
AGND
PGND
CF2
RB
CF3
RD
RE
Figure 28. Typical Transition Mode Interleaved PFC Pre-Regulator
Design Goals
The specifications for this design were chosen based on the power requirements of a 300-W LCD TV. These
specifications are shown in Table 2.
Table 2. Design Specifications
PARAMETER
MIN
TYP
VIN
RMS input voltage
85 (VIN_MIN)
VOUT
Output voltage
fLINE
Line frequency
PF
Power factor at maximum load
0.90
η
Full load efficiency
0.92
fMIN
Minimum switching frequency
UNIT
265
(VIN_MAX)
VRMS
390
47
POUT
22
MAX
45
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V
63
Hz
300
W
kHz
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Recommended PCB Device Layout
CF4
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, the timing setting resistor RT should be put as
close as possible to the TSET pin and returned to the analog ground. See Figure 29 for a recommended
component layout and placement.
Figure 29. Recommended PCB Layout
NOTE:
PHB and VREF Pins are connected by a Jumper on the back of the board.
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Inductor Selection
The boost inductor is selected based on the inductor ripple current requirements at the peak of low line.
Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE),
as shown in Equation 7.
VOUT - VIN_MIN Ö2
390 V - 85 V Ö2
DPEAK_LOW_LINE =
=
» 0.69
VOUT
390 V
(7)
The minimum switching frequency of the converter (fMIN) under low line conditions occurs at the peak of low line
and is set between 25 kHz and 50 kHz to avoid audible noise. For this design example, fMIN was set to 45 kHz:
h ´ VIN_MIN2 x DPEAK_LOW_LINE
0.92(85 V)2 0.69
L1 = L2 =
=
» 340 mH
POUT ´ fMIN
300 W ´ 45 kHz
(8)
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 9, and an RMS
current (ILRMS) of 2.2 A, as shown in Equation 10.
300 W Ö2
POUT Ö2
ILPEAK =
=
» 5.4 A
VIN_MIN ´ h
85 V ´ 0.92
(9)
ILRMS =
ILPEAK
Ö6
=
5.4 A
» 2.2 A
Ö6
(10)
This converter uses constant on-time (TON) and zero-current switching (ZCS) to set up the converter timing.
Auxiliary windings off of L1 and L2 detect when the inductor currents are 0. Selecting the turns ratio in
Equation 11 ensures that there is at least 2 V at the peak of high line to reset the ZCD comparator after every
switching cycle.
The turns-ratio of each auxiliary winding is:
VOUT - VIN_MAX Ö2
NP
390 V - 265 V Ö2
=
=
»8
2V
2V
NS
(11)
ZCD Resistor Selection (RZA, RZB)
The minimum value of the ZCD resistors is selected based on the internal zener clamp maximum current rating
of 3 mA, as shown in Equation 12.
VOUT NS
390 V
RZA = RZB ³
=
» 16.3 kW
NP ´ 3 mA
8 ´ 3 mA
(12)
In this design the ZCD resistors were set to 20 kΩ, as shown in Equation 13.
RZA = RZB = 20 kW
24
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(13)
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HVSENSE
The HVSENSE pin programs the PWMCNTL output of the UCC28061. The PWMCNTL open-drain output can be
used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts in high
impedance and pulls to ground when the HVSENSE increases above 2.5 V. Setting the point where PWMCNTL
becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 14 to
Equation 18 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal
value.
VOUT_OK = VOUT ´ 0.90 » 351 V
(14)
Resistor RE sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal.
For this example, RE was selected to provide 108 V of hysteresis, as shown in Equation 15.
Hysteresis
108 V
RE =
=
= 3 MW
36 mA
36 mA
(15)
Resistor RF is used to program the PWMCNTL active threshold, as shown in Equation 16.
RF =
2.5 V
VOUT_OK - 2.5 V
RE
=
- 36 mA
2.5 V
= 31.185 kW » 31.6 kW
351 V - 2.5 V
- 36 mA
3 MW
(16)
This PWMCNTRL output remains active until a minimum output voltage (VOUT_MIN) is reached, as shown in
Equation 17.
2.5 V (RE + RF)
2.5 V (3 MW + 31.6 kW)
VOUT_MIN =
=
» 240 V
31.6 kW
RF
(17)
According to the resistor value, the FailSafe OVP threshold should be set according to Equation 18:
4.87 V (RE + RF) 4.87 V (3 MW + 31.6 kW)
VOV_FAILSAFE =
=
» 467 V
31.6 kW
RF
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Output Capacitor Selection
The output capacitor (COUT) is selected based on holdup requirements as shown in Equation 19.
POUT
1
300 W 1
2 h
2
fLINE
0.92 47 Hz
COUT ³
=
» 147 mF
2
2
2
2
VOUT - (VOUT_MIN)
(390 V) - (240 V)
(19)
Two 100-µF capacitors were used in parallel for the output capacitor:
COUT = 200 mF
(20)
For this size capacitor, the output voltage ripple (VRIPPLE) is approximately 11 V, as shown in Equation 21:
VRIPPLE =
2 ´ POUT
1
2 ´ 300 W
=
» 14V
h
VOUT ´ 4 p ´ fLINE ´ COUT 0.92 ´ 390V ´ 4 p ´ 47 Hz ´ 200 m F
(21)
In addition to hold-up requirements, a capacitor must be selected so that it can withstand the low-frequency RMS
current (ICOUT_100 Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 22 to Equation 24.
High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current rating on the
product data sheets.
POUT
300 W
ICOUT_100Hz =
=
= 0.591 A
390 V ´ 0.92 ´ Ö2
VOUT ´ h ´ Ö2
(22)
2
ICOUT_HF =
POUT 2 Ö2
4 Ö2 VIN_MIN
2 ´ h ´ VIN_MIN
9p VOUT
- (ICOUT_100 Hz)2
(23)
2
ICOUT_HF =
300 W ´ 2 Ö2
2 ´ 0.92 ´ 85 V
4 Ö2 ´ 85 V
9p ´ 390 V
- (0.591 A)2
» 0.966 A
(24)
26
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Selecting an RS for Peak Current Limiting
The UCC28061 peak limit comparator senses the total input current and is used to protect the MOSFETs during
inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for
120% of the nominal inrush current that is observed during power-up, as shown in Equation 25.
2POUT Ö2 (1.2)
2 ´ 300 W Ö2 ´ 1.2
=
IPEAK =
» 13 A
h ´ VIN_MIN
0.92 ´ 85 V
(25)
A standard 15-mΩ metal-film current-sense resistor is used for current sensing, as shown in Equation 26. The
estimated power loss of the current sense resistor (PRS) is less than 0.25 W during normal operation, as shown
in Equation 27.
200 mV
200 mV
RS =
=
» 15 mW
IPEAK
13 A
(26)
PRS =
2
POUT
VIN_MIN ´ h
2
RS =
300 W
85 V ´ 0.92
´ 15 mW » 0.22 W
(27)
The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to
withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere squared
seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal
to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was
chosen to protect the design from a short-circuit condition. To ensure the current-sense resistors have a high
enough surge protection, a 15-MΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a
2.5-W surge rating for 5 seconds. This result translates into 833 A2s and has a high enough I2t rating to survive a
short-circuit before the fuse opens, as described in Equation 28.
2.5 W
I2t =
´ 5 s = 833 A2s
0.015 W
(28)
Power Semiconductor Selection (Q1, Q2, D1, D2):
The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note
SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-Regulator, explains how to
select power semiconductor components for transition-mode PFC pre-regulators.
The MOSFET maximum-pulsed drain current (Q1, Q2) is shown in Equation 29:
IDM ³ IPEAK = 13 A
(29)
The MOSFET RMS current calculation (Q1, Q2) is shown in Equation 30:
IDS =
IPEAK
2
4 Ö2 VIN_MIN
13 A
1
=
6
2
9p ´ VOUT
4 Ö2 ´ 85 V
1
6
9p ´ 390 V
» 2.3 A
(30)
To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.
The boost diode RMS current (D1, D2) is shown in Equation 31:
ID =
IPEAK
4 Ö2 VIN_MIN
2
9p ´ VOUT
=
13 A
2
4 Ö2 ´ 85 V
9p ´ 390 V
» 1.4 A
(31)
To meet the power requirements of the design, MURS306T3 600-V diodes from On Semiconductor were chosen
for the design for D1 and D2.
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Brownout Protection
Resistor RA and RB are selected to activate brownout protection at 75% of the specified minimum operated input
voltage. Resistor RA programs the brownout hysteresis comparator, which was selected to provide 21 V of
hysteresis. RA and RB are shown in Equation 32 and Equation 33.
In this design example, brownout becomes active when the input drops below 64 VRMS and deactivates when the
input reaches 79 VRMS.
Hysteresis
21 V
RA =
=
» 3 MW
7 mA
7 mA
(32)
1.4 V ´ RA
1.4 V ´ 3 MW
RB =
=
» 47 kW
85 V ´ 0.75 Ö2 - 1.4 V
VIN_MIN ´ 0.75 Ö2 - 1.4 V
(33)
Converter Timing
Select the timing resistor, RTSET, for the correct on-time (TON) based on KTL, as shown in Equation 34. To ensure
proper operation, the timing must be set based on the highest boost inductance (L1MAX). In this design example,
the boost inductor could be as high as 390 µH, based on line and load conditions, as shown in Equation 35.
h ´ (VIN_MIN)2 1 fMIN =
VIN_MIN ´ Ö2
0.92 ´ (85 V)2 1 -
VOUT
=
POUT ´ L1MAX
133 kW 1 RTSET =
300 W ´ 390 mH
VIN_MIN ´ Ö2
VOUT
4.85 V ´ 4 ms ´ fMIN
133 kW 1 =
85 V ´ Ö2
390 V
85 V ´ Ö2
390 V
4.85 V ´ 4 ms ´ 39.2 kHz
= 39.2 kHz
(34)
» 121 kW
(35)
This result sets the maximum frequency clamp (fMAX), as shown in Equation 36, which improves efficiency at light
load.
133 kW
133 kW
fMAX =
» 550 kHz
=
2 ms ´ R T
2 ms ´ 121 kW
(36)
Programming VOUT
Resistor RC is selected to minimize error because of VSENSE input bias current and minimize loading on the
power line when the PFC is disabled. Construct resistor RC from two or more resistors in series to meet
high-voltage requirements. RC was also selected to be of a similar value of RA and RE to simplify the bill of
materials and reduce design costs.
Based on the resistor values shown in Equation 37 to Equation 39, the primary output over-voltage protection
threshold should be as shown in Equation 40:
RC = 3 MW
(37)
VREF = 6 V
RD =
(VOUT - VREF)
VOVP = 6.45 V
28
(38)
VREF ´ RC
=
RC + RD
RD
6 V ´ 3 MW
» 47 kW
(390 V - 6V)
(39)
3 MW + 47 kW
= 6.45 V
= 418 V
47 kW
(40)
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Loop Compensation
Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low input current harmonic distortion.
The transconductance amplifier gain is shown in Equation 41:
gm = 96 mS
(41)
The voltage divider feedback gain is shown in Equation 42 and Equation 43:
VREF
6V
H=
=
» 0.015
390 V
VOUT
(42)
100 mV
100 mV
RZ =
=
= 6.313 kW » 6.34 kW
11 V ´ 0.015 ´ 96 mS
VRIPPLE ´ H ´ gm
(43)
CZ is then set to add 45° of phase margin at 1/5th of the switching frequency, as shown in Equation 44:
1
1
CZ =
=
= 2.67 mF
fLINE
47 Hz
2p ´
´ 6.34 kW
2p ´
´ RZ
5
5
(44)
CP is sized to attenuate high-frequency noise, as shown in Equation 45:
1
1
CP =
=
= 1.12 nF
fMIN
45 kHz
2p ´
´ 6.34 kW
2p ´
´ RZ
2
2
(45)
The standard values of Equation 46 and Equation 47 should be chosen for CZ and CP.
CZ = 2.2 mF
(46)
CP = 1 nF
(47)
ADDITIONAL REFERENCES
Related Parts
Table 3 lists several TI parts that have characteristics similar to the UCC28061.
Table 3. Related Parts
DEVICE
DESCRIPTION
UCC28051
PFC controller for low to medium power applications
UCC28019
8-pin continuous conduction mode (CCM) PFC controller
UCC28060
Natural Interleaving™ Dual-Phase Transition-Mode PFC Controller
References
These references, design tools, and links to additional references, including design software, may be found at
www.power.ti.com:
• Evaluation Module, UCC28060EVM 300W interleaved PFC Pre-regulator, SLUU280 from Texas Instruments
• Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator,
SLUU138 from Texas Instruments
Package Outline and Recommended PCB Footprint
The mechanical packages at the end of this data sheet outline the mechanical dimensions of the 16-pin D
(SOIC) package and provide recommendations for PCB layout.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28061D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28061
UCC28061DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28061
UCC28061DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28061
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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