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UCC28070
SLUS794F – NOVEMBER 2007 – REVISED APRIL 2016
UCC28070 Interleaving Continuous Conduction Mode PFC Controller
1 Features
3 Description
•
The UCC28070 is an advanced power factor
correction (PFC) device that integrates two pulsewidth modulators (PWMs) operating 180° out of
phase. This interleaved PWM operation generates
substantial reduction in the input and output ripple
currents, allowing the conducted-EMI filtering to
become easier and less expensive. A significantly
improved multiplier design provides a shared current
reference to two independent current amplifiers that
ensures matched average-current mode control in
both PWM outputs while maintaining a stable, lowdistortion, sinusoidal input-line current.
1
•
•
•
•
•
•
•
•
•
•
•
•
Interleaved Average Current-Mode PWM Control
With Inherent Current Matching
Advanced Current Synthesizer Current Sensing
for Superior Efficiency
Highly-Linear Multiplier Output With Internal
Quantized Voltage Feed-Forward Correction for
Near-Unity PF
Programmable Frequency from 30 kHz to 300 kHz
Programmable Maximum Duty-Cycle Clamp
Programmable Frequency-Dithering Rate and
Magnitude for Enhanced EMI Reduction
– Magnitude: 3 kHz to 30 kHz
– Rate: Up to 30 kHz
External-Clock Synchronization Capability
Enhanced Load and Line Transient Response
through Voltage Amplifier Output Slew-Rate
Correction
Programmable Peak Current Limiting
Bias-Supply UVLO, Overvoltage Protection, OpenLoop Detection, and PFC-Enable Monitoring
External PFC-Disable Interface
Open-Circuit Protection on VSENSE and VINAC
pins
Programmable Soft-Start
The UCC28070 device contains multiple innovations
including current synthesis and quantized voltage
feed-forward to promote performance enhancements
in PF, efficiency, THD, and transient response.
Features including frequency dithering, clock
synchronization, and slew rate enhancement further
expand the potential performance enhancements.
The UCC28070 device also contains a variety of
protection features including output-overvoltage
detection,
programmable
peak-current
limit,
undervoltage lockout, and open-loop protection.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
High-Efficiency Server and Desktop Power
Supplies
Telecom Rectifiers
White Goods and Industrial Equipment
PACKAGE
BODY SIZE (NOM)
UCC28070DW
SOIC (20)
12.80 mm × 7.50 mm
UCC28070DWR
SOIC (20)
12.80 mm × 7.50 mm
UCC28070PW
TSSOP (20)
6.50 mm × 4.40 mm
UCC28070PWG4
TSSOP (20)
6.50 mm × 4.40 mm
UCC28070PWR
TSSOP (20)
6.50 mm × 4.40 mm
UCC28070PWRG4 TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
VIN
L1
D1
+
VOUT
COUT
–
12V to 21V
To CSB
CCDR
1 CDR
DMAX 20
RRDM
2 RDM
RT 19
RA
3 VAO
RB
SS 18
4 VSENSE
GDB 17
5 VINAC
GND 16
RIMO
6 IMO
RSYN
7 RSYNTH
T1
RS
RDMX
RRT
CSS
M1
VCC 15
GDA 14
8 CSB
VREF 13
9 CSA
CAOA 12
L2
D2
To CSA
10 PKLMT
CAOB 11
RS
From Ixfrms
CZV
RPK1
CPV
CZC
CREF
CPC
T2
RA
CZC
CPC
M2
RPK2
RZV
RZC
RZC
RB
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28070
SLUS794F – NOVEMBER 2007 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 28
8
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application .................................................. 29
9 Power Supply Recommendations...................... 37
10 Layout................................................................... 38
10.1 Layout Guidelines ................................................. 38
10.2 Layout Example .................................................... 38
11 Device and Documentation Support ................. 39
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2011) to Revision F
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision D (June 2010) to Revision E
•
2
Page
Changed PWM switching frequency....................................................................................................................................... 6
Changes from Revision C (June 2009) to Revision D
•
Page
Page
Changed 30 kHz to 300 kHz .................................................................................................................................................. 1
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SLUS794F – NOVEMBER 2007 – REVISED APRIL 2016
5 Pin Configuration and Functions
DW and PW Packages
20-Pin SOIC and TSSOP
Top View
CDR
1
20
DMAX
RDM
2
19
RT
VAO
3
18
SS
VSENSE
4
17
GDB
VINAC
5
16
GND
IMO
6
15
VCC
RSYNTH
7
14
GDA
CSB
8
13
VREF
CSA
9
12
CAOA
10
11
CAOB
PKLMT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CAOA
12
O
Phase A Current Amplifier Output. Output of phase A transconductance current amplifier. Internally connected
to the inverting input of phase A PWM comparator for trailing-edge modulation. Connect the current regulation
loop compensation components between this pin and GND.
CAOB
11
O
Phase B Current Amplifier Output. Output of phase B transconductance current amplifier. Internally connected
to the inverting input of phase B PWM comparator for trailing-edge modulation. Connect the current regulation
loop compensation components between this pin and GND.
CDR
1
I
Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs the rate of
oscillator dither. Connect the CDR pin to the VREF pin to disable dithering.
CSA
9
I
Phase A Current Sense Input. During the ON-time of GDA, CSA is internally connected to the inverting input of
phase A current amplifier through the current synthesis stage.
CSB
8
I
Phase B Current Sense Input. During the ON-time of GDB, CSB is internally connected to the inverting input of
phase B current amplifier through the current synthesis stage.
DMAX
20
I
Maximum Duty-Cycle Resistor. Maximum PWM duty-cycle programming pin. A resistor to GND sets the PWM
maximum duty-cycle based on the ratio of RDMX / RRT.
GDA
14
O
Phase A Gate Drive. This limited-current output is intended to connect to a separate gate-drive device suitable
for driving the phase A switching component(s). The output voltage is typically clamped to 13.5 V.
GDB
17
O
Phase B Gate Drive. This limited-current output is intended to connect to a separate gate-drive device suitable
for driving the phase B switching component(s). The output voltage is typically clamped to 13.5 V.
GND
16
I/O
Device Ground Reference. Connect all compensation and programming resistor and capacitor networks to this
pin. Connect this pin to the system through a separate trace for high-current noise isolation.
IMO
6
O
Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier gain.
PKLMT
10
I
Peak Current Limit Programming. Connect a resistor-divider network between VREF and this pin to set the
voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows adjustment for desired ΔILB.
RDM
(SYNC)
2
I
Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An external
resistor to GND programs the magnitude of oscillator frequency dither. When frequency dithering is disabled
(CDR > 5 V), the internal master clock synchronizes to positive edges presented on the RDM pin. Connect
RDM to GND when dithering is disabled and synchronization is not desired.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
RSYNTH
7
I
Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to set the
magnitude of the current synthesizer down-slope. Connecting RSYNTH to VREF disables current synthesis and
connect CSA and CSB directly to their respective current amplifiers.
RT
19
I
Timing Resistor. Oscillator frequency programming pin. A resistor to GND sets the running frequency of the
internal oscillator.
SS
18
I
Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the soft-start slew rate
based on an internally-fixed, 10-μA current source. The regulation reference voltage for VSENSE is clamped to
VSS until VSS exceeds 3 V. Upon recovery from certain fault conditions, a 1-mA current source is present at the
SS pin until the SS voltage equals the VSENSE voltage. Pulling the SS pin below 0.6 V immediately disables
both GDA and GDB outputs.
VAO
3
O
Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally connected to the
multiplier input and the zero-power comparator. Connect the voltage regulation loop compensation components
between this pin and GND.
VCC
15
I
Bias Voltage Input. Connect a 0.1-μF ceramic bypass capacitor as close as possible to this pin and GND.
VINAC
5
I
Scaled AC Line Input Voltage. Internally connected to the multiplier and negative terminal of the current
synthesis difference amplifier. Connect a resistor-divider network between VIN, VINAC, and GND identical to
the PFC output divider network connected at VSENSE.
VREF
13
O
6-V Reference Voltage and Internal Bias Voltage. Connect a 0.1-μF ceramic bypass capacitor as close as
possible to this pin and GND.
VSENSE
4
I
Output Voltage Sense. Internally connected to the inverting input of the transconductance voltage error
amplifier in addition to the positive terminal of the current synthesis difference amplifier. Also connected to the
OVP, PFC enable, and slew-rate comparators. Connect to PFC output with a resistor-divider network.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Supply voltage
VCC
Supply current, IVCC
MAX
UNIT
22
V
20
mA
Gate drive current – continuous
GDA, GDB
±0.25
A
Gate drive current – pulsed
GDA, GDB
±0.75
GDA, GDB
–0.5
VCC + 0.3
DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA,
CSB, CAOA, CAOB, PKLMT, VREF
–0.5
7
RT, DMAX, RDM, RSYNTH
–0.5
Voltage
Current
VREF, VAO, CAOA, CAOB, IMO
A
mA
10
Lead temperature (10 seconds)
V
260
°C
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
UNIT
VUVLO + 1 V
21
V
2
mA
Input voltage (from a low-impedance source)
VCC
Load current
VREF
Input voltage range
VINAC
0
3
V
Voltage range
IMO
0
3.3
V
VPKLMT
Voltage range
CSA, CSB
0
3.6
V
RSYN
RSYNTH resistance
15
750
kΩ
RRDM
RDM resistance
30
330
kΩ
6.4 Thermal Information
UCC28070
THERMAL METRIC
(1)
SOIC (DW)
TSSOP (PW)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
78.1
99.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.5
34.1
°C/W
RθJB
Junction-to-board thermal resistance
46
50.8
°C/W
ψJT
Junction-to-top characterization parameter
17.5
1.9
°C/W
ψJB
Junction-to-board characterization parameter
45.5
50.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TA = –40°C to 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF,
CSS = CVREF = 0.1 μF, CVCC = 1 μF, IVREF = 0 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
23
25
27
UNIT
BIAS SUPPLY
VCC(SHUNT) VCC shunt voltage
IVCC
(1)
Supply current
IVCC = 10 mA
disabled
VVSENSE = 0 V
7
enabled
VVSENSE = 3 V (switching)
9
UVLO
VUVLO
VCC = 7 V
VCC = 9 V
UVLO turnon threshold
Measured at VCC (rising)
UVLO hysteresis
Measured at VCC (falling)
VREF enable threshold
Measured at VCC (rising)
9.8
12
V
mA
200
µA
4
6
mA
10.2
10.6
1
V
7.5
8
8.5
V
6
6.18
V
LINEAR REGULATOR
VVREF
(1)
Reference voltage
no load
IVREF = 0 mA
5.82
load
rejection
Measured as the change in VVREF
(IVREF = 0 mA and –2 mA)
–12
12
line
rejection
Measured as the change in VVREF
(VCC = 11 V and 20 V, IVREF = 0 μA)
–12
12
mV
Excessive VCC input voltage or current damages the device. This clamp does not protect the device from an unregulated supply. If an
unregulated supply is used, TI recommends a series-connected fixed positive voltage regulator such as a UA78L15A. See Absolute
Maximum Ratings for the limits on VCC voltage and current.
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Electrical Characteristics (continued)
TA = –40°C to 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF,
CSS = CVREF = 0.1 μF, CVCC = 1 μF, IVREF = 0 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.65
0.75
0.85
UNIT
PFC ENABLE
Enable threshold
VEN
Measured at VSENSE (rising)
Enable hysteresis
0.15
V
EXTERNAL PFC DISABLE
Disable threshold
Measured at SS (falling)
Hysteresis
VVSENSE > 0.85 V
0.5
0.6
V
0.15
V
OSCILLATOR
Output phase shift
Measured between GDA and GDB
179
180
181
°
VDMAX,
VRT, and
VRDM
Timing regulation voltages
Measured at DMAX, RT, and RDM
2.91
3
3.09
V
95
100
105
fPWM
PWM switching frequency
270
290
330
92%
95%
98%
50
150
250
DMAX
RRT = 75 kΩ, RDMX = 68.1 kΩ,
VRDM = 0 V, VCDR = 6 V
kHz
RRT = 24.9 kΩ, RDMX = 22.6 kΩ,
VRDM = 0 V, VCDR = 6 V
Duty-cycle clamp
RRT = 75 kΩ, RDMX = 68.1 kΩ,
VRDM = 0 V, VCDR = 6 V
Minimum programmable OFF-time
RRT = 24.9 kΩ, RDMX = 22.6 kΩ,
VRDM = 0 V, VCDR = 6 V
fDM
Frequency dithering magnitude
change in fPWM
RRDM = 316 kΩ, RRT = 75 kΩ
fDR
Frequency dithering rate of change
in fPWM
CCDR = 2.2 nF, RRDM = 100 kΩ
3
CCDR = 0.3 nF, RRDM = 100 kΩ
20
ICDR
Dither rate current
Measured at CDR (sink and source)
Dither disable threshold
Measured at CDR (rising)
5
5.25
V
SYNC enable threshold
Measured at CDR (rising)
5
5.25
V
SYNC propagation delay
VCDR = 6 V, measured from RDM (rising) to
GDx (rising)
50
100
ns
SYNC threshold (rising)
VCDR = 6 V, measured at RDM
1.2
1.5
V
SYNC threshold (falling)
VCDR = 6 V, measured at RDM
0.4
SYNC pulses
Positive pulse width
0.2
RRDM = 31.6 kΩ, RRT = 24.9 kΩ
2
3
4
24
30
36
ns
kHz
kHz
μA
±10
CLOCK SYNCHRONIZATION
VCDR
Maximum duty cycle
0.7
V
μs
(2)
50%
VOLTAGE AMPLIFIER
gMV
(2)
6
VSENSE voltage
In regulation, TA = 25°C
2.97
VSENSE voltage
In regulation
2.94
VSENSE input bias current
In regulation
VAO high voltage
VVSENSE = 2.9 V
VAO low voltage
VVSENSE = 3.1 V
VAO transconductance
VVSENSE = 2.8 V to 3.2 V, VVAO = 3 V
70
μS
VAO sink current, overdriven limit
VVSENSE = 3.5 V, VVAO = 3 V
30
μA
VAO source current, overdriven
VVSENSE = 2.5 V, VVAO = 3 V, SS = 3 V
–30
μA
VAO source current,
overdriven limit + ISRC
VVSENSE = 2.5 V, VVAO = 3 V
–130
μA
Slew-rate correction threshold
Measured as VVSENSE (falling) / VVSENSE
(regulation)
4.8
92%
3
3.03
3
3.06
V
250
500
nA
5
5.2
V
0.05
0.50
V
93%
V
95%
Due to the influence of the synchronization pulse width on the programmability of the maximum PWM switching duty cycle (DMAX), TI
recommends minimizing the synchronization signal duty cycle.
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Electrical Characteristics (continued)
TA = –40°C to 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF,
CSS = CVREF = 0.1 μF, CVCC = 1 μF, IVREF = 0 mA (unless otherwise noted)
PARAMETER
ISRC
TEST CONDITIONS
Slew-rate correction hysteresis
Measured at VSENSE (rising)
Slew-rate correction current
Measured at VAO, in addition to VAO
source current
Slew-rate correction enable
threshold
Measured at SS (rising)
VAO discharge current
MIN
TYP
MAX
3
9
UNIT
mV
–100
μA
4
V
VVSENSE = 0.5 V, VVAO = 1 V
10
μA
SS source current
VVSENSE = 0.9 V, VSS = 1 V
–10
μA
Adaptive source current
VVSENSE = 2 V, VSS = 1 V
–1.5
–2.5
mA
Adaptive SS disable
Measured as VVSENSE – VSS
–30
0
30
mV
SS sink current
VVSENSE = 0.5 V, VSS = 0.2 V
0.5
0.9
104%
106%
SOFT-START
ISS
mA
OVERVOLTAGE
VOVP
OVP threshold
Measured as VVSENSE (rising) / VVSENSE
(regulation)
OVP hysteresis
Measured at VSENSE (falling)
100
OVP propagation delay
Measured between VSENSE (rising) and
GDx (falling)
0.2
108%
mV
0.3
μs
ZERO-POWER
VZPWR
Zero-power detect threshold
Measured at VAO (falling)
0.65
Zero-power hysteresis
0.75
V
0.15
V
MULTIPLIER
kMULT
IIMO
Gain constant
Output current: zero
VVAO ≥ 1.5 V, TA = 25°C
16
17
18
VVAO = 1.2 V, TA = 25°C
14.5
17
19.5
VVAO ≥ 1.5 V
15
17
19
VVAO = 1.2 V
13
17
21
VVINAC = 0.9 VPK, VVAO = 0.8 V
–0.2
0
0.2
VVINAC = 0 V, VVAO = 5 V
–0.2
0
0.2
0.6
0.7
0.8
μA
μA
QUANTIZED VOLTAGE FEED-FORWARD
(3)
VLVL1
Level 1 threshold
VLVL2
Level 2 threshold
Measured at VINAC (rising)
1
V
V
VLVL3
Level 3 threshold
1.2
V
VLVL4
Level 4 threshold
1.4
V
VLVL5
Level 5 threshold
1.65
V
VLVL6
Level 6 threshold
1.95
V
VLVL7
Level 7 threshold
2.25
V
VLVL8
Level 8 threshold
2.6
V
6
V
CURRENT AMPLIFIERS
CAOx high voltage
5.75
CAOx low voltage
gMC
0.1
CAOx transconductance
CAOx sink current, overdriven
CAOx source current, overdriven
Input common mode range
Input offset voltage
(3)
μS
50
μA
–50
μA
0
VRSYNTH = 6 V, TA = 25°C
VRSYNTH = 6 V
V
100
3.6
–4
–8
–13
0
–8
–20
V
mV
The Level 1 threshold represents the zero-crossing detection threshold above which VVINAC must rise to initiate a new input half-cycle,
and below which VVINAC must fall to terminate that half-cycle.
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Electrical Characteristics (continued)
TA = –40°C to 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 68.1 kΩ, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF,
CSS = CVREF = 0.1 μF, CVCC = 1 μF, IVREF = 0 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input offset voltage
MIN
TYP
MAX
UNIT
0
–8
–20
mV
12
mV
Phase mismatch
Measured as phase A input offset minus
phase B input offset
–12
0
CAOx pulldown current
VVSENSE = 0.5 V, VCAOx = 0.2 V
0.5
0.9
mA
CURRENT SYNTHESIZER
VRSYNTH
Regulation voltage
Synthesizer disable threshold
VVSENSE = 3 V, VVINAC = 0 V
2.91
3
3.09
VVSENSE = 3 V, VVINAC = 2.85 V
0.10
0.15
0.20
5
5.25
V
0.250
0.500
μA
3.3
3.33
V
60
100
ns
3.8
4
4.2
V
0.65
0.7
V
–2
mV/°C
Measured at RSYNTH (rising)
VINAC input bias current
V
PEAK CURRENT LIMIT
Peak current limit threshold
VPKLMT = 3.30 V, measured at CSx (rising)
Peak current limit propagation delay
Measured between CSx (rising) and GDx
(falling) edges
3.27
PWM RAMP
VRMP
PWM ramp amplitude
PWM ramp offset voltage
TA = 25°C, RRT = 75 kΩ
PWM ramp offset temperature
coefficient
GATE DRIVE
8
GDA, GDB output voltage, high,
clamped
VCC = 20 V, CLOAD = 1 nF
GDA, GDB output voltage, high
CLOAD = 1 nF
GDA, GDB output voltage, low
CLOAD = 1 nF
0.2
0.3
V
Rise time GDx
1 V to 9 V, CLOAD = 1 nF
18
30
ns
Fall time GDx
9 V to 1 V, CLOAD = 1 nF
12
25
ns
GDA, GDB output voltage, UVLO
VCC = 0 V, IGDA, IGDB = 2.5 mA
0.7
2
V
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11.5
13
10
10.5
15
V
V
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6.6 Typical Characteristics
12
6.18
IVCC, VCC = 12 V, enabled
6.12
Reference Voltage (V)
Supply Current (mA)
10
8
IVCC, VCC = 12 V, disabled
6
4
6.06
6.00
5.94
5.88
2
5.82
0
–60
–40
–20
20
0
40
60
80
100
120
140
–60
–10
40
90
140
Temperature (°C)
Temperature (°C)
VVREF = 0 mA
Figure 1. VCC Supply Current vs Junction Temperature
Figure 2. VVREF vs Junction Temperature
0.50
3.06
0.45
0.40
0.35
3.02
Bias Current (mA)
VSENSE Regulation (V)
3.04
3.00
2.98
0.30
0.25
0.20
0.15
0.10
2.96
0.05
0
2.94
–60 –40
–20
0
20
40
60
80
100
–60
120 140
–10
40
90
140
Temperature (°C)
Temperature (°C)
Figure 3. VVSENSE Regulation vs Junction Temperature
Figure 4. IVSENSE Bias Current vs Junction Temperature
20
180
QVFF Level
Level 1
160
Level 3
120
Multiplier Constant (mA)
Multiplier Output Current (mA)
19
Level 2
140
Level 4
Level 5
100
Level 6
80
Level 7
Level 8
60
18
17
16
VAO
1.2 V
1.5 V
3V
5V
40
15
20
14
0
0
1
2
3
4
5
6
–60 –40
–20
0
20
40
60
80
100 120 140
Voltage Amplifier Output (V)
Temperature (°C)
Figure 5. IMO, Multiplier Output Current vs VVAO
Figure 6. Multiplier Constant vs Junction Temperature
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Typical Characteristics (continued)
0.50
0.45
0.40
Bias Current (mA)
0.35
0.30
0.25
0.20
0.15
VINAC
0.2 V
1V
2V
2.5 V
2.85 V
0.10
0.05
0.00
–60
–10
40
90
Normalized Change in Switching Frequency (%)
1
Typical Frequency = 30 kHz
RT = 249 kΩ
0.8
0.5
Typical Frequency = 100 kHz
RT = 75 kΩ
0.3
0
–0.3
Typical Frequency = 290 kHz
RT = 24.9 kΩ
–0.5
–0.8
–1
140
–60 –40
–20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Figure 7. IVINAC Bias Current vs Junction Temperature
Figure 8. Normalized Switching Frequency vs
Junction Temperature
40
80
Voltage Amplifier Output Current (mA)
Voltage Amplifier Transconductance (nS)
20
75
70
65
60
0
–20
–40
–60
–80
–100
55
–120
–140
50
–60 –40 –20
0
20
40
60
80
100
2.5
120 140
2.6
2.7
2.8
3.0
2.9
3.1
3.2
3.3
3.4
3.5
Temperature (°C)
VSENSE (V)
Figure 9. VAO, Voltage Amplifier Transconductance vs
Junction Temperature
Figure 10. Voltage Amplifier Transfer Function vs VVSENSE
110
5
105
100
CAx Input Offset (mV)
CAOx Tranjsconductance (nS)
0
95
90
CAx + 3 σ
–5
CAx AVG
–10
CAx - 3 σ
–15
85
80
–20
–60 –40 –20
0
20
40
60
80
100 120 140
–60
Temperature (°C)
–40 –20
0
20
40
60
80
100
120 140
Temperature (°C)
0.8-V Common Mode
Figure 11. Current Amplifier Transconductance vs
Junction Temperature
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Figure 12. CAx Input Offset Voltage vs
Junction Temperature
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Typical Characteristics (continued)
5
10
0
A-B+3σ
CAx Input Offset (mV)
CA1 to CA2 Relative Offset Voltage (mV)
15
5
0
A - B AVG
–5
CAx + 3 σ
–5
CAx AVG
–10
CAx - 3 σ
A-B-3σ
–15
–10
–20
–60
–15
–60 –40
–20
0
20
40
60
80
100
120 140
–40
–20
0
0.8-V Common Mode
40
60
80
100
120
140
2-V Common Mode
Figure 13. CA1 to CA2 Relative Offset vs
Junction Temperature
Figure 14. CAx Input Offset Voltage vs
Junction Temperature
5
15
10
0
A-B+3σ
CAx Input Offset (mV)
CA1 to CA2 Relative Offset Voltage (mV)
20
Temperature (°C)
Tempterature (°C)
5
0
A - B AVG
–5
CAx + 3 σ
–5
CAx AVG
–10
CAx - 3 σ
A-B-3σ
–15
–10
–20
–15
–60 –40 –20
0
20
40
60
80
–60 –40 –20
100 120 140
Temperature (°C)
0
20
40
60
80
100 120
140
Temperature (°C)
2-V Common Mode
3.6-V Common Mode
Figure 15. CA1 to CA2 Relative Offset vs
Junction Temperature
Figure 16. CAx Input Offset Voltage vs
Junction Temperature
CA1 to CA2 Relative Offset Voltage (mV)
15
10
A-B+3σ
5
0
A - B AVG
–5
A-B-3σ
–10
–15
–60 –40 –20
0
20
40
60
80
100 120
140
Temperature (°C)
3.6-V Common Mode
Figure 17. CA1 to CA2 Relative Offset vs Junction Temperature
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7 Detailed Description
7.1 Overview
The UCC28070 power factor corrector IC controls two CCM (Continuous Conduction Mode) Boost PFC power
stages operating 180° out of phase with each other. This interleaving action reduces the input and output ripple
currents so that less EMI filtering is needed and allows operation at higher power levels than a non-interleaved
solution.
The UCC28070 can operate over a wide range of frequencies, making it suitable for use with both MOSFET and
IGBT power switches. Multiple UCC28070 controllers can be synchronized for use in higher power applications
where more than two interleaved power stages are needed.
This device is especially suited to high-performance, high-power PFC applications where the use of Average
Current Mode PWM control gives low THD.
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7.2 Functional Block Diagram
+
OVP
VCC 15
25V
Linear EN
VREF 13 6V Regulator
160 On o
140 Off
C
+
ReStart
ThermSD
Ext.Disable
0.75V
+ 0.60V
SS
8V
0.75V
0.60V
VSENSE
3.18V
3.08V
Fault
S Q
+
VSENSE
R Q
0.90V
GND 16
UVLO
10.2V
9.2V
ZeroPwr
+ 0.75V
+
VAO
6
IMO
5 VINAC
DMAX 20
Voltage
FeedForward
CLKA
Oscillator w/
Freq. Dither
RT 19
CLKB
IIMO =
VVINAC ∗ (VVAO – 1)
KVFF
OffA
∗ 17uA
250nA
KVFF
x
OffB
Mult.
/
3 VAO
x
RDM/
2
SYNC
SYNC
Logic
CDR 1
SYNC Dither
Enable Disable
+
ReStart
100uA
5V
+
SS
4V
Slew Rate
Correction
+
10uA
2.8V
5V
GmAmp
4 VSENSE
-
VA +
3V
+
250nA
Adaptive SS
PKLMT 10
IpeakA
1mA
ReStart
ISS
10uA
+
+
Control
Logic
ReStart
Ext.Disable
IpeakB
CSA 9
+
+
18 SS
PWM1
CA1
GmAmp
+
S Q
OutA
CSB 8
Current
Synthesizer
RSYNTH 7
5V
CLKA
R Q
VINAC
VSENSE
CAOA 12
14 GDA
PWM2
CA2
GmAmp
Driver
GND
Fault
+
Disable
+
OffA
IpeakA
OutB
VCC
(Clamped at 13.5V)
VCC
S Q
+
OffB
IpeakB
Fault
CAOB 11
CLKB
R Q
(Clamped at 13.5V)
Driver
17 GDB
GND
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7.3 Feature Description
7.3.1 Interleaving
One of the main benefits from the 180° interleaving of phases is significant reductions in the high-frequency
ripple components of both the input current and the current into the output capacitor of the PFC preregulator.
Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the
burden of filtering conducted-EMI noise and helps reduce the EMI filter and CIN sizes. Additionally, reduced highfrequency ripple current into the PFC output capacitor, COUT, helps to reduce its size and cost. Furthermore, with
reduced ripple and average current in each phase, the boost inductor size can be smaller than in a single-phase
design [1].
Ripple current reduction due to interleaving is often referred to as ripple cancellation, but strictly speaking, the
peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other
than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual
phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC preregulator,
those of a 2-phase interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation, the
frequency of the interleaved ripple, at both the input and output, is 2 × fPWM.
On the input, 180° interleaving reduces the peak-to-peak ripple amplitude to ½ or less of the ripple amplitude of
the equivalent single-phase current.
On the output, 180° interleaving reduces the rms value of the PFC-generated ripple current in the output
capacitor by a factor of slightly more than √2, for PWM duty-cycles > 50%.
This can be seen in the following derivations, adapting the method by Erickson [2].
In a single-phase PFC preregulator, the total rms capacitor current contributed by the PFC stage at all dutycycles can be shown to be approximated by:
æI ö
iCRMS1j = ç O ÷
èhø
æ æ 16 ´ VO ö
ö
2
h
çç ç
÷
÷
÷
è è 3p ´ VM ø
ø
(1)
In a dual-phase interleaved PFC preregulator, the total rms capacitor current contributed by the PFC stage for
D > 50% can be shown to be approximated by:
æI ö
iCRMS2j = ç O ÷
èhø
æ æ 16 ´ VO ö
ö
2
çç ç
÷ - h ÷÷
è è 6p ´ VM ø
ø
(2)
In these equations, IO = average PFC output load current, VO = average PFC output voltage, VM = peak of the
input ac-line voltage, and η = efficiency of the PFC stage at these conditions. It can be seen that the quantity
under the radical for iCrms2φ is slightly smaller than ½ of that under the radical for iCrms1φ. The rms currents shown
contain both the low-frequency and the high-frequency components of the PFC output current. Interleaving
reduces the high-frequency component, but not the low-frequency component.
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Feature Description (continued)
7.3.2 Programming the PWM Frequency and Maximum Duty-Cycle Clamp
The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through
the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor
(RRT) directly sets the PWM frequency (fPWM).
RRT (kW ) =
7500
fPWM (kHz )
(3)
Once RRT has been determined, the DMAX resistor (RDMX) may be derived.
RDMX = RRT ´ (2 ´ DMAX - 1)
where
•
DMAX is the desired maximum PWM duty-cycle
(4)
7.3.3 Frequency Dithering (Magnitude and Rate)
Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise
beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which
results in equal time spent at every point along the switching frequency range. This total range from minimum to
maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency
fPWM set with RRT. For example, a dither magnitude of 20 kHz on a nominal fPWM of 100 kHz results in a
frequency range of 100 kHz ±10 kHz. Furthermore, the programmed duty-cycle clamp set by RDMX remains
constant at the programmed value across the entire range of the frequency dithering.
The rate at which fPWM traverses from one extreme to the other and back again is defined as the dither rate. For
example, a dither rate of 1 kHz would linearly modulate the nominal frequency from 110 kHz to 90 kHz to
110 kHz once every millisecond. A good initial design target for dither magnitude is ±10% of fPWM. Most boost
components can tolerate such a spread in fPWM. The designer can then iterate around there to find the best
compromise between EMI reduction, component tolerances, and loop stability.
The desired dither magnitude is set by a resistor from the RDM pin to GND, of value calculated with Equation 5:
RRDM (kW ) =
937.5
fDM (kHz )
(5)
Once the value of RRDM is determined, the desired dither rate may be set by a capacitor from the CDR pin to
GND, of value calculated with Equation 6:
æ R (kW) ö
CCDR (pF ) = 66.7 ´ ç RDM
÷
è fDR (kHz) ø
(6)
Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and
connecting the RDM pin directly to GND. (If populated, the relatively high impedance of the RDM resistor may
allow system switching noise to couple in and interfere with the controller timing functions if not bypassed with a
low impedance path when dithering is disabled.)
If an external frequency source is used to synchronize fPWM and frequency dithering is desired, the external
frequency source must provide the dither magnitude and rate functions as the internal dither circuitry is disabled
to prevent undesired performance during synchronization. (See External Clock Synchronization for more details.)
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Feature Description (continued)
7.3.4 External Clock Synchronization
The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By
disabling frequency dithering (pulling CDR > 5 V), the SYNC circuitry is enabled permitting the internal oscillator
to be synchronized with pulses presented on the RDM pin. To ensure a precise 180° phase shift is maintained
between the GDA and GDB outputs, the frequency (fSYNC) of the pulses presented at the RDM pin must be at
twice the desired fPWM. For example, if a 100-kHz switching frequency is desired, the fSYNC should be 200 kHz.
fPWM =
fSYNC
2
(7)
To ensure the internal oscillator does not interfere with the SYNC function, RRT must be sized to set the internal
oscillator frequency at least 10% below fSYNC.
RRT (kW ) =
15000
´ 1.1
fSYNC (kHz )
(8)
It must be noted that the PWM modulator gain is reduced by a factor equivalent to the scaled RRT due to a direct
correlation between the PWM ramp current and RRT. Adjustments to the current loop gains should be made
accordingly.
It must also be noted that the maximum duty-cycle clamp programmability is affected during external
synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the
falling edge of the synchronization pulse. Therefore, the selection of RDMX becomes dependent on the
synchronization pulse width (tSYNC).
DSYNC = t SYNC ´fSYNCFor use in RDMX equation immediately below.
(9)
æ 15000 ö
RDMX (kW ) = ç
÷ ´ (2 ´ DMAX - 1 - DSYNC )
è fSYNC (kHz) ø
(10)
Consequently to minimize the impact of the tSYNC it is clearly advantageous to use the smallest synchronization
pulse width feasible.
NOTE
When external synchronization is used, a propagation delay of approximately 50 ns to 100
ns exists between internal timing circuits and the falling edge of the SYNC signal, which
may result in reduced OFF-time at the highest of switching frequencies. Therefore, RDMX
should be adjusted downward slightly by (tSYNC – 0.1 μs) / tSYNC to compensate. At lower
SYNC frequencies, this delay becomes an insignificant fraction of the PWM period, and
can be neglected.
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Feature Description (continued)
7.3.5 Multi-phase Operation
External synchronization also facilitates using more than 2 phases for interleaving. Multiple UCC28070s can
easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate
phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be
obtained. (An odd number of phases can be accommodated if desired, but the ripple cancellation would not be
optimal.) For 4-, 6-, or any 2 × n-phases (where n = the number of UCC28070 controllers), each controller should
receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application
interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation.
Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for
optimal ripple cancellation.
In a multi-phase interleaved system, each current loop is independent and treated separately; however, there is
only one common voltage loop. To maintain a single control loop, all VSENSE, VINAC, SS, IMO, and VAO
signals are paralleled, respectively between the n controllers. Where current-source outputs are combined (SS,
IMO, VAO), the calculated load impedances must be adjusted by 1/n to maintain the same performance as with
a single controller.
Figure 18 illustrates the paralleling of two controllers for a 4-phase 90-degree-interleaved PFC system.
7.3.6 VSENSE and VINAC Resistor Configuration
The primary purpose of the VSENSE input is to provide the voltage feedback from the output to the voltage
control loop. Thus, a traditional resistor-divider network must be sized and connected between the output
capacitor and the VSENSE pin to set the desired output voltage based on the 3-V regulation voltage on
VSENSE.
A unique aspect of the UCC28070 is the need to place the same resistor-divider network on the VIN side of the
inductor to the VINAC pin. This provides the scaled input voltage monitoring needed for the linear multiplier and
current synthesizer circuitry. It is not required that the actual resistance of the VINAC network be identical to the
VSENSE network, but it is necessary that the attenuation (kR) of the two divider networks be equivalent for
proper PFC operation.
kR =
RB
(R A + RB )
(11)
In noisy environments, it may be beneficial for small filter capacitors to be applied to the VSENSE and VINAC
inputs to avoid the destabilizing effects of excessive noise on these inputs. If applied, the RC time-constant
should not exceed 100 μs on the VSENSE input to avoid significant delay in the output transient response. The
RC time-constant should also not exceed 100 μs on the VINAC input to avoid degrading of the wave-shape zerocrossings. Usually, a time constant of 3 / fPWM is adequate to filter out typical noise on VSENSE and VINAC.
Some design and test iteration may be required to find the optimal amount of filtering required in a particular
application.
7.3.7 VSENSE and VINAC Open-Circuit Protection
Both the VSENSE and VINAC pins have been designed with an internal 250-nA current sink to ensure that in the
event of an open circuit at either pin, the voltage is not left undefined, and the UCC28070 remains in a safe
operating mode.
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Feature Description (continued)
VIN
–
L1
D1
+
To CSB1
VREF1
RA
RB
RDMX1
1 CDR
DMAX 20
2 RDM
RT 19
3 VAO
SS 18
4 VSENSE
GDB 17
5 VINAC
GND 16
6 IMO
VCC 15
7 RSYNTH
GDA 14
CSB1
8 CSB
VREF 13
9 CSA
CAOA 12
T1
RS1
RRT1
M1
12V to 21V
L2
VREF1
D2
From Ixfrms
To CSA1
CSA1
10 PKLMT
CAOB 11
T2
RSYN1
RS2
M2
CZV
RIMO
CPV
CREF
CPC
CPC
RPK2
CZC
CZC
RPK1
CSS
RZV
RZC
RZC
VOUT
RZC
RZC
RA
COUT
CPC
CZC
CPC
CZC
RB
CREF
Vin
L3
D3
RSYN2
To CSA2
10 PKLMT
T3
RS3
CAOB 11
CSA2
9 CSA
CAOA 12
8 CSB
VREF 13
From Ixfrms
VREF2
M3
CSB2
7 RSYNTH
GDA 14
6 IMO
VCC 15
5 VINAC
GND 16
4 VSENSE
GDB 17
3 VAO
SS 18
2 RDM
RT 19
1 CDR
DMAX 20
12V to 21V
L4
D4
RRT2
To CSB2
Synchronized
Clocks
with 180°
Phase Shift
RDMX2
RS4
T4
M4
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Figure 18. Simplified Four-Phase Application Diagram Using Two UCC28070 Devices
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Feature Description (continued)
7.3.8 Current Synthesizer
One of the most prominent innovations in the UCC28070 design is the current synthesizer circuitry that
synchronously monitors the instantaneous inductor current through a combination of ON-time sampling and OFFtime down-slope emulation.
During the ON-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins,
respectively, through the current transformer network in each output phase. Meanwhile, the continuous
monitoring of the input and output voltages through the VINAC and VSENSE pins permits the UCC28070 to
internally recreate the down-slope of the inductor current during the respective OFF-time of each output. Through
the selection of the RSYNTH resistor (RSYN), based on Equation 12, the internal response may be adjusted to
accommodate the wide range of inductances expected across the wide array of applications.
During inrush surge events at power up and AC drop-out recovery, VVSENSE < VVINAC, the synthesized downslope
becomes zero. In this case, the synthesized inductor current remains above the IMO reference and the current
loop drives the duty cycle to zero. This avoids excessive stress on the MOSFETs during the surge event. Once
VVINAC falls below VVSENSE, the duty cycle increases until steady-state operation resumes.
Waveform at
CSx input
Synthesized
down-slope
Current Synthesizer
output to CA
Figure 19. Downslope of the Inductor Current
RSYN (kW ) =
(10 ´ N
CT
´ LB (mH)´ k R )
RS (W )
where:
•
•
•
•
LB = Nominal Zero-Bias Boost Inductance (μH)
RS = Sense Resistor (Ω)
NCT = Current-sense Transformer turns ratio
kR = RB / (RA + RB) = the resistor-divider attenuation at the VSENSE and VINAC pins
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Feature Description (continued)
7.3.9 Programmable Peak Current Limit
The UCC28070 has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling
either the GDA or GDB output whenever the corresponding current-sense input (CSA or CSB, respectively) rises
above the voltage established on the PKLMT pin. Once an output has been disabled through the detection of
peak current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The
programming range of the PKLMT voltage extends to upwards of 4 V to permit the full use of the 3-V average
current sense signal range; however, note that the linearity of the current amplifiers begins to compress above
3.6 V.
A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT,
provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. TI
recommends a load of less than 0.5 mA, but if the resistance on PKLMT is very high, TI recommends a small
filter capacitor on PKLMT to avoid operational problems in high-noise environments.
Externally Programmable Peak
Current Limit level (PKLMT)
PKLMT
10
IPEAKx
+
To Gate-Drive
Shut-down
CSx
Current
Synthesizer
DI
To Current
Amplifier
3V Average Current-sense
Signal Range, plus Ripple
Figure 20. Externally Programmable Peak Current Limit
7.3.10 Linear Multiplier and Quantized Voltage Feed Forward
The UCC28070 multiplier generates a reference current which represents the desired wave shape and
proportional amplitude of the AC input current. This current is converted to a reference voltage signal by the RIMO
resistor which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier
current is dependent upon the rectified, scaled input voltage VVINAC and the voltage-error amplifier output VVAO.
VVINAC conveys three pieces of information to the multiplier:
• The overall wave-shape of the input voltage (typically sinusoidal)
• The instantaneous input voltage magnitude at any point in the line cycle
• The rms level of the input voltage.
VVAO represents the total output power of the PFC preregulator.
A major innovation in the UCC28070 multiplier architecture is the internal quantized VRMS feed-forward (QVFF)
circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow
response to transient line variations. A unique circuit algorithm detects the transition of the peak of VVINAC
through seven thresholds and generates an equivalent VFF level centered within the 8-QVFF ranges. The
boundaries of the ranges expand with increasing VIN to maintain an approximately equal-percentage delta
between levels. These 8-QVFF levels are spaced to accommodate the full universal line range of 85 to 265 VRMS.
20
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Feature Description (continued)
A great benefit of the QVFF architecture is that the fixed kVFF factors eliminate any contribution to distortion of the
multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion
components. Furthermore, the QVFF algorithm allows for rapid response to both increasing and decreasing
changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in
the level thresholds help avoid chattering between QVFF levels for VVINAC voltage peaks near a particular
threshold or containing mild ringing or distortion. The QVFF architecture requires that the input voltage be largely
sinusoidal, and relies on detecting zero-crossings to adjust QVFF downward on decreasing input voltage. Zerocrossings are defined as VVINAC falling below 0.7 V for at least 50 μs, typically.
Table 1 shows the relationship between the various VVINAC peak voltages and the corresponding kVFF terms for
the multiplier equation.
Table 1. VVINAC Peak Voltages
VVINAC PEAK VOLTAGE
kVFF (V2)
8
2.6 V ≤ VVINAC(pk)
3.857
>345 V
7
2.25 V ≤ VVINAC(pk) < 2.6 V
2.922
300 V to 345 V
6
1.95 V ≤ VVINAC(pk) < 2.25 V
2.199
260 V to 300 V
5
1.65 V ≤ VVINAC(pk) < 1.95 V
1.604
220 V to 260 V
4
1.4 V ≤ VVINAC(pk) < 1.65 V
1.156
187 V to 220 V
3
1.2 V ≤ VVINAC(pk) < 1.4 V
0.839
160 V to 187 V
2
1 V ≤ VVINAC(pk) < 1.2 V
0.600
133 V to 160 V
1
VVINAC(pk) ≤ 1 V
0.398
10.2 V, and 1 V of hysteresis assures reliable start-up
from a possibly low-compliance bias source. An internal 25-V Zener-like clamp on the VCC pin is intended only
to protect the device from brief energy-limited surges from the bias supply, and should not be used as a regulator
with a current-limited source.
At minimum, a 0.1-μF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to
provide local filtering of the bias supply. Larger values may be required depending on ICC peak current
magnitudes and durations to minimize ripple voltage on VCC.
To provide a smooth transition out of UVLO and to make the 6-V voltage reference available as early as
possible, the output from VREF is enabled when VCC exceeds 8 V typically.
The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally.
At minimum, a 22-nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to
ensure stability of the circuit. External load current on the VREF pin should be limited to less than 2 mA, or
degraded regulation may result.
7.3.13 PFC Enable and Disable
The UCC28070 contains two independent circuits dedicated to disabling the GDx outputs based on the biasing
conditions of the VSENSE or SS pins. The first is a PFC Enable which monitors VVSENSE and holds off soft-start
and the overall PFC function until the output has pre-charged to approximately 25%. Prior to VVSENSE reaching
0.75 V, almost all of the internal circuitry is disabled. Once VVSENSE reaches 0.75 V and VVAO < 0.75 V, the
oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage on
the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable the
GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6 V,
the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present, normal
PWM operation resumes when the external SS pulldown is released. The external pulldown must be sized large
enough to override the internal 1.5-mA adaptive SS pullup once the SS voltage falls below the disable threshold.
TI recommends using a MOSFET with less than 100-Ω RDS(on) resistance to ensure the SS pin is held
adequately below the disable threshold.
7.3.14 Adaptive Soft Start
To maintain a controlled power up, the UCC28070 has been designed with an adaptive soft-start function that
overrides the internal reference voltage with a controlled voltage ramp during power up. On initial power up, once
VVSENSE exceeds the 0.75-V enable threshold (VEN), the internal pulldown on the SS pin is released, and the
1.5‑mA adaptive soft-start current source is activated. This 1.5-mA pull-up almost immediately pulls the SS pin to
0.75 V (VVSENSE) to bypass the initial 25% of dead time during a traditional 0 V to Vregulation SS ramp. Once the
SS pin has reached the voltage on VSENSE, the 10-μA soft-start current (ISS) takes over. Thus, through the
selection of the soft-start capacitor (CSS), the effective soft-start time (tSS) may be easily programmed based on
Equation 21.
æ 2.25 V ö
t SS = CSS ´ ç
÷
è 10 mA ø
(21)
Often, a system restart is desired following a brief shut-down. In such a case, VSENSE may still have substantial
voltage if VOUT has not fully discharged or if high line has peak charged COUT. To eliminate the delay caused by
charging CSS from 0 V up to the precharged VVSENSE with only the 10-μA current source and minimize any further
output voltage sag, the adaptive soft start uses a 1.5-mA current source to rapidly charge CSS to VVSENSE, after
which time the 10-μA source controls the VSS rise at the desired soft-start ramp rate. In such a case, tSS is
estimated as follows:
æ 3 V - VVSENSE0 ö
t SS = CSS ´ ç
÷
10 mA
è
ø
where
•
VVSENSE0 is the voltage at VSENSE at the moment a soft start or restart is initiated
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NOTE
For soft start to be effective and avoid overshoot on VOUT, the SS ramp must be slower
than the voltage-loop control response. Choose CSS ≥ CVZ to ensure this.
(V)
VSS
VVSENSE
VSS if no adaptive current
Time (s)
PFC externally
disabled due to
AC-line drop-out
Reduced delay to regulation
AC-Line recovers
and SS pin released
Figure 21. Soft-Start Ramp Rate
7.3.15 PFC Start-Up Hold Off
An additional feature designed into the UCC28070 is the Start-Up Hold Off logic that prevents the device from
initiating a soft-start cycle until the VAO pin is below the zero-power threshold (0.75 V). This feature ensures that
the SS cycle initiates from zero-power and zero duty-cycle while preventing the potential for any significant inrush
currents due to stored charge in the VAO compensation network.
7.3.16 Output Overvoltage Protection (OVP)
Because of the high voltage output and a limited design margin on the output capacitor, output overvoltage
protection is essential for PFC circuits. The UCC28070 implements OVP through the continuous monitoring of
VVSENSE. In the event VVSENSE rises above 106% of regulation (3.18 V), the GDx outputs are immediately
disabled to prevent the output voltage from reaching excessive levels. Meanwhile the CAOx outputs are pulled
low to ensure a controlled recovery starting from 0% duty-cycle after an OVP fault is released. Once VVSENSE has
dropped below 3.08 V, the PWM operation resumes normal operation.
7.3.17 Zero-Power Detection
To prevent undesired performance under no-load and near no-load conditions, the UCC28070 zero-power
detection comparator is designed to disable both GDA and GDB outputs in the event VVAO voltage falls below
0.75 V. The 150 mV of hysteresis ensures that the outputs remain disabled until VVAO has nearly risen back into
the linear range of the multiplier (VVAO ≥ 0.9 V).
7.3.18 Thermal Shutdown
To protect the power supplies from silicon failures at excessive temperatures, the UCC28070 has an internal
temperature-sensing comparator that shuts down nearly all of the internal circuitry, and disables the GDA and
GDB outputs, if the die temperature rises above 160°C. Once the die temperature falls below 140°C, the device
brings the outputs up through a typical soft start.
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7.3.19 Current Loop Compensation
The UCC28070 incorporates two identical and independent transconductance-type current-error amplifiers (one
for each phase) with which to control the shaping of the PFC input current waveform. The current-error amplifier
(CA) forms the heart of the embedded current control loop of the boost PFC preregulator, and is compensated
for loop stability using familiar principles [4, 5]. The output of the CA for phase-A is CAOA, and that for phase-B
is CAOB. Because the design considerations are the same for both, they are collectively referred to as CAOx,
where x is A or B.
In a boost PFC preregulator, the current control loop comprises the boost power plant stage, the current sensing
circuitry, the wave-shape reference, the PWM stage, and the CA with compensation components. The CA
compares the average boost inductor current sensed with the wave-shape reference from the multiplier stage
and generates an output current proportional to the difference.
This CA output current flows through the impedance of the compensation network generating an output voltage,
VCAO, which is then compared with a periodic voltage ramp to generate the PWM signal necessary to achieve
PFC.
IMO
CAOx
+
CAx
–
CSx
Current
Synthesizer
CZC
gmC = 100 µs
CPC
RZC
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Current Error Amplifier With Type II Compensation
For frequencies above boost LC resonance and below fPWM, the small-signal model of the boost stage, which
includes current sensing, can be simplified to:
VOUT ´ NRCTS
v RS
=
v CA DVRMP ´ k SYNC ´ s ´ LB
where:
•
•
•
•
•
•
•
LB = mid-value boost inductance
RS = CT sense resistor
NCT = CT turns ratio
VOUT = average output voltage
∆VRMP = 4 Vpk-pk amplitude of the PWM voltage ramp
kSYNC = ramp reduction factor (if PWM frequency is synchronized to an external oscillator; kSYNC = 1, otherwise)
s = Laplace complex variable
(23)
An RZCCZC network is introduced on CAOx to obtain high gain for the low-frequency content of the inductor
current signal, but reduced flat gain above the zero frequency out to fPWM to attenuate the high-frequency
switching ripple content of the signal (thus averaging it).
The switching ripple voltage should be attenuated to less than 1/10 of the ΔVRMP amplitude so as to be
considered negligible ripple.
Thus, CAOx gain at fPWM is:
gmc ´ Rzc £
DVRMP ´k SYNC
10
RS
LB
NCT
DI ´
where:
•
•
∆ILB is the maximum peak-to-peak ripple current in the boost inductor
gmc is the transconductance of the CA, 100 μS
(24)
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Rzc £
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4 V ´ NCT
10 ´ 100 ms ´ DILB ´ RS
(25)
The current-loop cross-over frequency is then found by equating the open loop gain to 1 and solving for fCXO:
fCXO =
VOUT ´ NRCTS
DVRMP ´ k SYNC ´ 2p ´ LB
´ gmc ´ Rzc
(26)
CCZ is then determined by setting fZC = fCXO = 1 / (2πRZC × CZC) and solving for CZC. At fZC = fCXO, a phase
margin of 45° is obtained at fCXO. Greater phase margin may be had by placing fZC < fCXO.
An additional high-frequency pole is generally added at fPWM to further attenuate ripple and noise at fPWM and
higher. This is done by adding a small-value capacitor, Cpc, across the RzcCzcnetwork.
Cpc =
1
2p ´ fPWM ´ Rzc
(27)
The procedure above is valid for fixed-value inductors.
NOTE
If a swinging-choke boost inductor (inductance decreases with increasing current) is used,
fCXO varies with inductance, so CZC should be determined at maximum inductance.
7.3.20 Voltage Loop Compensation
The outer voltage control loop of the dual-phase PFC controller functions the same as with a single-phase
controller, and compensation techniques for loop stability are standard [4]. The bandwidth of the voltage-loop
must be considerably lower than the twice-line ripple frequency (f2LF) on the output capacitor to avoid distortioncausing correction to the output voltage. The output of the voltage-error amplifier (VVAO) is an input to the
multiplier to adjust the input current amplitude relative to the required output power. Variations on VAO within the
bandwidth of the current loops influences the wave-shape of the input current. Because the low-frequency ripple
on COUT is a function of input power only, its peak-to-peak amplitude is the same at high-line as at low-line. Any
response of the voltage-loop to this ripple has a greater distorting effect on high-line current than on low-line
current. Therefore, the allowable percentage of 3rd-harmonic distortion on the input current contributed by VAO
should be determined using high-line conditions.
Because the voltage-error amplifier (VA) is a transconductance type of amplifier, the impedance on its input has
no bearing on the amplifier gain, which is determined solely by the product of its transconductance (gmv) with its
output impedance (ZOV). Thus, the VSENSE input divider-network values are determined separately based on
criteria discussed in VSENSE and VINAC Resistor Configuration. Its output is the VAO pin.
VAO
3V
+
VA
–
VSENSE
CZV
gmv = 70 µs
CPV
RZV
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Voltage Error Amplifier With Type II Compensation
The twice-line ripple voltage component of VVSENSE must be sufficiently attenuated and phase-shifted at VAO to
achieve the desired level of 3rd-harmonic distortion of the input current wave-shape [4]. For every 1% of 3rdharmonic input distortion allowable, the small-signal gain GVEA = VVAOpk / vSENSEpk = gmv × ZOV at the twice-line
frequency should allow no more than 2% ripple over the full VVAO voltage range. In the UCC28070, VVAO can
range from 1 V at zero load power to ~4.2 V at full load power for a ΔVVAO = 3.2 V, so 2% of 3.2 V is 64-mV
peak ripple.
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NOTE
Although the maximum VVAO is clamped at 5 V, at full load VVAO may vary around an
approximate center point of 4.2 V to compensate for the effects of the quantized feedforward voltage in the multiplier stage (see Linear Multiplier and Quantized Voltage Feed
Forward for details). Therefore, 4.2 V is the proper voltage to use to represent maximum
output power when performing voltage-loop gain calculations.
The output capacitor maximum low-frequency, zero-to-peak, ripple voltage is closely approximated by:
v 0pk =
PIN(avg) ´ XCout
PIN(avg)
=
VOUT(avg)
VOUT(avg) ´ 2p ´ f2LF ´ COUT
where:
•
•
•
PIN(avg) is the total maximum input power of the interleaved-PFC preregulator
VOUT(avg) is the average output voltage
COUT is the output capacitance
VSENSEpk = vopk × kR
(28)
where
•
kR is the gain of the resistor-divider network on VSENSE
(29)
Thus, for k3rd, the percentage of allowable 3rd-harmonic distortion on the input current attributable to the VAO
ripple,
ZOV( f2LF ) =
k 3rd ´ 64 mV ´ VOUT(avg) ´ 2p ´ f2LF ´ COUT
gmv ´ k R ´ PIN(avg)
(30)
This impedance on VAO is set by a capacitor (CPV), where CPV = 1 / (2πf2LF × ZOV(f2LF)); therefore:
Cpv =
gmv ´ k R ´ PIN(avg)
k 3rd ´ 64 mV ´ VOUT(avg) ´ (2p ´ f2LF )2 ´ COUT
(31)
The voltage-loop unity-gain cross-over frequency (fVXO) may now be solved by setting the open-loop gain equal
to 1:
æ PIN(avg) ´ XCout ö
´ g ´ XCpv )´ k R = 1
Tv(fVXO ) = GBST ´ GVEA ´ k R = ç
ç DVVAO ´ VOUT(avg) ÷÷ ( mv
è
ø
g
k
P
´
´
mv
R
IN(avg)
fVXO 2 =
2
DVVAO ´ VOUT(avg) ´ (2p ) ´ Cpv ´ COUT
so,
(32)
(33)
The zero-resistor (RZV) from the zero-placement network of the compensation may now be calculated. Together
with CPV, RZV sets a pole right at fVXO to obtain 45° phase margin at the cross-over.
Rzv =
Thus,
1
2p ´ fVXO ´ Cpv
(34)
Finally, a zero is placed at or below fVXO / 6 with capacitor CZV to provide high gain at DC but with a breakpoint
far enough below fVXO so as not to significantly reduce the phase margin. Choosing fVXO / 10 allows one to
approximate the parallel combination value of CZV and CPV as CZV, and solve for CZV simply as:
Czv =
10
2p ´ fVXO ´ Rzv
» 10 ´ Cpv
(35)
By using a spreadsheet or math program, CZV, RZV, and CPV may be manipulated to observe their effects on fVXO
and phase margin and the percentage contribution to 3rd-harmonic distortion. Also, phase margin may be
checked as PIN(avg) level and system parameter tolerances vary.
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NOTE
The percent of 3rd-harmonic distortion calculated in this section represents the
contribution from the f2LF voltage ripple on COUT only. Other sources of distortion, such as
the current-sense transformer, the current synthesizer stage, even distorted VIN, and so
on, can contribute additional 3rd and higher order harmonic distortion.
7.4 Device Functional Modes
The UCC28070 operates in Average Current Mode. This eliminates the peak-to-average current error inherent in
the peak current mode control method and gives lower THD and harmonics on the current drawn from the line. It
does not require slope compensation and has better noise immunity than the peak current control method.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28070 is a switch-mode controller used in interleaved boost converters for power factor correction. The
UCC28070 requires few external components to operate as an active PFC preregulator. It operates at a fixed
frequency in continuous conduction mode. The operating switching frequency can be programmed from 30 kHz
to 300 kHz by a single resistor from the RT pin to ground. The magnitude and rate of optional frequency dithering
may also be controlled easily. The internal 5-V reference voltage provides for accurate output voltage regulation
over the typical world-wide 85-VAC to 265-VAC mains input range from zero to full output load. The reference
may also be used to set a peak current limit. Regulation is accomplished in two loops. The inner current loop
shapes the average input current to match the sinusoidal input voltage under continuous inductor current
conditions. A single multiplier output is shared between the two current amplifiers to ensure close matching of the
currents in the two phases. A Zero Power detector disables both the GDA and GDB outputs under light-load
conditions.
8.2 Typical Application
L1
VIN
D1
12–21 V
VOUT
VREF
VREF
1
CDR
DMAX 20
2
RDM
RT 19
3
VAO
SS 18
4
VSENSE
GDB 17
5
VINAC
GND 16
6
IMO
VCC 15
7
RSYNTH
GDA 14
8
CSB
VREF 13
9
CSA
CAOA 12
RDMX
RRDM
RA
RA
To CSB
R S1
RRT
T1
CSS
M1
CVCC
L2
CREF
CSB
D2
To CSA
R S2
CSA
CZV
11
M2
CZC
RIMO
CPV
RB
CAOB
COUT
RSYN
10 PKLMT
T2
RPK1
CPC
CZC
CPC
RB
RZV
RPK2
RZC
RZC
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Typical Application Diagram
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
MIN
TYP
85
MAX
UNIT
265
V
63
Hz
VAC
Input voltage
VOUT
Output voltage
fLINE
Line frequency
fSW
Switching frequency
200
kHz
POUT
Output power
300
W
η
Full load efficiency
390
47
V
90%
8.2.2 Detailed Design Procedure
8.2.2.1 Output Current Calculation
The first step is to determine the maximum load current on the output.
P
300W
Io = o =
= 0.78A
Vo
385V
(36)
8.2.2.2 Bridge Rectifier
The maximum RMS input-line current is given by Equation 37:
Po
300W
Iline _ max =
=
= 3.6Arms
hVAC _ min 98%(85V)
(37)
The peak input current is given by Equation 38:
Iin _ pk = 2 ´ Iline _ max = 2 ´ 3.6A = 5.1A
(38)
The maximum average rectified line current is given by Equation 39:
Iin _ avg _ max =
2 2
2 2
´ Iline _ max =
´ 3.6A = 3.25A
p
p
(39)
A typical bridge rectifier has a forward voltage drop VF of 0.95 V. The power loss in the rectifier bridge can be
calculated by Equation 40:
PBR _ max = 2 ´ VF ´ Iin _ avg _ max = 2 ´ 0.95V ´ 3.25A = 6.2W
(40)
The bridge rectifier must be rated to carry the full line current. The voltage rating of the bridge should be at least
600 V. The bridge rectifier also carries the full inrush current as the bulk capacitor COUT charges when line is
connected.
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8.2.2.3 PFC Inductor (L1 and L2)
The selection of the PFC inductor value may be based on a number of different considerations. Cost, core size,
EMI filter, and inductor ripple current are some of the factors that have an influence. For this design we choose
the inductor so that at the minimum input voltage the peak to peak ripple (ΔIL) has the same amplitude as the
peak of line current in each phase. The line current flows equally in the two phases so ΔII is half Iin_pk calculated
in Equation 38. The inductor is calculated by Equation 41.
V
´ D(1 - D) 385V ´ 0.7(1 - 0.7)
L 1 = OUT
=
» 160µH
5.1A
f sw ´ DI L
200kHz ´
2
where
•
•
•
VOUT is the PFC stage output voltage
fSW is the switching frequency
ΔIL is the allowed peak-to-peak ripple current.
(41)
D is the PFC stage duty cycle at 120 VIN (peak of 85 Vrms line) and is given by Equation 42:
V
D = 1 - IN
V OUT
(42)
The peak current in each boost inductor is then:
I in _ pk DI L 5.1A 5.1A
+
=
+
= 3.8A
I L _ pk =
2
2
2
4
(43)
The inductor specifications are:
• Inductance: 160 µH
• Current: 4 A
8.2.2.4 PFC MOSFETs (M1 and M2)
The main specifications for the PFC MOSFETs are:
• BVDSS, drain source breakdown voltage: ≥650 V
• RDS(on), ON-state drain source resistance: 520 mΩ at 25°C, estimate 1 Ω at 125°C
• CDSS, output capacitance: 32 pF
• tr, devise rise time: 12 ns
• tf, device fall time: 16 ns
The losses in the device are calculated by Equation 44 and Equation 45. These calculations are approximations
because the losses are dependent on parameters which are not well controlled. For example, the RDS(on) of a
MOSFET can vary by a factor of 2 from 25°C to 125°C. Therefore several iterations may be needed to choose
an optimum device for an application different than the one discussed.
Each phase carries half the load power so the conduction losses are estimated by:
PM _ cond
æ
2 ´ VIN(min)
0.5 ´ Po
16
=ç
´ 2´
ç 2´V
3p
VOUT
IN(min)
è
2
ö
æ 150W
16
2 ´ 85V
÷ ´R
ç
=
´ 2´
DS(on)
÷
ç
3p
385V
è 2 ´ 85V
ø
2
ö
÷ ´ 1.0 = 2.25W
÷
ø
(44)
The switching losses in each MOSFET are estimated by:
PM _ sw =
Iline _ max
æ
ö 1
1
3.6A
æ
ö
´ f SW çç Vo ´
´ (t r + t f ) + C os s ´ Vo 2 ÷÷ = ´ 200kHz ç 385V ´
´ (12ns + 16ns ) + 32pF ´ 385V 2 ÷ = 2.4W
2
2
2
è
ø
è
ø 2
(45)
The total losses in each MOSFET are then:
PM = PM _ cond + PM _ sw = 2.25W + 2.4W = 4.9W
(46)
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8.2.2.5 PFC Diode
Reverse recovery losses can be significant in a CCM boost converter. A Silicon Carbide Diode is chosen here
because it has no reverse recovery charge (QRR) and therefore zero reverse recovery losses.
I
0.78A
PD = Vf ´ OUT = 1.5V ´
= 580mW
(47)
2
2
8.2.2.6 PFC Output Capacitor
The value of the output capacitor is governed by the required hold-up time and the allowable ripple on the output.
The hold-up time depends on the load current and the minimum acceptable voltage at the output.
The value of the output capacitor must be large enough to provide the required hold-up time and keep the ripple
voltage at twice line frequency within acceptable limits. Normally a capacitance value of about 0.6 μF per Watt of
output power is a reasonable compromise where hold-up time is not significant. At 300 W this would indicate a
capacitance of about 200 μF.
The low frequency (at twice line frequency) rms voltage ripple on VOUT is given by Equation 48:
Io
1
1
0.78A
Vo _ ripple =
´
=
´
= 4.4Vrms
2 2 2p ´ fline ´ C o 2 2 2p ´ 50Hz ´ 200µF
(48)
The resulting low frequency current in the capacitor is:
Io _ ripple = 2p ´ flf ´ C o ´ Vo _ ripple = 4p ´ 100Hz ´ 200µF ´ 4.4V = 1.1Arms
(49)
8.2.2.7 Current Loop Feedback Configuration
(Sizing of the Current Transformer Turns Ratio and Sense Resistor (RS)
A current-sense transformer (CT) is typically used in high-power applications to sense inductor current in order to
avoid the losses inherent in the use of a current sensing resistor. For average current-mode control, the entire
inductor current waveform is required; however low-frequency CTs are obviously impracticable. Normally, two
high-frequency CTs are used, one in the switching leg to obtain the up-slope current and one in the diode leg to
obtain the down-slope current. These two current signals are summed together to form the entire inductor
current, but this is not necessary with the UCC28070.
A major advantage of the UCC28070 design is the current synthesis function, which internally recreates the
inductor current down-slope during the switching period OFF-time. This eliminates the need for the diode-leg CT
in each phase, significantly reducing space, cost and complexity. A single resistor programs the synthesizer
down slope, as previously discussed in the Current Synthesizer section.
A number of trade-offs must be made in the selection of the CT. Various internal and external factors influence
the size, cost, performance, and distortion contribution of the CT.
These factors include, but are not limited to:
• Turns-ratio (NCT)
• Magnetizing inductance (LM)
• Leakage inductance (LLK)
• Volt-microsecond product (Vμs)
• Distributed capacitance (Cd)
• Series resistance (RSER)
• External diode drop (VD)
• External current sense resistor (RS)
• External reset network
Traditionally, the turns-ratio and the current sense resistor are selected first. Some iterations may be needed to
refine the selection once the other considerations are included.
In general, 50 ≤ NCT ≤ 200 is a reasonable range from which to choose. If NCT is too low, there may be high
power loss in RS and insufficient LM. If too high, there could be excessive LLK and Cd. (A one-turn primary
winding is assumed.)
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LLK
IDS
1
NCT
LM
CSx
RSER
D
Cd
iM
Reset
Network
RS
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Current Sense Transformer Equivalent Circuit
A major contributor to distortion of the input current is the effect of magnetizing current on the CT output signal
(iRS). A higher turns-ratio results in a higher LM for a given core size. LM should be high enough that the
magnetizing current (iM) generated is a very small percentage of the total transformed current. This is an
impossible criterion to maintain over the entire current range, because iM unavoidably becomes a larger fraction
of iRS as the input current decreases toward zero. The effect of iM is to steal some of the signal current away from
RS, reducing the CSx voltage and effectively understating the actual current being sensed. At low currents, this
understatement can be significant and CAOx increases the current-loop duty-cycle in an attempt to correct the
CSx input(s) to match the IMO reference voltage. This unwanted correction results in overstated current on the
input wave shape in the regions where the CT understatement is significant, such as near the AC line zero
crossings. It can affect the entire waveform to some degree under the high line, light-load conditions.
The sense resistor RS is chosen, in conjunction with NCT, to establish the sense voltage at CSx to be about 3 V
at the center of the reflected inductor ripple current under maximum load. The goal is to maximize the average
signal within the common-mode input range VCMCAO of the CAOx current-error amplifiers, while leaving room for
the peaks of the ripple current within VCMCAO. The design condition should be at the lowest maximum input power
limit as determined in the section on the Linear Multiplier and Quantized Voltage Feed Forward. If the inductor
ripple current is so high as to cause VCSx to exceed VCMCAO, then RS or NCT or both must be adjusted to reduce
peak VCSx, which could reduce the average sense voltage center below 3 V. There is nothing wrong with this
situation; but be aware that the signal is more compressed between full- and no-load, with potentially more
distortion at light loads.
The matter of volt-second balancing is important, especially with the widely varying duty-cycles in the PFC stage.
Ideally, the CT is reset once each switching period; that is, the OFF-time Vμs product equals the ON-time Vμs
product. On-time Vμs is the time-integral of the voltage across LM generated by the series elements RSER, LLK, D,
and RS. Off-time Vμs is the time-integral of the voltage across the reset network during the OFF-time. With
passive reset, Vμs-off is unlikely to exceed Vμs-on. Sustained unbalance in the on or off Vμs products leads to
core saturation and a total loss of the current-sense signal. Loss of VCSx causes VCAOx to quickly rise to its
maximum, programming a maximum duty-cycle at any line condition. This, in turn causes the boost inductor
current to increase without control, until the system fuse or some component failure interrupts the input current.
It is vital that the CT has plenty of Vμs design-margin to accommodate various special situations where there
may be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current
limiting.
Maximum Vμs(on) can be estimated by:
Vm(on)max = t ON(max ) ´ (VRS + VD + VRSER + VLK )
where
•
•
all factors are maximized to account for worst-case transient conditions
tON(max) occurs during the lowest dither frequency, if frequency dithering is enabled
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For design margin, a CT rating of approximately 5 × Vμs(on)max or higher is suggested. The contribution of VRS
varies directly with the line current. However, VD may have a significant voltage even at near-zero current, so
substantial Vμs(on) may accrue at the zero-crossings where the duty-cycle is maximum. VRSER is the least
contributor, and often can be neglected if RSER < RS. VLK is developed by the di/dt of the sensed current, and is
not observable externally. However, its impact is considerable, given the sub-microsecond rise-time of the
current signal plus the slope of the inductor current. Fortunately, most of the built-up Vμs across LM during the
ON-time is removed during the fall-time at the end of the duty-cycle, leaving a lower net Vμs(on) to be reset
during the OFF-time. Nevertheless, the CT must, at the very minimum, be capable of sustaining the full internal
Vμs(on)max built up until the moment of turn-off within a switching period.
Vμs(off) may be generated with a resistor or Zener diode, using the iM as bias current.
CRST
D
D
RRST
RRST
ZRST
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Possible Reset Networks
To accommodate various CT circuit designs and prevent the potentially destructive result due to CT saturation,
the UCC28070’s maximum duty-cycle must be programmed such that the resulting minimum OFF-time
accomplishes the required worst-case reset. (See the PWM Frequency and Duty-Cycle Clamp section of the
data sheet for more information on sizing RDMX) Be aware that excessive Cd in the CT can interfere with effective
resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT self-resonant
frequency. A higher turns-ratio results in higher Cd [3], so a trade-off between NCTand DMAX must be made.
The selected turns-ratio also affects LM and LLK, which vary proportionally to the square of the turns. Higher LM is
good, while higher LLK is not. If the voltage across LM during the ON-time is assumed to be constant (which it is
not, but close enough to simplify) then the magnetizing current is an increasing ramp.
This upward ramping current subtracts from iRS, which affects VCSx especially heavily at the zero-crossings and
light loads, as stated earlier. With a reduced peak at VCSx, the current synthesizer starts the down-slope at a
lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these
conditions. If low input current distortion at very light loads is required, special mitigation methods may need to
be developed to accomplish that goal.
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8.2.2.8 Current Sense Offset and PWM Ramp for Improved Noise Immunity
To improve noise immunity at extremely light loads, TI recommends adding a PWM ramp with a DC offset to the
current sense signals. Electrical components RTA, RTB, ROA, ROB, CTA, CTB, DPA1, DPA2, DPB1, DPB1 CTA, and CTB
form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. Resistor ROA
and ROB add a DC offset to the CS resistors (RSA and RSB).
VCC
DPA1
ROA
DPA2
RTA
GDA
CSA
CTA
RSA
VCC
DPB1
ROB
DPB2
RTB
GDB
CTB
RSB
Copyright © 2016, Texas Instruments Incorporated
Figure 27. PWM Ramp and Offset Circuit
When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitances in the
boost stages. This inductor current rings through the CTs causing a false current sense signal. Please refer to
the following graphical representation of what the current sense signal looks like when the inductor current goes
discontinuous.
NOTE
The inductor current and RS may vary from this graphical representation depending on
how much inductor ringing is in the design when the unit goes discontinuous.
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Figure 28. False Current Sense Signal
To counter for the offset (VOFF) just requires adjusting resistors ROA and ROB to ensure that when the unit goes
discontinuous the current sense resistor is not seeing a positive current when it should be zero. Setting the offset
to 120 mV is a good starting point and may need to be adjusted based on individual design criteria.
RSA = RSB
ROA = ROB =
(51)
(VVCC - VOFF )´ RSA
VOFF
(52)
A small PWM ramp that is equal to 10% of the maximum current sense signal (VS) less the offset can then be
added by properly selecting RTA, RTB, CTA and CTB.
RTA = RTB =
CTA = CTB =
36
(VVCC - (VS ´ 0.1 - VOFF ) + VDA 2 )´ RSA
VS ´ 0.1 - VOFF
1
RTA ´ fS ´ 3
(53)
(54)
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8.2.3 Application Curves
Ch1: Inductor current (IA)
M1: Inductor Current (IB)
Ch3: GDB
Ch2: GDA
Figure 29. Typical Inductor Currents
Ch1: Inductor current (IA)
M4: Input current (IA + IB)
Ch1: Inductor current (IA)
M4: Input current (IA + IB)
M1: Inductor current (IB)
Figure 30. Typical Inductor and Input Ripple Currents
Ch1: Input current
Figure 31. Typical Inductor and Input Ripple Currents
120 VAC
PF = 0.98
Figure 32. Typical Input Current
9 Power Supply Recommendations
The UCC28070 should be operated from a VCC rail which is within the limits given in Recommended Operating
Conditions. To avoid the possibility that the device might stop switching, VCC must not be allowed to fall into the
UVLO range.
In order to minimize power dissipation in the device, VCC should not be unnecessarily high. Keeping VCC at 12 V
is a good compromise between these competing constraints.
The gate drive outputs from the UCC28070 can deliver large current pulses into their loads. This indicates the
need for a low ESR decoupling capacitor to be connected as directly as possible between the VCC and GND
pins. TI recommends ceramic capacitors with a stable dielectric characteristic over temperature, such as X7R.
Avoid capacitors which have a large drop in capacitance with applied DC voltage bias and use a part that has a
low voltage co-efficient of capacitance. TI recommends a decoupling capacitance of 10 μF, X7R, with at least a
25-V rating. A capacitor of at least 0.1 μF must be placed as close as possible between the VCC and GND pins.
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10 Layout
10.1 Layout Guidelines
Interleaved PFC techniques dramatically reduce input and output ripple current caused by the PFC boost
inductor, which allows the circuit to use smaller and less expensive filters. To maximize the benefits of
interleaving, the output filter capacitor should be located after the two phases allowing the current of each phase
to be combined together before entering the boost capacitor. Similar to other power management devices, when
laying out the PCB it is important to use star grounding techniques and to keep filter and high frequency bypass
capacitors as close to device pins and ground as possible. To minimize the possibility of interference caused by
magnetic coupling from the boost inductor, the device should be located at least 1 inch away from the boost
inductor. TI recommends the device not be placed underneath magnetic elements.
10.2 Layout Example
To VOUT
CBOUT
RBOUT
CZV
RRDM
CCDR
Reference Designators are those used in the Simplified Application Diagram
RZV
CPV
UCC28070
RDMX
1 CDR
DMAX 20
2 RDM
RT 19
3 VAO
SS 18
To VIN
CBIN
RBIN
RAOUT
RRT
CSS
To Gate B
4 VSENSE
GDB 17
5 VINAC
GND 16
6 IMO
VCC 15
7 RSYNTH
GDA 14
RIMO
RSYN
To Current Sense B
RCSB
CCSB
8 CSB
VREF 13
9 CSA
CAOA 12
10 PKLMT
CAOB 11
RCSA
To VCC Supply
To Gate A
CPCA
CCSA
To Current Sense A
CVCC
RAIN
RPK2
CZCA
RZCA
CZCB
RZCB
CREF
CPCB
RPK1
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Layout Diagram
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
1. O’Loughlin, Michael, An Interleaving PFC Pre-Regulator for High-Power Converters, Texas Instruments, Inc.
2006 Unitrode Power Supply Seminar, Topic 5
2. Erickson, Robert W., Fundamentals of Power Electronics, 1st ed., pp. 604-608 Norwell, MA: Kluwer
Academic Publishers, 1997
3. Creel, Kirby Measuring Transformer Distributed Capacitance, White Paper, Datatronic Distribution, Inc.
website: http://www.datatronics.com/pdf/distributed_capacitance_paper.pdf
4. L. H. Dixon, Optimizing the Design of a High Power Factor Switching Preregulator, Unitrode Power Supply
Design Seminar Manual SEM700, 1990. SLUP093
5. L. H. Dixon, High Power Factor Preregulator for Off-Line Power Supplies, Unitrode Power Supply Design
Seminar Manual SEM600, 1988. SLUP087
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28070DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
UCC28070
UCC28070DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
UCC28070
UCC28070PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
28070
UCC28070PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
28070
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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