UCC28089D

UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 PRIMARY-SIDE PUSH-PULL OSCILLATOR WITH DEAD-TIME CONTROL FEATURES D Push-Pull Oscillator With Programmable Deadtime High-Current Totem-Pole Dual Output Stage Drives Push-Pull Configuration with 1-A Sink and 0.5-A Source Capability Can be Used in Push-Pull, Half-Bridge, or Full-Bridge Topologies Oscillator Synchronization Output Low Start-Up Current of 130 μA and 1.4-mA Typical Run Current Over-Current Shutdown Digitally Controlled Over-Current/Retry Feature Undervoltage Lockout With Hysteresis D D D D D D D APPLICATIONS D High Efficiency Cascaded Converters D Inverters D Electronic Ballasts D Uninterruptable Power Supplies (UPS) D AC or DC Links DESCRIPTION The UCC28089 is a versatile BiCMOS controller for dc-to-dc or off-line fixed-frequency switching power supplies. The UCC28089 has dual alternating output stages in dual-alternating push-pull configuration. Both outputs switch at half the oscillator frequency using a toggle flip-flop and duty cycle is limited to less than 50%. TYPICAL APPLICATION VO = 1.2 V + + VIN = 48 V -- -RA UCC28089 1 SYNC VDD 8 RB CT 2 DIS OUTA 7 3 CT OUTB 6 4 CS GND 5 BIAS UCC2540 G1 18 2 REF VDD 16 PGND 15 4 SYNCIN G2 14 UDG-04112 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 DESCRIPTION (CONTINUED) The UCC28089 is optimized for use as the primary-side companion controller for a cascaded converter that has secondary-side control. The device incorporates dead-time programming. The synchronization output also provides dead-time information. The retry and soft-start duration scales with the oscillator clock frequency for high performance fault recovery. The UCC28089 also provides primary side under-voltage protection (UVLO), and over-current protection. Both the soft start and retry after fault durations scale with oscillator frequency for high performance. The turn-on/off UVLO thresholds are 10.5 V/8.0 V. ORDERING INFORMATION † TEMPERATURE RANGE TA = TJ PACKAGED DEVICES{ --40°C to 105°C UCC28089D SOIC--8 (D) D (SOIC--8) package is available taped and reeled. Add R suffix to device type (e.g. UCC28089DR) to order quantities of 2,500 devices per reel (for D). CONNECTION DIAGRAM D PACKAGE (SOIC--8) (TOP VIEW) SYNC DIS CT CS 2 1 8 2 7 3 6 4 5 VDD OUTA OUTB GND www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)†} PARAMETER Supply voltage (IDD < 10 mA) SYMBOL RATING UNITS VDD 15 V mA Supply current OUTA/OUTB sink current (peak) OUTA/OUTB source current (peak) IDD 20 IOUT(sink) 1.0 IOUT(source) --0.5 A SYNC sink current (peak) 50 SYNC source current (peak) --50 Analog inputs (DIS, CT, CS) --0.3 to VDD + 0.3, not to exceed 5 Power dissipation at TA = 25°C (D package) 650 Power dissipation at TA = 25°C (DRB package) TBD Junction operating temperature TJ --55 to 150 Storage temperature Tstg --65 to 150 Lead temperature (soldering, 10 sec.) Tsol +300 mA V mW oC † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute--maximum--rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages. RECOMMENDED OPERATION CONDITIONS Parameter Symbol MIN VDD 8.5 Supply voltage (IDD < 10 mA) SYNC sink current (peak) SYNC source current (peak) Analog inputs (DIS, CT, CS) TYP MAX UNITS 14 V 0 10 25 --25 --10 0 mA 0 4 V Timing capacitor range CT 100 100,000 pF Timing charge resistor range RA 32 750 Discharge resistor range RB 0 250 Timing charge current ICHG(RA+RB) 10 Switching Frequency fSW Junction temperature TJ www.ti.com --40 kΩ 300 μA 1000 kHz 105 °C 3 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS: TA = --40°C to 105°C for UCC28089, VDD = 9 V (see Note 1), 1 μF capacitor from VDD to GND, RA = 110 kΩ, RB = 182 Ω, CT = 220 pF, TA = TJ, (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNITS Overall Section Startup current VDD < UVLO start threshold (see Note 2) 130 260 μA Operating supply current CS = 0 V, (see Note 1, Note 2) 1.4 2.0 mA Undervoltage Lockout Start threshold 9.5 10.5 11.5 Minimum operating voltage after start See Note 1 7.4 8.0 8.4 Hysteresis 2.1 2.5 2.9 180 200 220 kHz 0.650 0.725 0.800 V 45 100 ns 100 110 V Oscillator Oscillator frequency 2 x OUTx frequency, Measured at output(s) Current Sense Current Shutdown threshold Resetting current limit CS to output delay CS from 0 mV to 900 mV Output Dead Time Measured at OUTA or OUTB 90 Over temperature 80 125 Minimum duty cycle CS = 0.9 V VOL (OUTA or OUTB) IOUT = 75 mA 0.5 1 VOH (OUTA or OUTB) IOUT = --35 mA, (VDD – VOUT) 1.0 1.3 Output resistance high TA = 25°C IOUT = --1 mA (see Note 4) 80 90 Output resistance low 0 70 TA = full range IOUT = --1 mA (see Note 4) 40 80 135 TA = 25°C IOUT = 1 mA (see Note 4) 6.5 7.5 8.5 4 7.5 14 TA = full range IOUT = 1 mA (see Note 4) tr, Rise Time CLOAD = 1 nF 28 50 tf, Fall Time CLOAD = 1 nF 13 30 ns % V Ω ns SYNC SYNC duration Measured at SYNC pin 75 95 115 tr, delay Rising SYNC until falling OUTA or OUTB 0 8.5 30 tf, delay Falling SYNC until rising OUTA or OUTB 0 14 50 SYNC VOH ISYNC = --5 mA (VDD – VSYNC) 0.3 1 SYNC VOL ISYNC = 5 mA 0.3 1 tr, Rise Time CLOAD = 100 pF 15 30 tf, Fall Time CLOAD = 100 pF 15 30 ns V ns Soft Start & Fault OUTA/OUTB start delay time Cycles as measured at CT pin 57 59 62 OUTA/OUTB soft start duration First output stage cycle to first full output stage cycle, CS ≤ 0.6 V 4 5 7 NOTES: 1. 2. 3. 4. 4 cycles Set VDD above the start threshold before setting at 9V. Does not include current of the external oscillator network. Ensured by design. Not 100% tested in production. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resisstance is the RDS(ON) of the MOSFET transistor when the voltage of the driver output is less than the saturation voltage of the bipolar transistor. www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 FUNCTIONAL BLOCK DIAGRAM UCC28089 VDD SYNC 1 OSCILLATOR DIS 2 UVLO 8 VDD VDD/5 S Q VDD/19.6 R Q CT 3 CK VDD = 10.5/8.0 V VDD SOFT--START & FAULT OUTPUT LOGIC 56 STEP START DELAY GO OVER CURRENT COMP R 7 OUTA VDD/5 GO REF SS LATCH 7 STEP SOFT-- + START RAMP 0.2V S Q SS COMP CS 4 6 OUTB R Q Q _ T Q 0.725 V 5 GND UDG-04101 PIN # NAME I/O FUNCTION Active when OUTA and OUTB are active, logic LO at all other times such as during under-voltage lock-out and over-current shutdown. When active, SYNC is logic HI (VDD) during the discharge time of the oscillator and logic LO (GND) at all other times. The pulse occur during the dead time. 1 SYNC O 2 DIS I 3 CT I 4 CS I 5 GND -- Ground pin. Analog and digital signals reference this pin and output drivers return current through this pin 6 7 8 OUTB OUTA VDD O O I Driver output, capable of sinking 1 A and sourcing 0.5 A. OUTB signal alternates with OUTA. Driver output, capable of sinking 1 A and sourcing 0.5 A. OUTA signal alternates with OUTB. Power input connection for this device. Separate oscillator timing capacitor discharge pin that allows the dead time to be externally programmed. Oscillator timing capacitor connection. Current sense pin. An over current shutdown event is triggered when the voltage of this pin rises above 0.75 V. www.ti.com 5 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION UCC28089 is an alternating dual-driver output oscillator with over-current and under-voltage fault protection. This feature set is ideal as a start-up controller for isolated power systems where the majority of control functions are performed on the secondary side. This device is especially useful for dc link for topologies such as the cascaded buck converter [1], ac link inverter topologies [2], and inexpensive modified square wave inverters. The UCC28089 has a brief 5 to 7 cycle leading-edge modulated soft-start cycle so that it will not interfere with secondary-side controlled soft start. Both systems with off-line self bias and auxiliary bias supplies are more fault tolerant with the UCC28089 because it consistently responds to a fault with a delay of at least 56 oscillator cycles before retry. Detailed Functional Description VDD: Power input connection for this device. Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the programmed oscillator frequency. During fault response, the current drops to a lower level because the oscillator is disabled. In order to avoid noise problems, position a 1-μF ceramic bypass capacitor, connected from VDD to GND, as close to the chip as possible. The ceramic bypass capacitor is in addition to any energy storage capacitance that would be used to hold up the VDD voltage during start-up transients. GND: Ground pin. Analog signals reference this pin and output drivers return current through this pin. For best results, use this pin as a local ground point in a star ground configuration. OUTA and OUTB: Output drivers capable of sinking 1 A and sourcing 0.5 A. The output pulse alternates between OUTA and OUTB. In addition, a T latch forces the output pulses to alternate in order to reduce flux build up in a transformer during low duty ratio operation. Each output is capable of driving the gate of a power MOSFET. CT and DIS: Oscillator timing capacitor pin and timing capacitor discharge pin. The UCC28089 oscillator tracks VDD and GND internally in order to minimize oscillator frequency changes due to variations in the voltage of VDD. Figure 1 shows the oscillator block diagram. UCC28089 VDD VDD RA 2 DIS OSCILLATOR 15.7Rx RB 2.90Rx 3 CT SD Q CK R Q CT Rx VROK V(CT) VDD/5 VDD/19.6 CK Figure 1. Block Diagram for Oscillator 6 www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION The recommended oscillator frequency range is up to 1 MHz. In order to avoid noise issues, RA and RB should be small enough for the oscillator to have at least 10 μA of current. There are two sets of oscillator programming equations that model the oscillator over its wide programming range. Measure the charge and the discharge times at the SYNC pin in order to avoid affecting the oscillator with probe impedances or output driver delays. The approximate first order equations in the table are adequate for switching frequencies below 50 kHz and/or discharge times that are greater than 1 μs. The specific requirements for using the first order equations versus the second order equations are related to the timing capacitor size and the discharge resistor. Keep in mind that the 1st order equations and 2nd order equations are merely approximations that are typically within +/--20% of the actual operating point. The frequency, charge and discharge times are relatively insensitive to temperature but larger values of CT and RB exhibit the least sensitivity to temperature. Incidentally, the second order equations apply for the operating conditions that are in the Electrical Characteristics table. The oscillator frequency is set according to the following equations: Condition 1ST ORDER EQUATIONS 2ND ORDER EQUATIONS RA > 300 kΩ AND CT > 300 pF 32 kΩ < RA < 300 kΩ OR 100 pF < CT < 300 pF         TCHARGE 0.169 R + R C A B T 0.175 R + R C + 40 pF + 20 ns A B T TDISCHARGE 1.36 R C B T (1.37) R + 44 C + 14 pF + 20 ns B T fOSC 5.9 RA + 8.0 RBCT T CHARGE 1 +T DISCHARGE Where RA and RB are in Ohms; CT is in Farads; fOSC is in Hz; tCHARGE and tDISCHARGE are in seconds. The oscillator is optimized for a CT timing capacitor range from 100 pF to 1000 nF and RB more than 100 Ω. If the shortest discharge time possible is desired, it is permissible to short DIS to CT for all recommended CT values (100 pF to 0.100 μF). SYNC: This SYNC pin produces an output pulse from 0 to VDD that can be used to synchronize a secondary side-buck controller to the free running isolating power stage. The proper timing of this signal enables zero voltage switching on the primary side MOSFETs. The clean signal also solves a problem of getting a synchronization signal from the secondary side of the transformer, which can have leakage inductance voltage spikes that may cause false triggering. The SYNC pulse width is the oscillator discharge time, which is approximately equal to the dead time. Pulse frequency is the oscillator frequency. During fault conditions, the SYNC pulses are terminated and the SYNC output is held low for at least 56 oscillator cycles. During soft start, SYNC precedes the first output pulse by at least one oscillator cycle. CS: Connect the current sense device to this pin. A voltage threshold of 0.725 V triggers a shutdown sequence. An over-current fault triggers an immediate shutdown. After the fault clears, a total of 64 oscillator cycles are required for an entire soft start sequence to occur. First, the outputs and SYNC are kept OFF for at least 56 oscillator cycles. Next, after one or two SYNC pulses, the soft start progressively increases the output duty ratio over the next five to seven oscillator cycles. www.ti.com 7 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION Using the UCC28089 as the Primary-Side start-up Controller in a Cascaded Push-Pull Buck Two-Stage Converter The cascaded push-pull topology is ideal for converting from moderate bus voltages, such as 48-V telecom buses, to sub 2-V output voltages. The general topology is shown in Figure 2 using the UCC28089 as the primary-side start-up controller and the UCC2540 as the secondary-side regulator [3]. + + VO 1.2 V VIN = 48 V -10 V RA UCC28089 1 SYNC VDD 8 RB CT 2 DIS OUTA 7 3 CT OUTB 6 4 CS GND 5 CR1 CR2 L.REG IN OUT -- COM UCC2540 1 ISET/SDSWS 20 2 REF BST 19 3 G2C G1 18 4 SYNCIN SW 17 5 RAMP VDD 16 6 GND PGND 15 7 VEA-- G2 14 8 CEA-- VDRV 13 9 COMP G2S 12 10 TR SS 11 UDG-04100 Figure 2. Cascaded Push-Pull Buck Two-Stage Converter 8 www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION Program the oscillator frequency of the UCC28089 to equal the desired switching frequency of the output post regulator. The secondary-side controller may also need corresponding switching frequency programming, such as RAMP and G2C capacitor values for the UCC2540. Program the dead time to be approximately 1/4 of the resonant period of the equivalent parasitic L--C circuit that is established by the primary leakage inductance of the transformer and the total drain-source capacitance of the primary-side power MOSFET transistors (COSS + stray capacitances). Remember that COSS predictably varies over input line voltage. If the variation is too great and/or 1/4 the resonant period is less than 100 ns, connect additional capacitance (CR1 and CR2 in Figure 2) between the drain and source of the primary transistors, which stabilizes the capacitance and raise the total capacitance value. If the secondary-side controller is compatible with pulse edges, the pulse edge transformer circuit in Figure 3 can provide an isolated pulse edge signal on the secondary side using a transformer core that is 6-mm diameter or less. The recommended transformer (COEV #MGBBT--0001101) is compatible with all switching frequencies and it is smaller than many opto-isolators. Primary Ground UCC28089 SYNC Secondary Ground C1 T1 680 pF 1:1 1 R CB R1 422 634 R BE 115 L1 GND 5 UCC2540 15uH 2 REF 4 SYNCIN Q CL 2N3904 GND1 Figure 3. Isolation and clamping the SYNC signal for Cascaded Buck Converters Notice that the peak-pulse voltage is proportional to the UCC28089 bias voltage. The circuit in Figure 3 is well suited to the full VDD bias voltage range of the UCC28089 bias voltage because it has a clamp circuit. The clamp circuit in Figure 3 (RCB, RBE and QCL) is a VBE clamp rather than a Zener diode. A VBE clamp is used here because it has much lower capacitance than typical Zener diodes so that the clamp does not affect the narrow 50-ns pulse width. The clamp may be replaced by a single resistor in applications, as in Figure 2, where the VDD bias voltage of the UCC28089 is regulated within a +/--5% window. www.ti.com 9 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION Synchronization of Multiple UCC28089 Controllers to an External Signal In systems where multiple UCC28089 parts need to be synchronized to a common clock, a 3.3-V logic-level signal can be directly applied to the CT pin (the SYNC pin on UCC28089 only provides output sync signals). As shown in Figure 4, the externally supplied sync pulse width determines the frequency and the dead time between OUT A and OUT B. In this configuration, the discharge pin DIS should be grounded since it is not used. The external sync signal should exceed the oscillator trip level of VDD/5 when high, and pull CT below VDD/20 when low. VDD U1 UCC28089 OUT A NC 1 SYNC 2 DIS 3 CT 4 CS OUT B VDD 8 OUTA 7 OUTB 6 1 μF GND 5 Ext. Sync Applied to CT 3.3V Ext. Sync UDG-04113 External Sync pulse width defines output dead time Figure 4. Synchronizing the UCC28089 to an External Signal 10 www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION Using the UCC28089 as a Modified Square Wave Inverter Remote or dc-only power systems often require a limited amount of 60-Hz ac line power to supply small appliances. Compatible loads include universal motors, incandescent lamps, and other electronic devices with switched mode power supplies to convert the 110-VAC to lower dc voltages. Many of these devices do not require a perfect sinusoidal line voltage, and acceptable performance can be obtained with a modified square wave voltage. Using the circuit in Figure 5, the UCC28089 can provide the appropriate waveform along with primary side over-current protection. Components RA, RB, and CT are selected to program the desired modified square waveform with the appropriate dead time. + F1 12 V Bias VIN = 145 VDC 1N4003 -- 20 Ω RA 221 kΩ 47 μF 4.7 μF 200 Ω 200 Ω 4.7 μF 50 Ω 50 Ω MPSA42 MPSA42 UCC28089 NC SYNC 1 VDD 8 200 Ω 200 Ω RB 27 kΩ CT 0.1 μF 2 DIS OUTA 7 3 CT OUTB 6 4 CS GND 5 6800 pF 6800 pF 145 V 0V RS VO 110 VAC(rms) NOTE: CS signal should be selected to limit peak inrush current to acceptable levels. --145 V 16.7 ms UDG-04105 Figure 5. Modified Square Wave Inverter The high-side gate drives of the inverter in Figure 5 are suitable for low frequency applications with relatively constant duty ratio. The NPN transistors and the charge pump diodes on the high-side gate drives must be rated for high voltage (at least 145 V + VDD). The gates are protected from excessive negative voltage by the diodes shown from gate to source. www.ti.com 11 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 APPLICATION INFORMATION If desired, the 60-Hz modified square wave inverter frequency could be programmed using an external sync signal that might originate from a separate oscillator or digital controller. The following diagram in Figure 6 shows a 50% duty cycle square wave fed into the CT pin, with a frequency of 120 Hz, and the resulting OUTA/OUTB wave shapes. 16.7 ms VDD U1 UCC28089 OUT A NC OUT B 1 SYNC 2 DIS 3 CT 4 CS VDD 8 OUTA 7 1 μF OUTB 6 GND 5 Ext. Sync 3.3 V External Sync example with 50% duty cycle Ext. Sync 8.33 ms Figure 6. External Synchronization Example with 50% Duty Cycle Square Wave RELATED PRODUCTS DEVICE UCC2540 12 DESCRIPTION High-Efficiency Secondary-Side Synchronous-Buck PWM Controller www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs TEMPERATURE 220 RA = 221 kΩ RB = 3.32 Ω CT = 220 pF 108 fs -- Oscillator Frequency-- kHz fs -- Oscillator Frequency-- kHz 110 RA = 110 kΩ RB = 182 Ω CT = 220 pF 215 OSCILLATOR FREQUENCY vs TEMPERATURE 210 205 200 195 190 185 106 104 102 100 98 96 94 92 180 90 --50 --25 0 25 50 75 100 --50 --25 Tj -- Temperature -- °C 0 25 100 125 Figure 8 OSCILLATOR FREQUENCY SHIFT vs TEMPERATURE OSCILLATOR FREQUENCY SHIFT vs SUPPLY VOLTAGE 2.0% RA = 110 kΩ RB = 182 Ω CT = 220 pF VDD = 9 V RA = 110 kΩ RB = 182 Ω CT = 220 pF 1.5% f -- Frequency, Normalized -- % fs -- Normalized to 25°C-- kHz 1.5% 75 Tj -- Temperature -- °C Figure 7 2.0% 50 1.0% RA = 221 kΩ RB = 3.32 Ω CT = 220 pF 0.5% 0.0% --0.5% --1.0% 1.0% RA = 221 kΩ RB = 3.32 Ω CT = 220 pF 0.5% 0.0% --1.5% --2.0% --50 --0.5% --25 0 25 50 75 100 125 8 9 10 11 12 13 14 15 VDD -- Supply Voltage -- V Tj -- Temperature -- °C Figure 9 Figure 10 www.ti.com 13 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 TYPICAL CHARACTERISTICS OSCILATOR FREQUENCY vs RA x CT 1M 10 μ Tdischarge -- Discharge Time-- s RA = 76.8 kΩ RB = 0 Ω VDD = 10 V fOSC -- Oscilator Frequensy -- Hz DISCHARGE TIME vs CT 100 K 10 K 1K RA = 76.8 kΩ RB = 0 Ω VDD = 10 V 1μ 100 n 100 10 n 1μ 10 μ 1M 100 μ 10 M 1n 100 P 10 n RA x CT -- s Figure 12 SYNC PULSE WIDTH vs TEMPERATURE RA = 110 kΩ RB = 182 Ω CT = 220 pF TO -- Output Dead Time -- ns 120 SYNC -- Pulse Width-- ns 105 100 95 90 85 105 100 95 90 75 80 25 50 75 100 125 Tj -- Temperature -- °C --50 --25 0 25 50 Tj -- Temperature -- °C Figure 13 14 110 85 0 RA = 110 kΩ RB = 182 Ω CT = 220 pF 115 80 --25 OUTPUT DEAD TIME vs TEMPERATURE 125 115 --50 1μ CT-- Farad Figure 11 110 100 n Figure 14 www.ti.com 75 100 125 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 PROPAGATION DELAY (SYNC RISE TO OUTPUT FALL) vs TEMPERATURE 12 25 Tprop(f) -- Propagation Delay-- ns Tprop(f) -- Propagation Delay-- ns 11 PROPAGATION DELAY (SYNC FALL TO OUTPUT RISE) vs TEMPERATURE 10 9 8 7 20 15 10 6 5 5 --50 --25 0 25 50 75 100 125 --50 --25 Tj -- Temperature -- °C 25 50 75 100 125 Tj -- Temperature -- °C Figure 15 Figure 16 OSCILLATOR DISCHARGE ON-RESISTANCE vs TEMPERATURE CURRENT SENSE THRESHOLD vs TEMPERATURE 810 50 vDIS = 1.5 V VCT = 3.0 V CS -- Current Sense Threshold-- mV RDS(on) -- Oscillator Discharge FET On Resistance-- Ω 0 45 40 35 30 790 770 750 730 710 690 670 650 25 --50 --25 0 25 50 75 100 125 Tj -- Temperature -- °C --50 --25 0 25 50 75 100 125 Tj -- Temperature -- °C Figure 17 Figure 18 www.ti.com 15 UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs OSCILLATOR FREQUENCY (NO LOAD) SUPPLY CURRENT vs OSCILLATOR FREQUENCY (1 nF LOADS) 4.0 18 16 3.5 IDD -- Supply Current -- mA IDD -- Supply Current -- mA VDD = 14 V 3.0 2.5 VDD = 12 V 2.0 VDD = 9 V 14 VDD = 14 V 12 10 8 VDD = 12 V 6 VDD = 9 V 4 1.5 2 1.0 0 0 200 K 400 K 600 K 800 K 1M 0 fOSC -- Oscillator Frequency -- kHz 400 K 600 K TYPICAL OVERALL START--UP WAVEFORMS OUTA OUTB SYNC SYNC CT CT t -- Time -- 1 ms/div. t -- Time -- 1 ms/div. Figure 21 16 1M Figure 20 TYPICAL SOFT START WAVEFORMS OUTB 800 K fOSC -- Oscillator Frequency -- kHz Figure 19 OUTA 200 K Figure 22 www.ti.com UCC28089 SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006 REFERENCES 1. Power Supply Seminar SEM--1300 Topic 1: Unique Cascaded Power Converter Topology for High Current Low Output Voltage Applications, by L. Balogh, C. Bridge and B. Andreycak, Texas Instruments Literature No. SLUP133 2. Low Cost Inverter Suitable for Medium-Power Fuel Cell Sources, by P.T. Krein and R Balog, IEEE Power Electronics Specialists Conference Proceedings, 2002, vol. 1, pp. 321--326. 3. Datasheet, UCC2540 High-Efficiency Secondary-Side Synchronous-Buck PWM Controller, Texas Instruments Literature No. SLUS539 www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) UCC28089D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 28089 Samples UCC28089DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 28089 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of