SLUS579 − OCTOBER, 2003
FEATURES
D Controls Boost Preregulator to Near-Unity
D
D
D
D
D
D
D
D
D
D
D
DESCRIPTION
The UCC2819A/UCC3819A provides all the
functions necessary for active power factor
corrected preregulators. The controller achieves
near unity power factor by shaping the ac-input
line current waveform to correspond to that of the
ac-input line voltage. Average current mode
control maintains stable, low distortion sinusoidal
line current.
Power Factor
World Wide Line Operation
Over-Voltage Protection
Accurate Power Limiting
Average Current Mode Control
Improved Noise Immunity
Improved Feed-Forward Line Regulation
Leading Edge Modulation
150-µA Typical Start-Up Current
Low-Power BiCMOS Operation
10.8-V to 17-V Operation
Programmable Output Voltage (Tracking
Boost Topology)
Designed in Texas Instrument’s BiCMOS process,
the UCC3819A offers new features such as lower
start-up current, lower power dissipation,
overvoltage protection, a shunt UVLO detect
circuitry and a leading-edge modulation technique
to reduce ripple current in the bulk capacitor.
The UCC3819A allows the output voltage to be
programmed by bringing out the error amplifier
noninverting input.
BLOCK DIAGRAM
VCC
15
OVP/EN
10
7.5 V
REFERENCE
1.9 V
VAOUT
7
VSENSE
11
−
VFF
ENABLE
0.33 V
VOLTAGE
ERROR AMP
8
X
16
DRVOUT
1
GND
2
PKLMT
10.2 V/9.7 V
ZERO POWER
VCC
−
+
X
÷ MULT
X
13
VREF
UVLO
+
+
VAI
−
9
CURRENT
AMP
8.0 V
OVP
−
−
−
+
2
+
PWM
S
+
PWM
LATCH
R
R
OSC
CLK
MIRROR
2:1
Q
CLK
IAC
MOUT
6
OSCILLATOR
−
+
5
4
3
12
14
CAI
CAOUT
RT
CT
UDG-03124
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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$!. '' %$$!)
Copyright 2003, Texas Instruments Incorporated
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1
SLUS579 − OCTOBER, 2003
DESCRIPTION (CONTINUED)
The UCC3819A is directly pin for pin compatible with the UCC3819. Only the output stage of UCC3819A has
been modified to allow use of a smaller external gate drive resistor values. For some power supply designs
where an adequately high enough gate drive resistor can not be used, the UCC3819A offers a more robust
output stage at the cost of increasing the internal gate resistances. The gate drive of the UCC3819A remains
strong at ±1.2 A of peak current capability.
Available in the 16-pin D, N, and PW packages.
PIN CONNECTION DIAGRAM
D, N, AND PW PACKAGES
(TOP VIEW)
GND
PKLMT
CAOUT
CAI
MOUT
IAC
VAOUT
VFF
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
DRVOUT
VCC
CT
VAI
RT
VSENSE
OVP/EN
VREF
AVAILABLE OPTIONS TABLE
PACKAGE DEVICES
TA = TJ
SOIC (D) PACKAGE(1)
PDIP (N) PACKAGE
TSSOP (PW) PACKAGE(1)
0°C to 70°C
UCC3819AD
UCC3819AN
UCC3819APW
−40°C to 85°C
UCC2819AD
UCC2819AN
UCC2819APW
NOTES: (1) The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g. UCC3819ADR) to order quantities
of 2,500 devices per reel (D package) and 2,000 devices per reel (for PW package). Bulk quantities are 40 units (D package) and
90 units (PW package) per tube.
THERMAL RESISTANCE TABLE
PACKAGE
θjc(°C/W)
SOIC−16 (D)
22
θja(°C/W)
40 to 70 (1)
PDIP−16 (N)
12
14 (2)
25 to 50 (1)
123 to 147 (2)
TSSOP−16 (PW)
NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board with one ounce copper
where noted. When resistance range is given, lower values are for 5 inch2 aluminum PC board. Test PWB
was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace
widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.
(2) Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal copper ground plane,
higher value is for 1x1-inch. ground plane. All model data assumes only one trace for each non-fused
lead.
2
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SLUS579 − OCTOBER, 2003
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)†
UCCx81xA
UNIT
Supply voltage VCC
18
V
Gate drive current, continuous
0.2
Gate drive current
1.2
Input voltage, CAI, MOUT, SS
A
8
Input voltage, PKLMT
5
Input voltage, VSENSE, OVP/EN, VAI
10
Input current, RT, IAC, PKLMT
10
Maximum negative voltage, DRVOUT, PKLMT, MOUT
Power dissipation
V
−0.5
V
1
W
Junction temperature, TJ
−55 to 150
Storage temperature, Tstg
−65 to 150
Lead temperature, Tsol (soldering, 10 seconds)
mA
°C
C
300
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C for the UCC3819A, −40°C to 85°C for the UCC2819A, VCC = 12 V, RT = 22 kΩ, CT = 270 pF,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
150
300
µA
2
4
6
mA
VCC turnon threshold
9.7
10.2
10.8
VCC turnoff threshold
9.4
9.7
UVLO hysteresis
0.3
0.5
Supply Current
Supply current, off
VCC = (VCC turnon threshold −0.3 V)
Supply current, on
VCC = 12 V,
No load on DRVOUT
UVLO
V
Voltage Amplifier
VIO
VAOUT = 2.75 V,
VCM = 3.75 V
VAI bias current
VAOUT = 2.75 V,
VCM = 3.75 V
50
200
VSENSE bias current
CMRR
VSENSE = VREF,
VAOUT = 2.5 V
50
200
VCM = 1 V to 7.5 V
50
70
Open loop gain
VAOUT = 2 V to 5 V
50
90
High-level output voltage
IL = −150 µA
IL = 150 µA
5.3
5.5
5.6
V
0
50
150
mV
Low-level output voltage
−15
15
mV
nA
dB
NOTES: 1. Ensured by design, Not production tested.
2. Reference variation for VCC < 10.8 V is shown in Figure 2.
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SLUS579 − OCTOBER, 2003
ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C for the UCC3819A, −40°C to 85°C for the UCC2819A, VCC = 12 V, RT = 22 kΩ, CT = 270 pF,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VREF
+0.48
VREF
+0.50
VREF
+0.52
V
Hysteresis
300
500
600
Enable threshold
1.7
1.9
2.1
Enable hysteresis
0.1
0.2
0.3
Over Voltage Protection and Enable
Over voltage reference
mV
V
Current Amplifier
Input offset voltage
Input bias current
Input offset current
Open loop gain
Common-mode rejection ratio
High-level output voltage
Low-level output voltage
Gain bandwidth product
VCM = 0 V,
VCM = 0 V,
VCAOUT = 3 V
VCAOUT = 3 V
VCM = 0 V,
VCM = 0 V,
VCAOUT = 3 V
VCAOUT = 2 V to 5 V
90
VCM = 0 V to 1.5 V,
IL = −120 µA
VCAOUT = 3 V
60
80
5.6
6.5
6.8
0.1
0.2
0.5
IL = 1 mA
See Note 1
−3.5
0
2.5
−50
−100
25
100
mV
nA
dB
2.5
V
MHz
Voltage Reference
Input voltage, (UCC3819A)
Input voltage, (UCC2819A)
Load regulation
TA = 0°C to 70°C
TA = −40°C to 85°C
Line regulation
IREF = 1 mA to 2 mA
VCC = 10.8 V to 15 V,
Short-circuit current
VREF = 0 V
See Note 2
7.387
7.5
7.613
7.369
7.5
7.631
0
10
0
10
V
mV
−20
−25
−50
mA
85
100
115
kHz
Oscillator
Initial accuracy
Voltage stability
TA = 25°C
VCC = 10.8 V to 15 V
Total variation
Line, temp,
See Note 1
−1%
1%
80
120
kHz
Ramp peak voltage
4.5
5
5.5
Ramp amplitude voltage
(peak to peak)
3.5
4
4.5
15
mV
350
500
ns
V
Peak Current Limit
PKLMT reference voltage
−15
PKLMT propagation delay
150
NOTES: (1) Ensured by design, Not production tested.
(2) Reference variation for VCC < 10.8 V is shown in Figure 2.
4
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SLUS579 − OCTOBER, 2003
ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C for the UCC3819A, −40°C to 85°C for the UCC2819A, VCC = 12 V, RT = 22 kΩ, CT = 270 pF,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
−6
−20
UNITS
Multiplier
IMOUT, high line, low power output
current, (0°C to 85°C)
IAC = 500 µA,
VFF = 4.7 V,
VAOUT = 1.25 V
0
IMOUT, high line, low power output
current, (−40°C to 85°C)
IAC = 500 µA,
VFF = 4.7 V,
VAOUT = 1.25 V
0
IMOUT, high line, high power output
current
IAC = 500 µA,
VFF = 4.7 V,
VAOUT = 5 V
−70
−90
−105
IMOUT, low line, low power output
current
IAC = 150 µA,
VFF = 1.4 V,
VAOUT = 1.25 V
−10
−19
−50
IMOUT, low line, high power output
current
IAC = 150 µA,
VFF = 1.4 V,
VAOUT = 5 V
−268
−300
−346
IMOUT, IAC limited
Gain constant (K)
IAC = 150 µA,
IAC = 300 µA,
VFF = 1.3 V,
VFF = 3 V,
VAOUT = 5 V
−250
−300
−400
0.5
1
1.5
VFF = 1.4 V,
VFF = 4.7 V,
VAOUT = 0.25 V
0
−2
IMOUT, zero current
IAC = 150 µA,
IAC = 500 µA,
VAOUT = 0.25 V
0
−2
IMOUT, zero current, (0°C to 85°C)
IMOUT, zero current, (−40°C to 85°C)
IAC = 500 µA,
IAC = 500 µA,
VFF = 4.7 V,
VFF = 4.7 V,
VAOUT = 0.5 V
0
−3
Power limit (IMOUT x VFF)
IAC = 150 µA,
VFF = 1.4 V,
VAOUT = 5 V
VAOUT = 2.5 V
VAOUT = 0.5 V
−23
µA
1/V
µA
A
0
−3.5
−375
−420
−485
µW
−140
−150
−160
µA
9
12
4
10
25
50
10
50
95%
100%
Feed-Forward
VFF output current
IAC = 300 µA
Gate Driver
Pullup resistance
Pulldown resistance
IO = –100 mA to −200 mA
IO = 100 mA
Output rise time
CL = 1 nF,
RL = 10 Ω,
Output fall time
CL = 1 nF,
RL = 10 Ω,
Maximum duty cycle
Minimum controlled duty cycle
VDRVOUT = 0.7 V to 9 V
VDRVOUT = 9 V to 0.7 V
93%
At 100 kHz
Ω
ns
2%
Zero Power
Zero power comparator threshold
Measured on VAOUT
0.20
0.33
0.50
V
NOTES: (1) Ensured by design, Not production tested.
(2) Reference variation for VCC < 10.8 V is shown in Figure 2.
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5
SLUS579 − OCTOBER, 2003
PIN ASSIGNMENTS
TERMINAL
NAME
I/O
NO.
DESCRIPTION
CAI
4
I
Current amplifier noninverting input
CAOUT
3
O
Current amplifier output
CT
14
I
Oscillator timing capacitor
DRVOUT
16
O
Gate drive
GND
1
−
Ground
IAC
6
I
Current proportional to input voltage
MOUT
5
I/O
OVP/EN
10
I
Over-voltage/enable
PKLMT
2
I
PFC peak current limit
RT
12
I
Oscillator charging current
VAI
13
I
Voltage amplifier non-inverting input
VAOUT
7
O
Voltage amplifier output
VCC
15
I
Positive supply voltage
VFF
8
I
Feed-forward voltage
VSENSE
11
I
Voltage amplifier inverting input
VREF
9
O
Voltage reference output
Multiplier output and current amplifier inverting input
Pin Descriptions
CAI: Place a resistor between this pin and the GND side of current-sense resistor. This input and the inverting
input (MOUT) remain functional down to and below GND.
CAOUT: This is the output of a wide bandwidth operational amplifier that senses line current and commands
the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed
between CAOUT and MOUT.
CT: A capacitor from CT to GND sets the PWM oscillator frequency according to:
f[
ǒRT0.6CTǓ
The lead from the oscillator timing capacitor to GND should be as short and direct as possible.
DRVOUT: The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. To avoid the
excessive overshoot of the DRVOUT while driving a capacitive load, a series gate current-limiting/damping
resistor is recommended to prevent interaction between the gate impedance and the output driver. The value
of the series gate resistor is based on the pulldown resistance (Rpulldown which is 4-Ω typical), the maximum
VCC voltage (VCC), and the required maximum gate drive current (Imax). Using the equation below, a series
gate resistance of resistance 11 Ω would be required for a maximum VCC voltage of 18 V and for 1.2 A of
maximum sink current. The source current will be limited to approximately 900 mA (based on the Rpullup of 9-Ω
typical).
R GATE +
ǒ
VCC * I MAX
Ǔ
R pulldown
I MAX
GND: All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with
a 0.1-µF or larger ceramic capacitor.
6
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SLUS579 − OCTOBER, 2003
Pin Descriptions (continued)
IAC: This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is
tailored for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum
IIAC is 500 µA.
MOUT: The output of the analog multiplier and the inverting input of the current amplifier are connected together
at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured
as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge
modulation operation. The multiplier output current is limited to ǒ2 I IACǓ. The multiplier output current is given
by the equation:
I MOUT +
I IAC
(V VAOUT * 1)
V VFF
2
K
where K + 1 is the multiplier gain constant.
V
OVP/EN: A window comparator input that disables the output driver if the boost output voltage is a programmed
level above the nominal or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ).
PKLMT: The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense
resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the
peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.
RT: A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and
100 kΩ is recommended. Nominal voltage on this pin is 3 V.
VAI: This input can be tied to the VREF or any other voltage reference (≤7.5 V) to set the boost regulator output
voltage.
VAOUT: This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output
is internally limited to approximately 5.5 V to prevent overshoot.
VCC: Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC
directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To
prevent inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds the upper
under-voltage lockout voltage threshold and remains above the lower threshold.
VFF: The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single pole external filter.
At low line, the VFF roll should be 14 V.
VSENSE: This is normally connected to a compensation network and to the boost converter output through a
divider network.
VREF: VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA
to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when
VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best
stability. Please refer to Figures 8 and 9 for VREF line and load regulation characteristics.
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SLUS579 − OCTOBER, 2003
APPLICATION INFORMATION
The UCC3819A is based on the UCC3818 PFC preregulator. For a more detailed application information for
this part, please refer to the UCC3818 datasheet product folder.
The main difference between the UCC3818 and the UCC3819A is that the non-inverting input of the voltage
error amplifier is made available to the user through an external pin (VAI) in the UCC3819A. The SS pin and
function were eliminated to accommodate this change.
The benefit of VAI pin is that it can be used to dynamically change the PFC output voltage based on the line
voltage (RMS) level or other conditions. Figure 1 shows one suggested implementation of the tracking boost
PFC converter as this approach is sometimes referred to. The VAI pin is tied to the VFF pin and hence output
voltage scales up with the line voltage. The benefit of this approach is that at lower line voltages the output
voltage is lower and that leads to smaller boost inductor value, lower MOSFET conduction losses and reduced
component stresses. In order for this feature to work, the downstream converter has to operate over a wider
input range.
R21
R13
IAC
VO
D1
AC2
F1
+
D2
C14
VLINE
C13
Q1
D3
VOUT
AC1
C12
R14
−
R17
UCC3819A
R9
R12
R10
1
GND
DRVOUT 16
D4
2
PKLIMIT
3
CAOUT
4
CAI
5
MOUT
CT
14
6
IAC
VAI
13
RT
12
D5
R11
VREF
C9
R8
VCC 15
C2
C1
C4
C8
VFF
C7
D6
R7
VCC (FROM BIAS SUPPLY)
C3
C15
R1
VSENSE 11
7
VAOUT
8
VFF
R3
R2
R19
C6
R20
VO
R4
OVP/EN 10
R6
C5
VREF
R5
9
VREF
UDG−01008
Figure 1. Suggested Implementation of UCC3819A in a Tracking Boost PFC Preregulator
8
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SLUS579 − OCTOBER, 2003
APPLICATION INFORMATION
REFERENCE VOLTAGE
vs
REFERENCE CURRENT
REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
7.510
VREF − Reference Voltage − V
VREF − Reference Voltage − V
7.60
7.55
7.50
7.505
7.500
7.45
7.495
7.40
7.490
9
10
11
12
13
0
14
5
Figure 2
15
20
25
Figure 3
MULTIPLIER OUTPUT CURRENT
vs
VOLTAGE ERROR AMPLIFIER OUTPUT
MULTIPLIER GAIN
vs
VOLTAGE ERROR AMPLIFIER OUTPUT
1.5
350
300
1.3
IAC = 150 µ A
IAC = 150 µ A
250
1.1
200
IAC = 300 µ A
150
100
50
Multiplier Gain − K
IMOUT - Multiplier Output Current − µA
10
IVREF − Reference Current − mA
VCC − Supply Voltage − V
0.9
IAC = 300 µ A
IAC = 500 µ A
0.7
IAC = 500 µ A
0.5
0
0.0
1.0
2.0
3.0
4.0
5.0
VAOUT − Voltage Error Amplifier Output − V
1.0
2.0
3.0
4.0
5.0
VAOUT − Voltage Error Amplifier Output − V
Figure 5
Figure 4
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9
SLUS579 − OCTOBER, 2003
APPLICATION INFORMATION
MULTIPLIER CONSTANT POWER PERFORMANCE
(VFF × IMOUT) − µW
500
400
VAOUT = 5 V
300
VAOUT = 4 V
200
VAOUT = 3 V
100
VAOUT = 2 V
0
0.0
1.0
2.0
3.0
4.0
VFF − Feedforward Voltage − V
5.0
Figure 6
References and Resources:
Application Note: Differences Between UCC3817A/18A/19A and UCC3817/18/19, Texas Instruments
Literature Number SLUA294
User’s Guide: UCC3817 BiCMOS Power Factor Preregulator Evaluation Board, Texas Instruments Literature
Number SLUU077
Application Note: Synchronizing a PFC Controller from a Down Stream Controller Gate Drive, Texas
Instruments Literature Number SLUA245
Seminar topic: High Power Factor Switching Preregulator Design Optimization, L.H. Dixon, SEM−700,1990.
Seminar topic: High Power Factor Preregulator for Off−line Supplie”, L.H. Dixon, SEM−600, 1988.
Related Products
DEVICE
UCC3817/A,18/A
DESCRIPTION
BiCMOS PFC controller
UC3854
PFC controller
UC3854A/B
Improved PFC controller
UC3855A/B
High performance soft switching PFC controller
UCC38050/1
Transition mode PFC controller
UCC28510/11/12/13
Advanced PFC+PWM combo controller
UCC28514/15/16/17
Advanced PFC+PWM combo controller
NOTES: (1). Critical conduction mode
(2). Average current mode
10
www.ti.com
CONTROL METHOD
ACM(2)
TYPICAL POWER LEVEL
ACM(2)
ACM(2)
200 W to 2 kW+
ACM(2)
CRM(1)
400 W to 2 kW+
ACM(2)
ACM(2)
75 W to 1kW+
75 W to 2 kW+
200 W to 2 kW+
50 W to 400 W
75 W to 1kW+
PACKAGE OPTION ADDENDUM
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13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
UCC2819AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
UCC2819AD
Samples
UCC2819ADR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
UCC2819AD
Samples
UCC2819APW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2819A
Samples
UCC2819APWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
2819A
Samples
UCC3819AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
UCC3819AD
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of