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UCC28220, UCC28221
SLUS544G – SEPTEMBER 2003 – REVISED APRIL 2017
UCC2822x Interleaved Dual PWM Controller With Programmable Max Duty Cycle
1 Features
3 Description
•
The UCC28220 and UCC28221 are a family of
BiCMOS interleaved dual channel PWM controllers.
Peak current mode control is used to ensure current
sharing between the two channels. A precise
maximum duty cycle clamp can be set to any value
between 60% and 90% duty cycle per channel.
1
•
•
•
•
•
•
•
•
•
2-MHz High-Frequency Oscillator With 1-MHz
Operation Per Channel
Matched Internal Slope Compensation Circuits
Programmable Maximum Duty Cycle Clamp 60%
to 90% Per Channel
Peak Current Mode Control With Cycle-by-Cycle
Current Limit
Current Sense Discharge Transistor for Improved
Noise Immunity
Accurate Line Undervoltage and Overvoltage
Sense With Programmable Hysteresis
Opto-Coupler Interface
110-V Internal Start-Up JFET (UCC28221)
Operates From 12-V Supply (UCC28220)
Programmable Soft Start
The UCC28220 has an UVLO turnon threshold of
10 V for use in 12-V supplies while UCC28221 has a
turnon threshold of 13 V for systems needing wider
UVLO hysteresis. Both have 8-V turnoff thresholds.
Additional features include a programmable internal
slope compensation with a special circuit which is
used to ensure exactly the same slope is added to
each channel and a high-voltage 110-V internal JFET
for easier start-up for the wider hysteresis UCC28221
version.
The UCC28220 is available in both 16-pin SOIC and
low-profile TSSOP packages. The UCC28221 also
comes in 16-pin SOIC package and a slightly larger
20-pin TSSOP package to allow for high-voltage pin
spacing to meet UL1950 creepage clearance safety
requirements.
2 Applications
•
•
•
•
High Output Current (50-A to 100-A) Converters
Maximum Power Density Designs
High-Efficiency 48-V Input With Low Output Ripple
Converters
High-Power Offline, Telecom, and Datacom
Power Supplies
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC28220,
UCC28221
SOIC (16)
9.00 mm × 3.90 mm
TSSOP (16)
5.00 mm × 4.40 mm
UCC28221
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VIN
(+48V)
CS1
1 LINEOV
VIN 16
2 LINE
HYS
LINEUV 15
3 VDD
REF 14
4 CS1
OUT1 13
5 SLOPE
OUT2 12
Bias
VOUT
1/2 UCC27324
6 CS2
GND 11
7 SS
CHG 10
CS2
REF
8 CTRL DISCHG 9
1/2 UCC27324
E/A
Copyright © 2016, Texas Instruments Incorporated
Pin 16 is a no connect (NC) on UCC28220 which does not include the JFET option.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28220, UCC28221
SLUS544G – SEPTEMBER 2003 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision F (September 2016) to Revision G
Page
•
Deleted Control Loop Compensation section. ..................................................................................................................... 19
•
Deleted Current Loop section............................................................................................................................................... 19
•
Deleted Voltage Loop (TV(s)) section..................................................................................................................................... 19
Changes from Revision E (March 2009) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 3
•
Added Thermal Information table ........................................................................................................................................... 5
2
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Copyright © 2003–2017, Texas Instruments Incorporated
Product Folder Links: UCC28220 UCC28221
UCC28220, UCC28221
www.ti.com
SLUS544G – SEPTEMBER 2003 – REVISED APRIL 2017
5 Device Comparison Table
DEVICE
DESCRIPTION
PACKAGE OPTION
UCC2732x
Dual 4-A High Speed Low Side MOSFET Drivers
SOIC (8), PowerPAD MSOP (8), PDIP (8)
UCC2742x
Dual 4-A High Speed Low Side MOSFET Drivers with Enable
SOIC (8), PowerPAD MSOP (8), PDIP (8)
TPS281x
Dual 2.4-A High Speed Low Side MOSFET Drivers
SOIC (8), TSSOP (8), PDIP (8)
UC371x
Dual 2.4-A High Speed Low Side MOSFET Drivers
SOIC (8), PowerSOIC (14), PDIP (8)
6 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
PW Package
20-Pin TSSOP
Top View
VIN (for UCC28221)
NC (for UCC28220)
LINEOV
1
16
8
LINEHYS
2
15
7 LINEUV
VDD
3
14
6 REF
CS1
4
13
5 OUT1
SLOPE
5
2
12
7 OUT2
CS2
SS
CTRL
3
6
NC
1
20
8 VIN
LINEOV
2
19
7 NC
LINEHYS
3
18
6 LINEUV
VDD
4
17
5 REF
CS1
5
2
16
7 OUT1
SLOPE
3
6
15
6 OUT2
CS2
7
4
5 GND
14
SS
8
4
5
13
9 CHG
CTRL
9
4
5 DISCHG
12
11
6 GND
7
4
5 CHG
10
5
9
8
4
DISCHG
NC 10
4
5 NC
11
Pin Functions
PIN
NAME
CHG
CS1
SOIC,
TSSOP (16)
10
4
TSSOP (20)
13
5
I/O
DESCRIPTION
I
Sets oscillator charge current: A resistor from this pin to GND sets up the
charging current of the internal CT capacitor used in the oscillator. This resistor,
in conjunction with the resistor on the DISCHG pin is used to set up the
operating frequency and maximum duty cycle. Under normal operation the dc
voltage on this pin is 2.5 V.
I
Channel 1 current sense input: These 2 pins are the current sense inputs to the
device. The signals are internally level shifted by 0.5 V before the signal gets to
the PWM comparator. Internally the slope compensation ramp is added to this
signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin gets
pulled to ground each time its respective output goes low (that is: OUT1 and
OUT2).
CS2
6
7
I
Channel 2 current sense input: These 2 pins are the current sense inputs to the
device. The signals are internally level shifted by 0.5 V before the signal gets to
the PWM comparator. Internally the slope compensation ramp is added to this
signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin gets
pulled to ground each time its respective output goes low (that is: OUT1 and
OUT2).
CTRL
8
9
I
Feedback control input:
Copyright © 2003–2017, Texas Instruments Incorporated
Product Folder Links: UCC28220 UCC28221
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Pin Functions (continued)
PIN
SOIC,
TSSOP (16)
NAME
TSSOP (20)
I/O
DESCRIPTION
Sets oscillator discharge current: A resistor from this pin to GND sets up the
discharge current of the internal CT capacitor used in the oscillator. This
resistor, in conjunction with the resistor on the CHG pin is used to set up the
operating frequency and maximum duty cycle. Under normal operation the dc
voltage on this pin is 2.5 V.
DISCHG
9
12
I
GND
11
14
—
LINEHYS
2
3
I
Sets line comparator hysteresis: This pin is controlled by both the LINEOV and
LINEUV pins. It is used to control the hysteresis values for both the over and
under voltage line detectors.
LINEOV
1
2
I
Input for line over voltage comparator: This pin is connected to a comparator
and used to monitor the line voltage for an over voltage condition. The typical
threshold is 1.26 V.
LINEUV
15
18
I
Input for line under voltage comparator: This pin is connected to a comparator
and used to monitor the line voltage for an under voltage condition. The typical
threshold is 1.26 V.
N/C
16
1, 10, 11, 19
—
No connection
O
PWM output from channel 1: These output buffers are intended to interface with
high current MOSFET drivers. The output drive capability is approximately 33
mA and has an output impedance of 100 Ω. The outputs swing between GND
and REF.
O
PWM output from channel 2: These output buffers are intended to interface with
high current MOSFET drivers. The output drive capability is approximately 33
mA and has an output impedance of 100 Ω. The outputs swing between GND
and REF.
O
Reference voltage output: REF is a 3.3-V output used primarily as a source for
the output buffers and other internal circuits. It is protected from accidental
shorts to ground. For improved noise immunity, TI recommends the reference
pin be bypassed with a minimum of 0.1 µF of capacitance to GND.
I
Sets slope compensation: This pin sets up a current used for the slope
compensation ramp. A resistor to ground sets up a current, which is internally
divided by 25 and then applied to an internal 10-pF capacitor. Under normal
operation th dc voltage on this pin is 2.5 V.
I
Soft-start input: A capacitor to ground sets up the soft-start time for the open
loop soft-start function. The source and sink current from this pin is equal to
3/7th of the oscillator charge current set by the resistor on the CHG pin. The
soft start capacitor is held low during UVLO and during a Line OV or UV
condition. Once an OV or UV fault occurs, the soft-start capacitor is discharged
by a current equal to its charging current. The capacitor does NOT quickly
discharge during faults. In this way, the controller has the ability to recover
quickly from very short line transients. This pin can also be used as an
Enable/Disable function.
I
Device supply input: This is used to supply power to the device, monitoring this
pin is a the UVLO circuit. This is used to insure glitch-free startup operation.
Until VDD reaches its UVLO threshold, it remains in a low power mode,
drawing approximately 150 µA of current and forcing pins, SS, CS1, CS2,
OUT1, and OUT2 to logic 0 states. If the VDD falls below 8 V after reaching
turnon, it goes back into this low power state. In the case of the UCC28221, the
UVLO threshold is 13 V. It is 10 V for the UCC28220. Both versions have a
turnoff threshold of 8 V.
I
High voltage start-up input: This pin has an internal high voltage JFET used for
startup. The drain is connected to VIN, while its’ source is connected to VDD.
During startup, this JFET delivers 12 mA typically with a minimum of 4 mA to
VDD, which in turn, charges up the VDD bypass capacitor. When VDD gets to
13 V, the JFET is turned off.
OUT1
OUT2
REF
SLOPE
SS
VDD
VIN
4
13
12
14
5
7
3
—
16
15
17
6
8
4
20
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Device ground
Copyright © 2003–2017, Texas Instruments Incorporated
Product Folder Links: UCC28220 UCC28221
UCC28220, UCC28221
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SLUS544G – SEPTEMBER 2003 – REVISED APRIL 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
High-voltage start-up input, VIN
MAX
UNIT
110
V
Supply voltage, VDD
15
V
Output current (OUT1, OUT2) dc, IOUT(dc)
±10
mA
OUT1/ OUT2 capacitive load
200
pF
REF output current, IREF
Current sense inputs, CS1, CS2
Analog inputs (CHG, DISCHG, SLOPE, REF, CNTRL)
Analog inputs (SS, LINEOV, LINEUV, LINEHYS)
Power dissipation at TA = 25°C
10
mA
–1
2
V
–0.3
3.6
V
7
V
–0.3
PW package
400
D package
650
mW
Junction operating temperature, TJ
–55
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
High-voltage start-up input
36
76
UNIT
V
VDD
Supply voltage
8.4
14.5
V
7.4 Thermal Information
UCC28220, UCC28221
THERMAL METRIC (1)
UCC28221
D (SOIC)
PW (TSSOP)
PW (TSSOP)
16 PINS
16 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
73
100.9
92.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.6
28.8
27.6
°C/W
RθJB
Junction-to-board thermal resistance
30.6
46.6
43.7
°C/W
ψJT
Junction-to-top characterization parameter
5.7
1.4
1.4
°C/W
ψJB
Junction-to-board characterization parameter
30.3
46
43.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2003–2017, Texas Instruments Incorporated
Product Folder Links: UCC28220 UCC28221
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7.5 Electrical Characteristics
VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = –40°C to 105°C,
and TA = TJ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
Operating VDD
8.4
14.5
V
Quiescent current
SS = 0 V, no switching, FOSC = 1 MHz
1.5
3
4
mA
Operating current
Outputs switching, FOSC = 1 MHz
1.6
3.5
6
mA
200
µA
UCC28220
9.5
10
10.5
UCC28221
12.3
13
13.7
START-UP
Startup current
UVLO start threshold
UCC28220, VDD < (UVLO – 0.8)
UVLO stop threshold
UVLO hysteresis
JFET ON threshold
High voltage JFET current
JFET leakage
7.6
8
8.4
UCC28220
1.8
2
2.2
UCC28221
4.8
5
5.2
SS = 0, outputs not switching, VDD decreasing
9.5
10
10.5
SS = 2 V, Cntrl = 2 V, output switching, VDD
decreasing; same threshold as UVLO stop
7.6
8
8.4
VIN = 36 V to 76 V, VDD = 0 V
16
48
100
VIN = 36 V to 76 V, VDD = 10 V
4
16
40
VIN = 36 V to 76 V, VDD < UVLO
4
12
40
VIN = 36 V to 76 V, VDD = 14 V
100
V
V
V
V
mA
µA
REFERENCE
Output voltage
8 V < VDD < 14 V, ILOAD = 0 mA to –10 mA
Output current
Outputs not switching, CNTRL = 0 V
Output short-circuit current
VREF = 0 V
3.15
3.3
3.45
10
VREF UVLO
V
mA
–40
–20
–10
mA
2.55
3
3.25
V
–70
–100
–130
µA
SOFT START
SS charge current
RCHG = 10.2 kΩ, SS = 0 V
SS discharge current
RCHG = 10.2 kΩ, SS = 2 V
70
100
130
µA
SS initial voltage
LINEOV = 2 V, LINEUV = 0 V
0.5
1
1.5
V
SS voltage at 0% dc
Point at which output starts switching
0.5
1.2
1.8
V
75%
90%
100%
3
3.5
4
SS voltage ratio
SS max voltage
LINEOV = 0 V, LINEUV = 2 V
V
OSCILLATOR AND PWM
Output frequency
RCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ
450
500
550
kHz
Oscillator frequency
RCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ
900
1000
1100
kHz
Output maximum duty cycle
RCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ,
measured at OUT1 and OUT2
73%
75%
77%
CHG voltage
2
2.5
3
V
DSCHG voltage
2
2.5
3
V
140
200
260
0%
10%
SLOPE COMPENSATION
Slope
RSLOPE = 75 kΩ, RCH = 66 kΩ,
RDISCHG = 44 kΩ, Csx = 0 V to 0.5 V
Channel matching
RSLOPE = 75 kΩ, Csx = 0 V
mV/us
CURRENT SENSE
CS1, CS2 bias current
CS1 = 0, CS2 = 0
Prop delay CSx to OUTx
CSx input 0 V to 1.5 V step
CS1, CS2 sink current
CSx = 2 V
6
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–500
2.3
0
500
40
85
nA
ns
4.5
7
mA
Copyright © 2003–2017, Texas Instruments Incorporated
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SLUS544G – SEPTEMBER 2003 – REVISED APRIL 2017
Electrical Characteristics (continued)
VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = –40°C to 105°C,
and TA = TJ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CNTRL
Resistor ratio (1)
0.6
Ctrl input current
CTRL = 0 V and 3.3 V
Ctrl voltage at 0% dc
CSx = 0 V, point at which output starts switching
(checks resistor ratio)
–100
0
100
nA
0.5
1.2
1.8
V
OUTPUT (OUT1, OUT2)
Low level
IOUT = 10 mA
0.4
1
V
High level
IOUT = −10 mA, VREF – VOUT
0.4
1
V
Rise time
CLOAD = 50 pF
10
20
ns
Fall time
CLOAD = 50 pF
10
20
ns
LINE SENSE
LINEOV threshold
LINEUV threshold
TA = 25°C
TA = –40°C to 105°C
TA = 25°C
TA = –40°C to 105°C
1.24
1.26
1.28
1.235
1.26
1.285
1.24
1.26
1.28
1.235
1.26
1.285
V
V
LINEHYST pullup voltage
LINEOV = 2 V, LINEUV = 2 V
3.1
3.25
3.4
V
LINEHYST off leakage
LINEOV = 0 V, LINEUV = 2 V
–500
0
500
nA
LINEHYS pullup resistance
I = –20 µA
100
500
Ω
LINEHYS pulldown resistance
I = 20 µA
100
500
Ω
LINEOV, LINEUV bias I
LINEOV = 1.25 V, LINEUV = 1.25 V
500
nA
(1)
–500
Ensured by design. Not 100% tested in production.
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7.6 Typical Characteristics
4.0
13.5
3.5
11.5
UCC28220 UVLO on threshold and UCC28221
JFET on threshold (when not switching)
10.5
9.5
UCC28220 and UCC28221 UVLO off threshold and
UCC28221 JFET on threshold (when switching)
8.5
UCC28221 EXCLUDES JFET CURRENT
3.0
2.5
2.0
UCC28221
12.5
UCC28220
IDD − Quiescent Current − mA
VUVLO − UVLO Thresholds− V
UCC28221 UVLO on threshold
1.5
1.0
0.5
7.5
0.0
−50
−25
0
25
50
75
100
125
0
2
4
Tj − Temperature − °C
Figure 1. UVLO Thresholds vs Temperature
8
10
12
14
16
Figure 2. Quiescent Current vs Supply Voltage
30
3.45
VIN = 36 V
20
3.40
UCC28221
VREF − ReferenceVoltage − V
IDD − Supply Current − mA
6
VDD − Supply Voltage − V
10
0
−10
−20
−30
3.35
3.30
No Load
3.25
Load
3.20
−40
JFET source current
3.15
−50
0
2
4
6
8
10
12
14
−50
16
−25
VDD − Supply Voltage − V
0
25
Figure 3. Supply Current vs Supply Voltage
100
125
Figure 4. Reference Voltage vs Temperature
225
SLOPE − Slope Compensation − mV per µs
1.265
LINEOV
1.260
Vth − Trip Threshold − V
75
230
1.270
1.255
1.250
LINEUV
1.245
1.240
1.235
RSLOPE = 75 kΩ
220
215
210
205
CS1 = 0 V
200
195
190
CS1 = 0.5 V
185
180
175
170
1.230
−50
−25
0
25
50
75
100
125
−50
−25
Figure 5. LINEOV and LINEUV Thresholds vs Temperature
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0.0
25
50
75
100
125
Tj − Temperature − °C
Tj − Temperature − °C
8
50
Tj − Temperature − °C
Figure 6. Slope Compensation vs Temperature
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Typical Characteristics (continued)
10
8
6
4
106
Mismatch − %
RSLOPE − Slope Programming Resistor − Ω
107
105
0
RSLOPE = 75 kΩ
CS0 = 0 V
CS1 = 0 V
−2
−4
−6
−8
104
−10
10
100
SLOPE − Slope Compensation − mV per µs
−50
1000
−25
0.0
25
50
75
100
125
Tj − Temperature − °C
Figure 7. Programming Resistor vs Slope Compensation
Figure 8. Channel1 and Channel2 Slope Matching
vs Temperature
20
19
18
17
1.0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0.8
0.9
VO -Output Voltage − V
Tr and Tf − Rise and Fall Time − ns
2
Fall Time
Rise Time
IOUT = 10 mA
0.7
VREF − VOUT (VOH)
0.6
0.5
0.4
VOL
0.3
0.2
0.1
0.0
−50
−25
0
25
50
75
100
125
−50
−25
Tj − Temperature − °C
0
25
50
75
Tj − Temperature − °C
100
125
space
CL = 50 pF
Figure 10. VOH and VOL vs Temperature
Figure 9. Rise and Fall Time vs Temperature
−70
130
120
−80
ISSdis − Charge Current − µA
ISSCH − Charge Current − µA
RCHG = 10.2 kΩ
−90
−100
−110
−120
110
100
90
80
−130
70
−50
−25
0
25
50
75
100
125
−50
−25
Tj − Temperature − °C
0
25
50
75
100
125
Tj − Temperature − °C
Figure 11. Soft-Start Charge Current vs Temperature
Figure 12. Soft-Start Discharge Current vs Temperature
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Typical Characteristics (continued)
550
1M
540
RCHRG = RDISRG
DMAX = 75%
100K
fS - Oscillator Frequency − kHz
RCHRG RDISRG − Resistance − Ω
RCHRG = RDISRG = 10.2 kΩ
530
10K
1K
520
510
500
490
480
470
460
450
10K
100K
1M
10M
−50
−25
fS - Switching Frequency − Hz
0
25
Figure 13. Programming Resistors vs Switching Frequency
75
100
125
Figure 14. Oscillator Frequency vs Temperature
100
77
90
RCHRG = RDISRG = 10.2 kΩ
105°C
80
CSx to OUTx delay − ns
76
DC − Duty Cycle − %
50
Tj − Temperature − °C
75
70
60
25°C
50
−40°C
40
30
74
20
10
0
73
−50
−25
0
25
50
75
100
125
0
0.2
Tj − Temperature − °C
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0.6
0.8
1.0
1.2
1.4
1.6
1.8
CSx − Peak Voltage − V
Figure 15. Programmable Max Duty Cycle vs Temperature
10
0.4
Figure 16. CSx to OUTx Delay vs CSx Peak Voltage
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8 Detailed Description
8.1 Overview
The UCC2822x device is comprised of several housekeeping blocks as well as two slope compensated PWM
channels that are interleaved. The circuit is intended to run from an external VDD supply voltage between 8 V
and 14 V; however, the UCC28221 has the addition of a high-voltage start-up JFET with control circuitry which
can be used for system start-up. Other functions contained in the device are supply UVLO, 3.3-V reference,
accurate line OV and UV functions, a high-speed programmable oscillator for both frequency and duty cycle,
programmable slope compensation, and programmable soft-start functions.
The UCC2822x is a primary side controller for a two-channel interleaved power converter. The device is
compatible with forward or flyback converters as long as a duty cycle clamp between 60% and 90% is required.
The active clamp forward and flyback converters as well as the RCD and resonant reset forward converters are
therefore compatible with this device. To ensure the two channels share the total converter output current,
current mode control with internal slope compensation is used. Slope compensation is user programmable
through a dedicated pin and can be set over a 50:1 range, ensuring good small-signal stability over a wide range
of applications.
8.2 Functional Block Diagram
RUN
REFERENCE
REF 14
UVLO/ JFET
CONTROL
16
VIN
(N/C on
UCC28220)
3
VDD
13
OUT1
11
GND
12
OUT2
2
CHG 10
T
OSC
DISCHG 9
CLK1
Q
FF
CLK2
Q
+
CLK1
CS1 4
+
S Q
LATCH
R
0.5 V
VREF
Q
RUN
SLOPE
COMPENSATION
0.5 V
CLK2
+
CS2 6
+
S Q
LATCH
R
VREF
Q
RUN
SLOPE
5
CTRL
8
+
+
−
20 kΩ
30 kΩ
1 pF
LINE OV/UV
1
LINEOV
2
LINEHYS
15
LINEUV
Soft−Start
SS 7
RUN
Copyright © 2016, Texas Instruments Incorporated
Pinout for 16 pin option shown. See the 20-pin connection to UCC28221-PW in Pin Configuration and Functions.
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8.3 Feature Description
8.3.1 VDD
Because the driver output impedance is high, the energy storage requirement on the VDD capacitor is low. For
improved noise immunity, TI recommends that the VDD pin is bypassed with a minimum of 0.1-µF capacitance to
GND. In most typical applications, the bias voltage for the MOSFET drivers is also used as the VDD supply
voltage for the chip. It is beneficial to add a low valued resistor between the bulk storage capacitor of the driver
and the VDD capacitor for the UCC2822x. By adding a resistor in series with the bias supply with the bias
supply, any noise that is present on the bias supply is filtered out before getting to the VDD pin of the controller.
8.3.2 Reference
For improved noise immunity, TI recommends that the reference pin, REF, is bypassed with a minimum of 0.1-µF
capacitance to GND.
8.3.3 Oscillator Operation and Maximum Duty Cycle Setpoint
The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator is
programmable over a 200-kHz to 2-MHz frequency range with 20% to 80% maximum duty cycle range. Both the
dead time and the frequency of the oscillator are divided by 2 to generate the PWM clock and off-time
information for each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum duty
cycle at each output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output.
The design equations for the oscillator and maximum duty cycle setpoint are given in Equation 1 through
Equation 4.
FOSC = 2 ´ FOUT
(1)
DMAX(osc) = 1 - 2 ´ (1 - DMAX(out) )
RCHG = K OSC ´
(2)
DMAX(osc)
FOSC
RDISCHG = K OSC ´
(3)
(1 - DMAX(osc) )
FOSC
where
•
•
•
•
•
•
•
KOSC = 2.04 × 1010 (Ω/s)
FOUT = Switching frequency at the outputs of the chip (Hz)
DMAX(out) = Maximum duty cycle limit at the outputs of the chip
DMAX(osc) = Maximum duty cycle of the oscillator for the desired maximum duty cycle at the outputs
FOSC = Oscillator frequency for desired output frequency (Hz)
RCHG = External oscillator resistor which sets the charge current (Ω)
RDISCHG = External oscillator resistor which sets the discarge current (Ω)
(4)
8.3.4 Soft Start
A current is forced out of the SS pin, equal to 3/7 of the current set by RCHG, to provide a controlled ramp
voltage. The current set by the RCHG resistor is equal to 2.5 V divided by RCHG. This ramp voltage overrides the
commanded duty cycle on the CTRL pin, allowing a controlled start-up. Assuming the UCC288221 is biased on
the primary side, the soft start must be quite quick to allow the secondary bias to be generated and the
secondary side control can then take over. Once the soft-start time interval is complete, a closed-loop soft-start
on the secondary side can be executed, such as Equation 5.
3
2.5
ISS = ´
7 RCHG
where
•
12
ISS = current which is sourced out of the SS pin during the soft-start time (A)
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Feature Description (continued)
8.3.5 Current Sense
The current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation ramps
added to them before being compared to the control voltage at the input of the PMW comparators. The amplitude
of the current sense signal at full load must be selected such that it is very close to the maximum control voltage
to limit the peak output current during short-circuit operation.
8.3.6 Output Drivers
The UCC2822x is intended to interface with the UCC2732x family of MOSFET drivers. As such, the output drive
capability is low, effectively 100 Ω, and the driver output swing between GND and REF.
8.4 Device Functional Modes
8.4.1 Line Overvoltage and Undervoltage
Three pins are provided to turn off the output drivers and reset the soft-start capacitor when the converter input
voltage is outside a prescribed range. The undervoltage setpoint and undervoltage hysteresis are accurately set
through external resistors. The overvoltage set point is also accurately set through a resistor ratio, but the
hysteresis is fixed by the same resistor that set the undervoltage hysteresis.
Figure 17 and Figure 18 show the detailed functional diagram and operation of the undervoltage lockout (UVLO)
and overvoltage lockout (OVLO) features. Equation 6 through Equation 9 are for setting the thresholds define in
Figure 18.
R1
V1 = 1.26 ´
+ 1.26
(R2 + R3)
(6)
(R1 + Rx)
, where Rx = R4 P (R2 + R3)
Rx
(R1 + R2 + R3)
V4 = 1.26 ´
R3
æ R1 ö
V3 = V4 - 1.26 ´ ç
÷
è R4 ø
V2 = 1.26 ´
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(7)
(8)
(9)
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Device Functional Modes (continued)
Input
Voltage
R1
UV
15
+
1.26 V
1.26 V
+
S1
OPEN
HYS
2
R4
S2
CLOSED
LINE_GOOD
R2
OV
1
R3
+
1.26 V
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Line UVLO and OVLO Functional Diagram
ENABLE
LINE_GOOD
OFF
V1
V2
V3
V4
Figure 18. Line UVLO and OVLO Operation
The UVLO hysteresis and the OVLO hysteresis can be calculated as V2 – V1 and V4 – V3, respectively. By
examining the design equations, it becomes apparent that the value of R4 sets the amount of hysteresis at both
thresholds. By realizing this fact, the designer can then set the value of R4 based on the most critical hysteresis
specification either at high line or at low line. In most designs the value of R4 is determined by the desired
amount of hysteresis around the UVLO threshold. As an example, consider a telecom power supply with the
following input UVLO and OVLO design specifications:
• V1 = 32 V
• V2 = 34 V
• V3 = 83 V
• V4 = 84.7 V
Then,
• R1
• R2
• R3
• R4
=
=
=
=
14
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976 kΩ
24.9 kΩ
15 kΩ
604 kΩ
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Device Functional Modes (continued)
8.4.2 Start-Up JFET Section
A 110-V start-up JFET is included to start the device from a wide range (36 V to 75 V) telecom input source.
When VDD is lower than 13 V, the JFET is on, behaving as a current source charging the bias capacitors on
VDD and supplying current to the device. In this way, the VDD bypass capacitors are charged to 13 V where the
outputs start switching and the JFET is turned off. To enable a constant bias supply to the device during a pulse
skipping condition, the JFET is turned back on whenever VDD decreases below 10 V and the outputs are not
switching. Thus, the current from the JFET can overcome the internal bias currents, as long as the device is not
actively switching the output drivers. See Figure 19 for a representation of the JFET and VDD operation. The
OCC28220 does not contain an internal JFET and has a start-up threshold of 10 V which makes it capable of
directly operating off a 12-V dc bus.
VDD
13 V
13 V
8 − 14 V
10 V
8 V (UVLO off)
NORMAL OPERATION
0V
OUTx
GATE DRV
HV JFET
OFF
ON
ON
OFF
Figure 19. JFET Device Operation With VDD Voltage
8.4.3 Slope Compensation
The slope compensation circuit in the UCC2822x operates on a cycle-by-cycle basis. The two channels have
separate slope compensation circuits. These are fabricated in precisely the same way so as current sharing is
unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever that
channel's output is off. At the beginning of the PMW cycle, a current is mirrored off the SLOPE pin into the
capacitor, developing an independent ramp. Because the two channel's ramps start when the channel's output
changes from a low to high state, the ramps are thus interleaved. These internal ramps are added to the voltages
on the current sense pins, CS1 and CS2, and form an input to the PMW comparators.
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Device Functional Modes (continued)
REF
SLOPE
(5)
2.5/(16.6∗R_SLOPE)=I_SC
R_SLOPE
CTRL
(8)
PWM −
+
+
TO RESET
of
PWM LATCH
0.5V
C_SC
OUT 1
ON
S1
10 pF
OFF
CS1
(4)
S2
Figure 20. Slope Compensation Detail for Chanel 1.
Duplicate Matched Circuitry Exists for Channel 2.
To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslope to
each of the current sense signals before being applied to the input of the PWM comparator.
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC28220 control device from Texas Instruments is used in a dual-interleaved, forward converter that
enables the power supply designer to reduce output current ripple and reduce magnetic size per power stage
allowing for improved transient response. The UCC28220 is a dual-interleaved PWM controller with
programmable maximum duty cycle per channel up to 90% for interleaved forward and interleaved flyback
designs.
9.2 Typical Application
VIN
CS1
UCC28220
1
OV
2
HYS
UV 15
3
VDD
REF 14
4
CS1
OUT1 13
5
SLOPE
OUT2 12
N/C 16
1/2 UCC27424
Bias
VOUT
CS2
6
CS2
GND 11
7
SS
CHG 10
8
CTRL
DISCHG 9
1/2 UCC27424
E/A
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Interleaved Boost Application Circuit Using the UCC28220
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 lists the design parameters for the interleaved boost application circuit.
Table 1. Design Parameters
PARAMETER
VIN
VOUT
VRIPPLE
Current THD at 350 W
MIN
TYP
MAX
UNIT
85
110 or 230
265
V RMS
374
390
425
V
—
—
30
V
—
—
10%
PF at 350 W
0.95
—
—
Full load efficiency
90%
—
—
—
100
—
kHz
fS
Holdup requirements, tHOLD
—
—
20
ms
fLINE
47
50
60
Hz
9.2.2 Detailed Design Procedure
9.2.2.1 Overvoltage Protection and Undervoltage Lockout
The OVP function and undervoltage lockout (UVLO) were handled by the UCC28220. It is a simple comparator
that monitors the boost voltage. The OVP for this design was set to 425 V and UVLO was set to 108 V. The
preregulator does not start switching until VOUT reaches 108 V.
9.2.2.2 Peak Current Limit
Peak current limit is set by the maximum control voltage (VC) at the input of the UCC28220’s PWM comparator
with Equation 10 through Equation 12. Where a is the current sense transformer turns ratio of T1 and T2. The
peak current limit trip point was set for 130% of the nominal peak current to protect the boost FETs.
I
N
V
1
a= P = P = S =
NS VS IP 50
(10)
æ P
´ 2
DIL1 ö
÷ ´ 1.3
IPEAK = ç OUT
+
ç 2 ´ v in(min ) ´ h
2 ÷
è
ø
(11)
VC = 1.8, VCTRL was set to a maximum of 3 V to protect the UCC28220 CTRL pin.
VC - 0.5 V
2
RSENSE =
IPEAK ´ a
(12)
Equation 12 considers slope compensation that is added later.
The peak current of the FET during power up is 2 times IPEAK under normal operation as calculated with
Equation 13. This is due to the excessive slope compensation that is required for stability.
IPEAK (startup ) = 2 ´ IPEAK
(13)
9.2.2.3 Current Sense Transformer Reset Resistor (T1 and T2)
VC - 0.5 V
2
RRESET =
IPEAK ´ 1 - DMIN(LL ) ´ a
(
18
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(14)
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9.2.2.4 Oscillator and Maximum Duty Cycle Clamp
The UCC28220’s oscillator and maximum duty cycle clamp are setup through resistor RCHG and discharge. The
desired duty cycle clamp (DMAX) was set at 0.9 to stop the current sense transformers from saturating.
W
K OSC = 2.04 ´ 1010
S
(15)
(
)
Equation 15 is UCC28220's oscillator constant.
FOSC = 2 ´ fS
(16)
Equation 16 is UCC28220's internal oscillator frequency.
FOSC = 2 ´ fS
(17)
Equation 17 is the internal duty cycle clamp.
DMAX(OSC ) = 1 - 2 (1 - DMAX )
(18)
RDISCHG = K OSC
(1 - D
MAX(OSC )
)
FOSC
(19)
9.2.3 Application Curves
CH2: V OUT
100 V/div..
10 mV/div.
CH1: 100 V/div .
Rectified Line
t − Time − 5 ms/div.
POUT = 350 W
Figure 22. Output Ripple Voltage
t − Time − 100 ms/div .
Line transients at 350-W load
VIN stepped from 240 V to 120 V to 240 V
Figure 23. Line Dropout at Full Load
10 Power Supply Recommendations
The VDD power terminal for the device requires the placement of electrolytic capacitor as energy storage
capacitor. And requires the placement of low-ESR noise decoupling capacitance as directly as possible from the
VDD terminal to the VSS terminal, ceramic capacitors with stable dielectric characteristics over temperature are
recommended, such as X7R or better. TI recommends a 1-µF, 50-V e-capacitor.
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11 Layout
11.1 Layout Guidelines
1. TI recommends placing a 1-µF ceramic decoupling capacitor as close as possible between the VDD terminal
and GND, tracked directly to both terminals.
2. TI recommends placing a small, external filter capacitor on the CS1 and CS2 terminal. Track the filter
capacitor as directly as possible from the CS to GND terminal.
3. Reduce the total surface area of traces on the CS net to a minimum.
4. Connect decoupling and noise filter capacitors, as well as sensing resistors directly to the GND terminal in a
star-point fashion, ensuring that the current-carrying power tracks (such as the gate drive return) are track
separately to avoid noise and ground-drops that could affect the analogue signal integrity.
11.2 Layout Example
1
LINEOV
2
LINEHYS
3
VDD
4
CS1
VIN
16
LINEUV
15
REF
14
OUT1
13
5
SLOPE
OUT2
12
6
CS2
GND
11
7
SS
CHG
10
8
CTRL
DISCHG
9
Figure 24. UCC28221 Layout
20
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SLUS544G – SEPTEMBER 2003 – REVISED APRIL 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
An evaluation module and an associated user’s guide are available. The UCC28221 is used in a two-channel
interleaved Forward design converting from 36-V to 76-V dc input voltage to a regulated 12-V dc output. The
power module has two isolated 100 W forward power stages operating at 500 kHz, which are operating 180
degrees out of phase with each other allowing for output current ripple cancellation and smaller magnetic design.
This design also takes advantage of the UCC28221’s on-board 110-V internal JFET start up circuit that removes
the need of an external trickle charge resistor for boot strapping. This circuit turns off after auxiliary power is
supplied to the device conserving power.
UCC28221 200-W Evaluation Module (EVM) (SLUU173)
For other related documentation see the following:
• Unitrode - UC3854A/B and UC3855A-B Provide Power Limiting With Sinusoidal Input Current for PFC Front
Ends (SLUA196)
• Advanced PFC/PWM Combination Controller With Trailing-Edge/Trailing-Edge Modulation (SLUS608)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC28220
Click here
Click here
Click here
Click here
Click here
UCC28221
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28220D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28220
UCC28220DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28220
UCC28220PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28220
UCC28220PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28220
UCC28221D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28221
UCC28221DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28221
UCC28221PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
28221
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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