Order
Now
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
UCC28740 Constant-Voltage Constant-Current Flyback Controller
Using Optocoupled Feedback
1 Features
3 Description
•
•
The UCC28740 isolated-flyback power-supply
controller provides Constant-Voltage (CV) using an
optical coupler to improve transient response to largeload steps. Constant-Current (CC) regulation is
accomplished through Primary-Side Regulation (PSR)
techniques. This device processes information from
opto-coupled feedback and an auxiliary flyback
winding for precise high-performance control of
output voltage and current.
1
•
•
•
•
•
•
•
•
•
Less than 10-mW No-Load Power Capability
Optocoupled Feedback for CV, and
Primary-Side Regulation (PSR) for CC
Enables ±1% Voltage Regulation and ±5%
Current Regulation Across Line and Load
700-V Startup Switch
100-kHz Maximum Switching Frequency Enables
High-Power-Density Charger Designs
Resonant-Ring Valley-Switching Operation for
Highest Overall Efficiency
Frequency Dithering to Ease EMI Compliance
Clamped Gate-Drive Output for MOSFET
Overvoltage, Low-Line, and Overcurrent
Protection Functions
SOIC-7 Package
Create a Custom Design Using the UCC28740
With the WEBENCH® Power Designer
2 Applications
•
•
•
An internal 700-V startup switch, dynamically
controlled operating states, and a tailored modulation
profile support ultra-low standby power without
sacrificing startup time or output transient response.
Control algorithms in the UCC28740 allow operating
efficiencies to meet or exceed applicable standards.
The drive output interfaces to a MOSFET power
switch. Discontinuous conduction mode (DCM) with
valley-switching reduces switching losses. Modulation
of switching frequency and primary current-peak
amplitude (FM and AM) keeps the conversion
efficiency high across the entire load and line ranges.
The controller has a maximum switching frequency of
100 kHz and always maintains control of the peakprimary current in the transformer. Protection features
keep primary and secondary component stresses in
check. A minimum switching frequency of 170 Hz
facilitates the achievement of less than 10-mW noload power.
USB-Compliant Adapters and Chargers for
Consumer Electronics
– Smart Phones
– Tablet Computers
– Cameras
Standby Supply for TV and Desktop
White Goods
Device Information(1)
PART NUMBER
UCC28740
PACKAGE
BODY SIZE (NOM)
SOIC (7)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
VBULK
CB2
CB1
+
Typical V-I Diagram
VOUT
NP
COUT
NS
VOCV
±
4V
UCC28740
SOIC-7
RTL
VAUX
VDD
NA
RS1
HV
CVDD
RFB1
VS
ZFB
DRV
RLC
RS2
±5%
3V
2V
1V
CS
FB GND
Output Voltage (VO)
VAC
RCS
RFB2
Output Current (IO)
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
32
32
32
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2017) to Revision D
Page
•
Changed Pin 7 to Pin 8 to match the mechanical drawing. ................................................................................................... 3
•
Changed Layout Example's pin 7 to pin 8 to match the mechanical drawing...................................................................... 29
Changes from Revision B (December 2014) to Revision C
Page
•
Moved the timing parameters from the Electrical Characteristics table to the Switching Characteristics table .................... 6
•
Deleted quasi from quasi-resonant in the Transformer Turns Ratio, Inductance, Primary-Peak Current section .............. 21
•
Added the Development Support, Documentation Support, Receiving Notification of Documentation Updates, and
Community Resources sections ........................................................................................................................................... 30
Changes from Revision A (July 2013) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Original (July 2013) to Revision A
•
2
Page
Page
Changed marketing status from Product Preview to Production Data .................................................................................. 1
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
5 Pin Configuration and Functions
D Package
7-Pin SOIC
Top View
VDD
1
8
HV
VS
2
FB
3
6
DRV
GND
4
5
CS
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CS
5
I
The current-sense (CS) input connects to a ground-referenced current-sense resistor in series with the power
switch. The resulting voltage monitors and controls the peak primary current. A series resistor is added to this
pin to compensate for peak switch-current levels as the AC-mains input varies.
DRV
6
O
Drive (DRV) is an output that drives the gate of an external high-voltage MOSFET switching transistor.
FB
3
I
The feedback (FB) input receives a current signal from the optocoupler output transistor. An internal current
mirror divides the feedback current by 2.5 and applies it to an internal pullup resistor to generate a control
voltage, VCL. The voltage at this resistor directly drives the control law function, which determines the switching
frequency and the peak amplitude of the switching current .
GND
4
—
The ground (GND) pin is both the reference pin for the controller, and the low-side return for the drive output.
Special care must be taken to return all AC-decoupling capacitors as close as possible to this pin and avoid any
common trace length with analog signal-return paths.
HV
8
I
The high-voltage (HV) pin may connect directly, or through a series resistor, to the rectified bulk voltage and
provides a charge to the VDD capacitor for the startup of the power supply.
VDD
1
I
VDD is the bias-supply input pin to the controller. A carefully placed bypass capacitor to GND is required on this
pin.
I
Voltage sense (VS) is an input used to provide demagnetization timing feedback to the controller to limit
frequency, to control constant-current operation, and to provide output-overvoltage detection. VS is also used for
AC-mains input-voltage detection for peak primary-current compensation. This pin connects to a voltage divider
between an auxiliary winding and GND. The value of the upper resistor of this divider programs the AC-mains
run and stop thresholds, and factors into line compensation at the CS pin.
VS
2
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
3
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
and
(2)
.
MAX
UNIT
VHV
Start-up pin voltage, HV
MIN
700
V
VVDD
Bias supply voltage, VDD
38
V
IDRV
Continuous gate-current sink
50
mA
IDRV
Continuous gate-current source
Self-limiting
mA
IFB
Peak current, VS
1
mA
IVS
Peak current, FB
−1.2
mA
VDRV
Gate-drive voltage at DRV
–0.5
Self-limiting
V
Voltage, CS
–0.5
5
V
Voltage, FB
–0.5
7
V
Voltage, VS
–0.75
7
V
TJ
Operating junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the
operating ambient temperature ranges unless otherwise noted.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VVDD
Bias-supply operating voltage
CVDD
VDD bypass capacitor
IFB
Feedback current, continuous
IVS
VS pin current, out of pin
TJ
Operating junction temperature
MIN
MAX
9
35
0.047
–40
UNIT
V
µF
50
µA
1
mA
125
°C
6.4 Thermal Information
UCC28740
THERMAL METRIC (1)
D (SOIC)
UNIT
7 PINS
RθJA
Junction-to-ambient thermal resistance
141.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.8
°C/W
RθJB
Junction-to-board thermal resistance
89
°C/W
ψJT
Junction-to-top characterization parameter
23.5
°C/W
ψJB
Junction-to-board characterization parameter
88.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-VOLTAGE START UP
IHV
Start-up current out of VDD
VHV = 100 V, VVDD = 0 V, start state
IHVLKG25
Leakage current at HV
VHV = 400 V, run state, TJ = 25°C
100
250
500
µA
0.01
0.5
µA
BIAS SUPPLY INPUT
IRUN
Supply current, run
IDRV = 0, run state
2
2.65
mA
IWAIT
Supply current, wait
IDRV = 0, wait state
95
125
µA
ISTART
Supply current, start
IDRV = 0, VVDD = 18 V, start state, IHV = 0
18
30
µA
IFAULT
Supply current, fault
IDRV = 0, fault state
95
130
µA
UNDERVOLTAGE LOCKOUT
VVDD(on)
VDD turnon threshold
VVDD low to high
19
21
23
V
VVDD(off)
VDD turnoff threshold
VVDD high to low
7.35
7.75
8.15
V
VVSNC
Negative clamp level
IVSLS = –300 µA, volts below ground
190
250
325
mV
IVSB
Input bias current
VVS = 4 V
–0.25
0
0.25
µA
IFBMAX
Full-range input current
fSW = fSW(min)
VFBMAX
Input voltage at full range
IFB = 25 µA, TJ = 25°C
FB-input resistance, linearized
ΔIFB = 20 µA, centered at IFB = 15 µA, TJ =
25°C
Maximum CS threshold voltage
IFB = 0 µA (1)
VS INPUT
FB INPUT
RFB
16
23
30
µA
0.75
0.88
1
V
10
14
18
kΩ
738
773
810
mV
170
194
215
mV
3.6
4
4.45
V/V
318
330
343
mV
24
25
28.6
A/A
180
230
280
ns
20
25
CS INPUT
VCST(max)
(1)
VCST(min)
Minimum CS threshold voltage
IFB = 35 µA
KAM
AM-control ratio
VCST(max) / VCST(min)
VCCR
Constant-current regulation factor
KLC
Line-compensation current ratio
IVSLS = –300 µA, IVSLS / current out of CS pin
tCSLEB
Leading-edge blanking time
DRV output duration, V CS = 1 V
IDRS
DRV source current
VDRV = 8 V, VVDD = 9 V
RDRVLS
DRV low-side drive resistance
IDRV = 10 mA
6
12
VDRCL
DRV clamp voltage
VVDD = 35 V
14
16
V
RDRVSS
DRV pulldown in start-state
150
190
230
kΩ
V
DRIVERS
mA
Ω
PROTECTION
VOVP
Overvoltage threshold
At VS input, TJ = 25°C (2)
4.52
4.6
4.71
VOCP
Overcurrent threshold
At CS input
1.4
1.5
1.6
V
IVSL(run)
VS line-sense run current
Current out of VS pin increasing
190
225
275
µA
IVSL(stop)
VS line-sense stop current
Current out of VS pin decreasing
KVSL
VS line sense ratio
IVSL(run) / IVSL(stop)
TJ(stop)
Thermal-shutdown temperature
Internal junction temperature
(1)
(2)
70
80
100
µA
2.45
2.8
3.05
A/A
165
°C
This device automatically varies the control frequency and current sense thresholds to improve EMI performance. These threshold
voltages and frequency limits represent average levels.
The overvoltage threshold level at VS decreases with increasing temperature by 0.8 mV/°C. This compensation is included to reduce the
power-supply output overvoltage detection variance over temperature.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
5
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
6.6 Switching Characteristics
over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA
(unless otherwise noted)
PARAMETER
fSW(max)
Maximum switching frequency
fSW(min)
Minimum switching frequency
tZTO
Zero-crossing timeout delay
(1)
6
TEST CONDITIONS
IFB = 0 µA (1)
IFB = 35 µA
(1)
MIN
TYP
MAX
UNIT
91
100
106
kHz
140
170
210
Hz
1.8
2.1
2.55
µs
This device automatically varies the control frequency and current sense thresholds to improve EMI performance. These threshold
voltages and frequency limits represent average levels.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
6.7 Typical Characteristics
VVDD = 25 V, TJ = 25°C, unless otherwise noted.
10
10
HV = Open
Run State
HV = Open
IRUN, VDD = 25 V
1
IVDD - Bias-Supply Current (mA)
IVDD - Bias-Supply Current (mA)
1
Wait State
0.1
VDD Turn-Off
VDD Turn-On
0.01
Start State
IWAIT, VDD = 25 V
0.1
ISTART, VDD = 18 V
0.01
0.001
0.001
0.0001
0.0001
0
5
10
15
20
25
30
35
-50
-25
0
VDD - Bias-Supply Voltage (V)
25
50
75
100
125
TJ - Temperature (oC)
C001
C002
HV = Open
HV = Open
Figure 1. Bias-Supply Current vs. Bias-Supply Voltage
Figure 2. Bias-Supply Current vs. Temperature
320
300
VHV = 100 V, VVDD = 0 V
280
IVSL(run)
VS Line-Sense Current (µA)
IHV - HV Startup Current (µA)
250
240
200
160
120
200
150
100
IVSL(stop)
80
50
40
0
0
-50
-25
0
25
50
TJ - Temperature
75
100
125
-50
-25
0
25
50
TJ - Temperature
(oC)
75
100
125
(oC)
C003
C004
VHV = 100 V, VVDD = 0 V
Figure 3. HV Startup Current vs. Temperature
Figure 4. VS Line-Sense Currents vs. Temperature
350
VCCR - Constant-Current Regulation Factor (mV)
VCST(min) - Minimum CS Threshold Voltage (mV)
210
205
200
195
190
185
180
175
170
345
340
335
330
325
320
315
310
-50
-25
0
25
50
TJ - Temperature
75
100
125
-50
(oC)
-25
0
25
50
75
100
125
TJ - Temperature (oC)
C005
Figure 5. Minimum CS Threshold vs. Temperature
C006
Figure 6. Constant-Current Regulation Factor vs.
Temperature
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
7
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
Typical Characteristics (continued)
VVDD = 25 V, TJ = 25°C, unless otherwise noted.
34
200
32
190
IDRS - DRV Source Current (mA)
fSW(min) - Minimum Switching Frequency (Hz)
VDRV = 8 V, VVDD = 9 V
180
170
160
150
30
28
26
24
22
140
20
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
TJ - Temperature (oC)
TJ - Temperature (oC)
C007
C008
VDRV = 8 V, VVDD = 9 V
Figure 7. Minimum Switching Frequency vs. Temperature
Figure 8. DRV Source Current vs. Temperature
1.0
4.68
0.9
4.66
VOVP - VS Overvoltage Threshold (V)
VFB - FB Input Voltage (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
4.64
4.62
4.60
4.58
4.56
4.54
0.1
0.0
4.52
0
5
10
15
20
25
30
35
-50
IFB - FB Input Current (µA)
0
25
50
75
100
125
TJ - Temperature (oC)
C009
Figure 9. FB Input Voltage vs. FB Input Current
8
-25
C010
Figure 10. VS Overvoltage Threshold vs. Temperature
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
7 Detailed Description
7.1 Overview
The UCC28740 is a flyback power-supply controller which provides high-performance voltage regulation using an
optically coupled feedback signal from a secondary-side voltage regulator. The device provides accurate
constant-current regulation using primary-side feedback. The controller operates in discontinuous-conduction
mode (DCM) with valley-switching to minimize switching losses. The control law scheme combines frequency
with primary peak-current amplitude modulation to provide high conversion efficiency across the load range. The
control law provides a wide dynamic operating range of output power which allows the power-supply designer to
easily achieve less than 30-mW standby power dissipation using a standard shunt-regulator and optocoupler. For
a target of less than 10-mW standby power, careful loss-management design with a low-power regulator and
high-CTR optocoupler is required.
During low-power operating conditions, the power-management features of the controller reduce the deviceoperating current at switching frequencies below 32 kHz. At and above this frequency, the UCC28740 includes
features in the modulator to reduce the EMI peak energy of the fundamental switching frequency and harmonics.
A complete low-cost and low component-count charger-solution is realized using a straight-forward design
process.
7.2 Functional Block Diagram
IHV
GND
VDD
POWER
AND FAULT
MANAGEMENT
UVLO
21 V / 7.75 V
5V
FB
HV
OC Fault
OV Fault
LINE Fault
IFB
5V
480 k
14 k
VDD
VCL
IFB / 2.5
0.55 V
CONTROL
LAW
VCST
25 mA
DRV
VS
14 V
+
SAMPLER
VOVP
±
190 k
1 / fSW
OV Fault
VALLEY
SWITCHING
SECONDARY
TIMING
DETECT
S
Q
R
Q
CS
+
CURRENT
REGULATION
±
VCST
LEB
IVSLS
LINE
SENSE
IVSLS
10 k
IVSLS / KLC
±
+
+
LINE Fault
OC Fault
±
1.5 V
2.25 V / 0.8 V
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
9
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
7.3 Feature Description
7.3.1 Detailed Pin Description
VDD (Device Bias Voltage Supply) The VDD pin connects to a bypass capacitor-to-ground. The turnon UVLO
threshold is 21 V and turnoff UVLO threshold is 7.75 V with an available operating range up to 35 V
on VDD. The typical USB-charging specification requires the output current to operate in constantcurrent mode from 5 V down to at least 2 V which is achieved easily with a nominal VVDD of
approximately 25 V. The additional VDD headroom up to 35 V allows for VVDD to rise due to the
leakage energy delivered to the VDD capacitor during high-load conditions.
GND (Ground) UCC28740 has a single ground reference external to the device for the gate-drive current and
analog signal reference. Place the VDD-bypass capacitor close to GND and VDD with short traces
to minimize noise on the VS, FB, and CS signal pins.
HV (High-Voltage Startup) The HV pin connects directly to the bulk capacitor to provide a startup current to the
VDD capacitor. The typical startup current is approximately 250 µA which provides fast charging of
the VDD capacitor. The internal HV startup device is active until VVDD exceeds the turnon UVLO
threshold of 21 V at which time the HV startup device turns off. In the off state the HV leakage
current is very low to minimize standby losses of the controller. When VVDD falls below the 7.75 V
UVLO turnoff threshold the HV startup device turns on.
VS (Voltage Sense) The VS pin connects to a resistor-divider from the auxiliary winding to ground. The auxiliary
voltage waveform is sampled at the end of the transformer secondary-current demagnetization time
to provide accurate control of the output current when in constant-current mode. The waveform on
the VS pin determines the timing information to achieve valley-switching, and the timing to control
the duty-cycle of the transformer secondary current. Avoid placing a filter capacitor on this input
which interferes with accurate sensing of this waveform.
During the MOSFET on-time, this pin also senses VS current generated through RS1 by the
reflected bulk-capacitor voltage to provide for AC-input run and stop thresholds, and to compensate
the current-sense threshold across the AC-input range. For the AC-input run/stop function, the run
threshold on VS is 225 µA and the stop threshold is 80 µA.
At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to provide
output overvoltage protection. The values for the auxiliary voltage-divider upper-resistor, RS1, and
lower-resistor, RS2, are determined by Equation 1 and Equation 2.
RS1 =
VIN(run) ´ 2
NPA ´ IVSL(run)
where
•
•
•
RS2
NPA is the transformer primary-to-auxiliary turns-ratio,
VIN(run) is the AC RMS voltage to enable turnon of the controller (run),
(in case of DC input, leave out the √2 term in the equation),
IVSL(run) is the run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical
Characteristics).
(1)
RS1 u VOVP
NAS u VOV
VF
VOVP
where
•
•
•
•
•
VOV is the maximum allowable peak voltage at the converter output,
VF is the output-rectifier forward drop at near-zero current,
NAS is the transformer auxiliary-to-secondary turns-ratio,
RS1 is the VS divider high-side resistance,
VOVP is the overvoltage detection threshold at the VS input (see Electrical Characteristics).
(2)
FB (Feedback) The FB pin connects to the emitter of an analog-optocoupler output transistor which usually has
the collector connected to VDD. The current supplied to FB by the optocoupler is reduced internally
by a factor of 2.5 and the resulting current is applied to an internal 480-kΩ resistor to generate the
control law voltage (VCL). This VCL directly determines the converter switching frequency and peak
primary current required for regulation per the control-law for any given line and load condition.
10
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Feature Description (continued)
DRV (Gate Drive) The DRV pin connects to the MOSFET gate pin, usually through a series resistor. The gate
driver provides a gate-drive signal limited to 14 V. The turnon characteristic of the driver is a 25-mA
current source which limits the turnon dv/dt of the MOSFET drain and reduces the leading-edge
current spike while still providing a gate-drive current to overcome the Miller plateau. The gate-drive
turnoff current is determined by the RDSON of the low-side driver along with any external gate-drive
resistance. Adding external gate resistance reduces the MOSFET drain turn-off dv/dt, if necessary.
CS (Current Sense) The current-sense pin connects through a series resistor (RLC) to the current-sense resistor
(RCS). The maximum current-sense threshold (VCST(max)) is 0.773 V for IPP(max), and the minimum
current-sense threshold (VCST(min)) is 0.194 V for IPP(min). RLC provides the feed-forward line
compensation to eliminate changes in IPP with input voltage due to the propagation delay of the
internal comparator and MOSFET turnoff time. An internal leading-edge blanking time of 235 ns
eliminates sensitivity to the MOSFET turnon current spike. Placing a bypass capacitor on the CS
pin is unnecessary. The target output current in constant-current (CC) regulation determines the
value of RCS. The values of RCS and RLC are calculated using Equation 3 and Equation 4. The term
VCCR is the product of the demagnetization constant, 0.425, and VCST(max). VCCRis held to a tighter
accuracy than either of its constituent terms. The term ηXFMR accounts for the energy stored in the
transformer but not delivered to the secondary. This term includes transformer resistance and core
loss, bias power, and primary-to-secondary leakage ratio.
Example:
With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%, and bias
power to output power ratio of 0.5%, the ηXFMR value at full power is approximately: 1 - 0.05 - 0.035 - 0.005 =
0.91.
V
´ NPS
RCS = CCR
´ hXFMR
2IOCC
where
•
•
•
•
RLC =
VCCR is a constant-current regulation factor (see Electrical Characteristics),
NPS is the transformer primary-to-secondary turns-ratio (a ratio of 13 to 15 is typical for 5-V output),
IOCC is the target output current in constant-current regulation,
ηXFMR is the transformer efficiency at full power.
(3)
KLC ´ RS1 ´ RCS ´ tD ´ NPA
LP
where
•
•
•
•
•
•
RS1 is the VS pin high-side resistor value,
RCS is the current-sense resistor value,
tD is the total current-sense delay consisting of MOSFET turnoff delay, plus approximately 50 ns internal delay,
NPA is the transformer primary-to-auxiliary turns-ratio,
LP is the transformer primary inductance,
KLC is a current-scaling constant for line compensation (see Electrical Characteristics).
(4)
7.3.2 Valley-Switching and Valley-Skipping
The UCC28740 uses valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI, and to
minimize the turnon current spike at the current-sense resistor. The controller operates in valley-switching in all
load conditions unless the VDS ringing diminishes to the point where valleys are no longer detectable.
As shown in Figure 11, the UCC28740 operates in a valley-skipping mode (also known as valley-hopping) in
most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest
available VDS voltage.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
11
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
Feature Description (continued)
VDS
VDRV
Figure 11. Valley-Skipping Mode
Valley-skipping modulates each switching cycle into discrete period durations. During FM operation, the
switching cycles are periods when energy is delivered to the output in fixed packets, where the power-per-cycle
varies discretely with the switching period. During operating conditions when the switching period is relatively
short, such as at high-load and low-line, the average power delivered per cycle varies significantly based on the
number of valleys skipped between cycles. As a consequence, valley-skipping adds additional ripple voltage to
the output with a frequency and amplitude dependent upon the loop-response of the shunt-regulator. For a load
with an average power level between that of cycles with fewer valleys skipped and cycles with more valleys
skipped, the voltage-control loop modulates the FB current according to the loop-bandwidth and toggles between
longer and shorter switching periods to match the required average output power.
7.3.3 Startup Operation
An internal high-voltage startup switch, connected to the bulk-capacitor voltage (VBULK) through the HV pin,
charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 µA
to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turnon threshold the controller is enabled, the
converter starts switching, and the startup switch turns off.
Often at initial turnon, the output capacitor is in a fully discharged state. The first three switching-cycle current
peaks are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these
three cycles, if the sampled voltage at VS is less than 1.33 V, the controller operates in a special startup mode.
In this mode, the primary current peak amplitude of each switching cycle is limited to approximately 0.63 ×
IPP(max) and DMAGCC increases from 0.425 to 0.735. These modifications to IPP(max) and DMAGCC during startup
allows high-frequency charge-up of the output capacitor to avoid audible noise while the demagnetization voltage
is low. Once the sampled VS voltage exceeds 1.38 V, DMAGCC is restored to 0.425 and the primary current peak
resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to maintain a
constant output current until the output voltage enters regulation. Thereafter, the controller responds to the
condition dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor
charges to 21 V plus the time the output capacitor charges.
7.3.4 Fault Protection
The UCC28740 provides extensive fault protection. The protection functions include:
• Output overvoltage
• Input undervoltage
• Internal overtemperature
• Primary overcurrent fault
• CS-pin fault
• VS-pin fault
A UVLO reset and restart sequence applies to all fault-protection events.
12
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Feature Description (continued)
The output-overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample of VS
exceeds 4.6 V, the device stops switching and the internal current consumption becomes IFAULT which
discharges the VDD capacitor to the UVLO-turnoff threshold. After that, the device returns to the start state and a
startup sequence ensues.
The UCC28740 always operates with cycle-by-cycle primary peak current control. The normal operating voltage
range of the CS pin is 0.773 V to 0.194 V. An additional protection, not filtered by leading-edge blanking, occurs
if the CS pin voltage reaches 1.5 V, which results in a UVLO reset and restart sequence.
Current into the VS pin during the MOSFET on-time determines the line-input run and stop thresholds. While the
VS pin clamps close to GND during the MOSFET on-time, the current through RS1 is monitored to determine a
sample of VBULK. A wide separation of the run and stop thresholds allows for clean startup and shutdown of the
power supply with the line voltage. The run-current threshold is 225 µA and the stop-current threshold is 80 µA.
The internal overtemperature-protection threshold is 165°C. If the junction temperature reaches this threshold the
device initiates a UVLO-reset cycle. If the temperature is still high at the end of the UVLO cycle, the protection
cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.
7.4 Device Functional Modes
7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
Figure 12 shows a simplified flyback convertor with the main output-regulation blocks of the device shown, along
with typical implementation of secondary-side-derived regulation. The power-train operation is the same as any
DCM-flyback circuit. A feedback current is optically coupled to the controller from a shunt-regulator sensing the
output voltage.
+ VF ±
VBULK
Auxiliary
VOUT
COUT
Timing
Primary
Secondary
RLOAD
RS1
VS
Discriminator and
Sampler
RS2
VCL
GD
DRV
Control Law
Minimum Period
and Peak
Primary Current
VDD
RTL
CS
RCS
Zero Crossings
ROPT
RFB1
Mirror Network
FB
IOPT
IFB
ZFB
RFB2
Figure 12. Simplified Flyback Convertor
(With the Main Voltage Regulation Blocks)
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
13
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
Device Functional Modes (continued)
In this configuration, a secondary-side shunt-regulator, such as the TL431, generates a current through the input
photo-diode of an optocoupler. The photo-transistor delivers a proportional current that is dependent on the
current-transfer ratio (CTR) of the optocoupler to the FB input of the UCC28740 controller. This FB current then
converts into the VCL by the input-mirror network, detailed in the device block diagram (see Functional Block
Diagram). Output-voltage variations convert to FB-current variations. The FB-current variations modify the VCL
which dictates the appropriate IPP and fSW necessary to maintain CV regulation. At the same time, the VS input
senses the auxiliary winding voltage during the transfer of transformer energy to the secondary output to monitor
for an output overvoltage condition. When fSW reaches the target maximum frequency, chosen between 32 kHz
and 100 kHz, CC operation is entered and further increases in VCL have no effect.
Figure 13 shows that as the secondary current decreases to zero, a clearly defined down slope reflects the
decreasing rectifier VF combined with stray resistance voltage-drop (ISRS). To achieve an accurate representation
of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the leakage-inductance
reset and ringing while continuously sampling the auxiliary voltage during the down slope after the ringing
diminishes. The discriminator then captures the voltage signal at the moment that the secondary-winding current
reaches zero. The internal overvoltage threshold on VS is 4.6 V. Temperature compensation of –0.8 mV/°C on
the overvoltage threshold offsets the change in the output-rectifier forward voltage with temperature. The resistor
divider is selected as outlined in the VS pin description (see Detailed Pin Description).
VS Sample
(VOUT+VF) NAS
0V
±VBULK / NPA
Figure 13. Auxiliary-Winding Voltage
The UCC28740 VS-signal sampler includes signal-discrimination methods to ensure an accurate sample of the
output voltage from the auxiliary winding. Controlling some details of the auxiliary-winding signal to ensure
reliable operation is necessary; specifically, the reset time of the leakage inductance and the duration of any
subsequent leakage-inductance ringing. See Figure 14 for a detailed illustration of waveform criteria to ensure a
reliable sample on the VS pin.
The first detail to examine is the duration of the leakage-inductance reset pedestal, tLK_RESET, in Figure 14.
Because tLK_RESET mimics the waveform of the secondary-current decay, followed by a sharp downslope,
tLK_RESET is internally blanked for a duration which scales with the peak primary current. Keeping the leakagereset time to less than 600 ns for IPP(min), and less than 2.2 µs for IPP(max) is important.
The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET. The peak-to-peak voltage
variation at the VS pin must be less than 100 mVp-p for at least 200 ns before the end of the demagnetization
time (tDM). A concern with excessive ringing usually occurs during light or no-load conditions, when tDM is at the
minimum. The tolerable ripple on VS is scaled up to the auxiliary-winding voltage by RS1 and RS2, and is equal to
100 mV × (RS1 + RS2) / RS2 .
14
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Device Functional Modes (continued)
tLK_RESET
tSMPL
VS ring (p-p)
0V
tDM
Figure 14. Auxiliary-Winding Waveform Details
During voltage regulation, the controller operates in frequency-modulation mode and amplitude-modulation
mode, as shown in Figure 15. The internal operating-frequency limits of the device are 100 kHz and fSW(min). The
maximum operating frequency of the converter at full-load is generally chosen to be slightly lower than 100 kHz
to allow for tolerances, or significantly lower due to switching-loss considerations. The maximum operating
frequency and primary peak current chosen determine the transformer primary inductance of the converter. The
shunt-regulator bias power, output preload resistor (if any), and low-power conversion efficiency determine the
minimum-operating frequency of the converter. Voltage-loop stability compensation is applied at the shuntregulator which drives the opto-coupled feedback signal. The tolerances chosen for the shunt-regulator reference
and the sense resistors determines the regulation accuracy.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
15
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
Device Functional Modes (continued)
Control-Law Profile in Constant-Voltage (CV) Mode
IPP(max)
IPP (peak primary current)
100 kHz
fSW
IPP
fSW
32 kHz
IPP(max) / 4
FM
AM
FM
fSW = 170 Hz
3 kHz
0V
0.75 V
1.3 V
2.2 V
3.55 V
4.9 V
5V
Control Law Voltage, Internal (VCL)
26 µA
22.1 µA
19.3 µA
14.6 µA
7.55 µA
0.5 µA
Corresponding Feedback Current, FB Input (IFB)
Figure 15. Frequency and Amplitude Modulation Modes
(During CV Regulation)
The level of feedback current (IFB) into the FB pin determines the internal VCL which determines the operating
point of the controller while in CV mode. When IFB rises above 22 µA, no further decrease in fSW occurs. When
the output-load current increases to the point where maximum fSW is reached, control transfers to CC mode. All
current, voltage, frequency, breakpoints, and curve-segment linearity depicted in Figure 15 are nominal.
Figure 15 indicates the general operation of the controller while in CV mode, although minor variations may occur
from part to part. An internal frequency-dithering mechanism is enabled when IFB is less than 14.6 µA to help
reduce conducted EMI (including during CC-mode operation), and is disabled otherwise.
7.4.2 Primary-Side Constant-Current (CC) Regulation
When the load current of the converter increases to the predetermined constant-current limit, operation enters
CC mode. In CC mode, output voltage regulation is lost and the shunt-regulator drives the current and voltage at
FB to minimum. During CC mode, timing information at the VS pin and current information at the CS pin allow
accurate regulation of the average current of the secondary winding. The CV-regulation control law dictates that
as load increases approaches CC regulation the primary peak current will be at IPP(max). The primary peak
current, turns-ratio, demagnetization time tDM, and switching period tSW determine the secondary average output
current (see Figure 16). Ignoring leakage-inductance effects, the average output current is given by Equation 5.
When the demagnetization duty-cycle reaches the CC-regulation reference, DMAGCC, in the current-control block,
the controller operates in frequency modulation (FM) mode to control the output current for any output voltage at
or below the voltage-regulation target as long as the auxiliary winding keeps VVDD above the UVLO turnoff
threshold. As the output voltage falls, tDM increases. The controller acts to increase tSW to maintain the ratio of
tDM to switching period (tDM / tSW) at a maximum of 0.425 (DMAGCC), thereby maintaining a constant average
output current.
16
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Device Functional Modes (continued)
IS ´ NS
NP
IPP
tON
tDM
tSW
UDG-12203
Figure 16. Transformer-Current Relationship
I
N
t
IOUT = PP ´ P ´ DM
2 NS tSW
(5)
Fast, accurate, opto-coupled CV control combined with line-compensated PSR CC control results in highperformance voltage and current regulation which minimizes voltage deviations due to heavy load and unload
steps, as illustrated by the V-I curve in Figure 17.
VOCV
Output Voltage (VO)
VO(min)
IOCC ±5%
Minimum allowable
transient voltage level
for heavy load step
Output Current (IO)
IOCC
Figure 17. Typical Target Output V-I Characteristic
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
17
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28740 is a flyback controller that provides constant-voltage (CV) mode control and constant current
(CC) mode control for precise output regulation. While in CV operating range, the controller uses an opto-coupler
for tight voltage regulation and improved transient response to large load steps. Accurate regulation while in CC
mode is provided by primary side control. The UCC28740 uses frequency modulation, peak primary current
modulation, valley switching and valley hopping in its control algorithm in order to maximize efficiency over the
entire operating range.
8.2 Typical Application
The UCC28740 is well suited for use in isolated off-line systems requiring high efficiency and fault protection
features such as USB compliant adapters and chargers for consumer electronics such a smart phones, tablet
computers, and cameras. A 10-W application for a USB charger is shown in Figure 18.
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28740 controller. See Figure 18 for component names and network locations. The design procedure
equations use terms that are defined below.
+ VF ±
VBULK
VAC
VAUX
CB2
CB1
+
NP
VOUT
COUT
NS
±
+ VFA ±
NA
RS1
UCC28740
SOIC-7
VVDD
VDD
HV
ROPT
CVDD
VE
RS2
RTL
CFB3
RFB1
VS
DRV
RLC
RFB3
IFB
IOPT
CS
FB GND
ZFB
RCS
RFB4
RFB2
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Design Procedure Application Example
18
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Typical Application (continued)
8.2.1 Design Requirements
Table 1. Design Parameters
PARAMETER
NOTES AND CONDITIONS
MIN
NOM
MAX
UNIT
85
115/230
265
VRMS
INPUT CHARACTERISTICS
Input Voltage, VIN
Maximum Input Current
VIN = VINmin, IOUT = IOUTmax
Line Frequency
No Load Input Power
Consumption
0.265
47
60/50
VINmin ≤ VIN ≤ VINmax, IOUT = 0 A
ARMS
63
Hz
20
mW
OUTPUT CHARACTERISTICS
Output Voltage, VOUT
VINmin ≤ VIN ≤ VINmax, 0 A ≤ IOUT ≤ IOUTmax
Output Load Current, CV Mode,
IOUTmax
VINmin ≤ VIN ≤ VINmax
Output Voltage Regulation
4.95
5
5.05
V
1.995
2.1
2.205
A
Line Regulation: VINmin ≤ VIN ≤ VINmax, IOUT ≤
IOUTmax
0.1%
Load Regulation: 0 A ≤ IOUT ≤ IOUTmax
0.1%
Output Voltage Ripple
VINmin ≤ VIN ≤ VINmax, 0 A ≤ IOUT ≤ IOUTmax
150
mVpp
Output Overcurrent, ICCC
VINmin ≤ VIN ≤ VINmax
2.5
A
Minimum Output Voltage, CC
Mode
VINmin ≤ VIN ≤ VINmax, IOUT = IOCC
2
V
Brown-out Protection
IOUT = IOUTmax
Transient Response Undershoot
IOUT = IOUTmax to 0-A load transient
Transient Response Time
IOUT = IOUTmax to 0-A load transient
1.78
68
VRMS
4.3
V
20
ms
71
kHz
SYSTEMS CHARACTERISTICS
Switching Frequency, fSW
Average Efficiency
1.2
25%, 50%, 75%, 100% load average at
nominal input voltages
81%
Operating Temperature
25
°C
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28740 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
19
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
8.2.2.2
www.ti.com
Standby Power Estimate and No-Load Switching Frequency
Assuming minimal no-load standby power is a critical design requirement, determine the estimated no-load
power loss based on an accounting of all no-load operating and leakage currents at their respective voltages.
Close attention to detail is necessary to account for all of the sources of leakage, however, in many cases,
prototype measurement is the only means to obtain a realistic estimation of total primary and secondary leakage
currents. At present, converter standby power is certified by compliance-agency authorities based on steadystate room-temperature operation at the highest nominal input voltage rating (typically 230 Vrms).
Equation 6 estimates the standby power loss from the sum of all leakage currents of the primary-side
components of the converter. These leakage currents are measured in aggregate by disconnecting the HV input
of the controller from the bulk-voltage rail to prevent operating currents from interfering with the leakage
measurement.
nP
PPRI _ SB
VBULK u
¦IPRI _ LK
K
(6)
k 1
Equation 7 estimates the standby power loss from the sum of all leakage and operating currents of the
secondary-side components on the output of the converter. Leakage currents result from reverse voltage applied
across the output rectifier and capacitors, while the operating current includes currents required by the shuntregulator, optocoupler, and associated components.
nS
PSEC _ SB
VOCV u
¦ISEC
K
(7)
k 1
Equation 8 estimates the standby power loss from the sum of all leakage and operating currents of the auxiliaryside components on the controller of the converter. Leakage currents of the auxiliary diode and capacitor are
usually negligible. The operating current includes the wait-state current, IWAIT, of the UCC28740 controller, plus
the optocoupler-output current for the FB network in the steady-state no-load condition. The VDD voltage in the
no-load condition VVDDNL are the lowest practicable value to minimize loss.
na
PAUX _ SB
VVDDNL u
¦IAUX
K
(8)
k 1
Note that PPRI_SB is the only loss that is not dependent on transformer conversion efficiency. PSEC_SB and PAUX_SB
are processed through the transformer and incur additional losses as a consequence. Typically, the transformer
no-load conversion efficiency ηSWNL lies in the range of 0.50 to 0.70. Total standby input power (no-load
condition) is estimated by Equation 9.
1
PSB PPRI _ SB
PSEC _ SB PAUX _ SB
KSWNL
(9)
Although the UCC28740 is capable of operating at the minimum switching frequency of 170 Hz, a typical
converter is likely to require a higher frequency to sustain operation at no-load. An accurate estimate of the noload switching frequency fSWNL entails a thorough accounting of all switching-related energy losses within the
converter including parasitic elements of the power-train components. In general, fSWNL is likely to lie within the
range of 400 Hz to 800 Hz. A more detailed treatment of standby power and no-load frequency is beyond the
scope of this data sheet.
8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input bulk capacitance, CB1 and CB2 total, in order to determine the
maximum Np-to-Ns turns-ratio of the transformer. The input power of the converter based on target full-load
efficiency, the minimum input RMS voltage, and the minimum AC input frequency determine the input
capacitance requirement.
Maximum input power is determined based on IOCC, VOCV, VCBC (if used), and the full-load conversion-efficiency
target.
VOCV VCBC u IOCC
PIN
K
(10)
20
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Equation 11 provides an accurate solution for the total input capacitance based on a target minimum bulkcapacitor voltage. Alternatively, to target a given input capacitance value, iterate the minimum capacitor voltage
to achieve the target capacitance value.
CBULK
æ
æ VBULK(min)
1
2PIN ´ ç 0.25 +
´ arcsin ç
ç
2p
ç
è 2 ´ VIN(min)
è
=
2VIN(min)2 - VBULK(min)2 ´ fLINE
(
)
öö
÷÷
÷÷
øø
(11)
8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
The target maximum switching frequency at full-load, the minimum input-capacitor bulk voltage, and the
estimated DCM resonant time determine the maximum primary-to-secondary turns-ratio of the transformer.
Initially determine the maximum-available total duty-cycle of the on-time and secondary conduction time based
on the target switching frequency, fMAX, and DCM resonant time. For DCM resonant frequency, assume 500 kHz
if an estimate from previous designs is not available. At the transition-mode operation limit of DCM, the interval
required from the end of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM
resonant period (tR), or 1 µs assuming 500 kHz resonant frequency. The maximum allowable MOSFET on-time
DMAX is determined using Equation 12.
§t
·
DMAX 1 DMAGCC ¨ R u fMAX ¸
© 2
¹
(12)
When DMAX is known, the maximum primary-to-secondary turns-ratio is determined with Equation 13. DMAGCC is
defined as the secondary-diode conduction duty-cycle during CC operation and is fixed internally by the
UCC28740 at 0.425. The total voltage on the secondary winding must be determined, which is the sum of VOCV,
VF, and VOCBC. For the 5-V USB-charger applications, a turns ratio range of 13 to 15 is typically used.
DMAX ´ VBULK(min)
NPS(max) =
DMAGCC ´ (VOCV + VF + VOCBC )
(13)
A higher turns-ratio generally improves efficiency, but may limit operation at low input voltage. Transformer
design iterations are generally necessary to evaluate system-level performance trade-offs. When the optimum
turns-ratio NPS is determined from a detailed transformer design, use this ratio for the following parameters.
The UCC28740 constant-current regulation is achieved by maintaining DMAGCC at the maximum primary peak
current setting. The product of DMAGCC and VCST(max) defines a CC-regulating voltage factor VCCR which is used
with NPS to determine the current-sense resistor value necessary to achieve the regulated CC target, IOCC (see
Equation 14).
Because a small portion of the energy stored in the transformer does not transfer to the output, a transformerefficiency term is included in the RCS equation. This efficiency number includes the core and winding losses, the
leakage-inductance ratio, and a bias-power to maximum-output-power ratio. An overall-transformer efficiency of
0.91 is a good estimate based on 3.5% leakage inductance, 5% core & winding loss, and 0.5% bias power, for
example. Adjust these estimates as appropriate based on each specific application.
V
´ NPS
RCS = CCR
´ hXFMR
2IOCC
(14)
The primary transformer inductance is calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency, output voltage and current targets, and transformer
power losses are included in Equation 16.
First, determine the transformer primary peak current using Equation 15. Peak primary current is the maximum
current-sense threshold divided by the current-sense resistance.
VCST(max)
IPP(max) =
RCS
(15)
LP =
2 (VOCV + VF + VOCBC ) ´ IOCC
hXFMR ´ IPP(max)2 ´ fMAX
(16)
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
21
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
NAS is determined by the lowest target operating output voltage while in constant-current regulation and by the
VDD UVLO turnoff threshold of the UCC28740. Additional energy is supplied to VDD from the transformer
leakage-inductance which allows a lower turns ratio to be used in many designs.
VVDD(off ) VFA
NAS
VOCC VF
(17)
8.2.2.5 Transformer Parameter Verification
Because the selected transformer turns-ratio affects the MOSFET VDS and the secondary and auxiliary rectifier
reverse voltages, a review of these voltages is important. In addition, internal timing constraints of the UCC28740
require a minimum on time of the MOSFET (tON) and a minimum demagnetization time (tDM) of the transformer in
the high-line minimum-load condition. The selection of fMAX, LP, and RCS affects the minimum tON and tDM.
Equation 18 and Equation 19 determine the reverse voltage stresses on the secondary and auxiliary rectifiers.
Stray inductance can impress additional voltage spikes upon these stresses and snubbers may be necessary.
VIN(max) u 2
VREVS
NPS
VIN(max) u 2
VREVA
NPA
u VOV
(18)
u VVDD
(19)
For the MOSFET VDS peak voltage stress, an estimated leakage inductance voltage spike (VLK) is included.
VDSPK
VIN(max) u 2
VOCV
VF
VOCBC u NPS
VLK
(20)
Equation 21 determines if tON(min) exceeds the minimum tON target of 280 ns (maximum tCSLEB). Equation 22
verifies that tDM(min) exceeds the minimum tDM target of 1.2 µs.
IPP(max)
LP
t ON(min)
u
K AM
VIN(max) u 2
(21)
tDM(min)
tON(min) u VIN(max) u 2
NPS u VOCV
VF
(22)
8.2.2.6 VS Resistor Divider, Line Compensation
The VS divider resistors determine the output overvoltage detection point of the flyback converter. The high-side
divider resistor (RS1) determines the input-line voltage at which the controller enables continuous DRV operation.
RS1 is determined based on transformer primary-to-auxiliary turns-ratio and desired input voltage operating
threshold.
RS1 =
VIN(run) ´ 2
NPA ´ IVSL(run)
(23)
The low-side VS pin resistor is then selected based on the desired overvoltage limit, VOV.
RS1 u VOVP
RS2
NAS u VOV VF VOVP
(24)
The UCC28740 maintains tight constant-current regulation over varying input line by using the line-compensation
feature. The line-compensation resistor (RLC) value is determined by current flowing in RS1 and the total internal
gate-drive and external MOSFET turnoff delay. Assume an internal delay of 50 ns in the UCC28740.
K ´ RS1 ´ RCS ´ tD ´ NPA
RLC = LC
LP
(25)
22
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
8.2.2.7 Output Capacitance
The output capacitance value is often determined by the transient-response requirement from the no-load
condition. For example, in typical low-power USB-charger applications, there is a requirement to maintain a
minimum transient VO of 4.1 V with a load-step ITRAN from 0 mA to 500 mA. Yet new higher-performance
applications require smaller transient voltage droop VOΔ with ITRAN of much greater amplitude (such as from noload to full-load), which drives the need for high-speed opto-coupled voltage feedback.
I
ut
COUT t TRAN RESP
VO'
where
•
tRESP is the time delay from the moment ITRAN is applied to the moment when IFB falls below 1 µA
(26)
Additional considerations for the selection of appropriate output capacitors include ripple-current, ESR, and ESL
ratings necessary to meet reliability and ripple-voltage requirements. Detailed design criteria for these
considerations are beyond the scope of this datasheet.
8.2.2.8 VDD Capacitance, CVDD
The capacitance on VDD must supply the primary-side operating current used during startup and between lowfrequency switching pulses. The largest result of three independent calculations denoted in Equation 27,
Equation 28, and Equation 29 determines the value of CVDD.
At startup, when VVDD(on) is reached, CVDD alone supplies the device operating current and MOSFET gate current
until the output of the converter reaches the target minimum-operating voltage in CC regulation, VOCC. Now the
auxiliary winding sustains VDD for the UCC28740 above UVLO. The total output current available to the load and
to charge the output capacitors is the CC-regulation target, IOCC. Equation 27 assumes that all of the output
current of the converter is available to charge the output capacitance until VOCC is achieved. For typical
applications, Equation 27 includes an estimated qGfSW(max) of average gate-drive current and a 1-V margin added
to VVDD.
C
u VOCC
IRUN qG fSW(max) u OUT
IOCC
CVDD t
VDD(on) VVDD(off ) 1 V
(27)
During a worst-case un-load transient event from full-load to no-load, COUT overcharges above the normal
regulation level for a duration of tOV, until the output shunt-regulator loading is able to drain VOUT back to
regulation. During tOV, the voltage feedback loop and optocoupler are saturated, driving maximum IFB and
temporarily switching at fSW(min). The auxiliary bias current expended during this situation exceeds that normally
required during the steady-state no-load condition. Equation 28 calculates the value of CVDD (with a safety factor
of 2) required to ride through the tOV duration until steady-state no-load operation is achieved.
2 u IAUXNL(max) u t OV
CVDD t
VVDDFL VVDD(off ) 1 V
(28)
Finally, in the steady-state no-load operating condition, total no-load auxiliary-bias current, IAUXNL is provided by
the converter switching at a no-load frequency, fSWNL, which is generally higher than fSW(min). CVDD is calculated to
maintain a target VDD ripple voltage lower than ΔVVDD, using Equation 29.
1
IAUXNL u
fSWNL
CVDD t
'VVDD
(29)
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
23
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
8.2.2.9 Feedback Network Biasing
Achieving very low standby power while maintaining high-performance load-step transient response requires
careful design of the feedback network. Optically coupled secondary-side regulation is used to provide the rapid
response needed when a heavy load step occurs during the no-load condition. One of the most commonly used
devices to drive the optocoupler is the TL431 shunt-regulator, due to its simplicity, regulation performance, and
low cost. This device requires a minimum bias current of 1 mA to maintain regulation accuracy. Together with the
UCC28740 primary-side controller, careful biasing will ensure less than 30 mW of standby power loss at room
temperature. Where a more stringent standby loss limit of less than 10 mW is required, the TLV431 device is
recommended due to its minimum 80-µA bias capability.
Facilitating these low standby-power targets is the approximate 23-µA range of the FB input for full to no-load
voltage regulation. The control-law profile graph (see Figure 15) shows that for FB-input current greater than 22
µA, no further reduction in switching frequency is possible. Therefore, minimum power is converted at fSW(min).
However, the typical minimum steady-state operating frequency tends to be in the range of several-hundred
Hertz, and consequently the maximum steady-state FB current at no-load will be less than IFBMAX. Even so,
prudent design practice dictates that IFBMAX should be used for conservative steady-state biasing calculations. At
this current level, VFBMAX can be expected at the FB input.
Referring to the Design Procedure Application Example in Figure 18, the main purpose of RFB4 is to speed up the
turnoff time of the optocoupler in the case of a heavy load-step transient condition. The value of RFB4 is
determined empirically due to the variable nature of the specific optocoupler chosen for the design, but tends to
fall within the range of 10 kΩ to 100 kΩ. A tradeoff must be made between a lower value for faster transient
response and a higher value for lower standby power. RFB4 also serves to set a minimum bias current for the
optocoupler and to drain dark current.
It is important to understand the distinction between steady-state no-load bias currents and voltages which affect
standby power, and the varying extremes of these same currents and voltages which affect regulation during
transient conditions. Design targets for minimum standby loss and maximum transient response often result in
conflicting requirements for component values. Trade-offs, such as for RFB4 as discussed previously, must be
made.
During standby operation, the total auxiliary current (used in Equation 8) is the sum of IWAIT into the IC and the
no-load optocoupler-output current ICENL. This optocoupler current is given by Equation 30.
VFBMAX
ICENL IFBMAX
RFB4
(30)
For fast response, the optocoupler-output transistor is biased to minimize the variation of VCE between full-load
and no-load operation. Connecting the emitter directly to the FB input of the UCC28740 is possible, however, an
unload-step response may unavoidably drive the optocoupler into saturation which will overload the FB input with
full VDD applied. A series-resistor RFB3 is necessary to limit the current into FB and to avoid excess draining of
CVDD during this type of transient situation. The value of RFB3 is chosen to limit the excess IFB and RFB4 current to
an acceptable level when the optocoupler is saturated. Like RFB4, the RFB3 value is also chosen empirically
during prototype evaluation to optimize performance based on the conditions present during that situation. A
starting value may be estimated using Equation 31.
VVDDNL 1 V
RFB3
ICENL
(31)
Note that RFB3 is estimated based on the expected no-load VDD voltage, but full-load VDD voltage will be higher
resulting in initially higher ICE current during the unload-step transient condition. Because RFB3 is interposed
between VE and the FB input, the optocoupler transistor VCE varies considerably more as ICE varies and transient
response time is reduced. Capacitor CFB3 across RFB3 helps to improve the transient response again. The value
of CFB3 is estimated initially by equating the RFB3CFB3 time constant to 1 ms, and later is adjusted higher or lower
for optimal performance during prototype evaluation.
24
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
The optocoupler transistor-output current ICE is proportional to the optocoupler diode input current by its current
transfer ratio, CTR. Although many optocouplers are rated with nominal CTR between 50% and 600%, or are
ranked into narrower ranges, the actual CTR obtained at the low currents used with the UCC28740 falls around
5% to 15%. At full-load regulation, when IFB is near zero, VFB is still approximately 0.4 V and this sets a minimum
steady-state current for ICE through RFB4. After choosing an optocoupler, the designer must characterize its CTR
over the range of low output currents expected in this application, because optocoupler data sheets rarely
include such information. The actual CTR obtained is required to determine the diode input current range at the
secondary-side shunt-regulator.
Referring again to Figure 18, the shunt-regulator (typically a TL431) current must be at least 1 mA even when
almost no optocoupler diode current flows. Since even a near-zero diode current establishes a forward voltage,
ROPT is selected to provide the minimum 1-mA regulator bias current. The optocoupler input diode must be
characterized by the designer to obtain the actual forward voltage versus forward current at the low currents
expected. At the full-load condition of the converter, IFB is around 0.5 µA, ICE may be around (0.4 V / RFB4), and
CTR at this level is about 10%, so the diode current typically falls in the range of 25 µA to 100 µA. Typical optodiode forward voltage at this level is about 0.97 V which is applied across ROPT. If ROPT is set equal to 1 kΩ, this
provides 970 µA plus the diode current for IOPT.
As output load decreases, the voltage across the shunt-regulator also decreases to increase the current through
the optocoupler diode. This increases the diode forward voltage across ROPT. CTR at no-load (when ICE is
higher) is generally a few percent higher than CTR at full-load (when ICE is lower). At steady-state no-load
condition, the shunt-regulator current is maximized and can be estimated by Equation 30 and Equation 32.
IOPTNL, plus the sum of the leakage currents of all the components on the output of the converter, constitute the
total current required for use in Equation 7 to estimate secondary-side standby loss.
ICENL
VOPTNL
IOPTNL
CTRNL
ROPT
(32)
The shunt-regulator voltage can decrease to a minimum, saturated level of about 2 V. To prevent excessive
diode current, a series resistor, RTL, is added to limit IOPT to the maximum value necessary for regulation.
Equation 33 provides an estimated initial value for RTL, which may be adjusted for optimal limiting later during the
prototype evaluation process.
VOUTNL VOPTNL 2 V
RTL
IOPTNL
(33)
The output-voltage sense-network resistors RFB1 and RFB2 are calculated in the usual manner based on the
shunt-regulator reference voltage and input bias current. Having characterized the optocoupler at low currents
and determined the initial values of RFB1, RFB2, RFB3, RFB4, CFB3, ROPT and RTL using the above procedure, the
DC-bias states of the feedback network can be established for steady-state full-load and no-load conditions.
Adjustments of these initial values may be necessary to accommodate variations of the UCC28740, optocoupler,
and shunt-regulator parameters for optimal overall performance.
The shunt-regulator compensation network, ZFB, is determined using well-established design techniques for
control-loop stability. Typically, a type-II compensation network is used. The compensation design procedure is
beyond the scope of this datasheet.
8.2.3 Application Curves
The transient response shown in Figure 19 was taken with a 115 VAC, 60 Hz input voltage and a load transition
from 0 A to full load. Channel 1 is the load current on a scale of 1 A per division, channel 4 is the otutput voltage
on a scale of 1 V per division. The cursor shows the minimum acceptable voltage limit, 4.30 V, under transient
conditions. Also note that the output waveform was taken with the probe on TP5 with the ground referenced to
TP4 but not using the tip and barrel technique accounting for the high frequency noise seen on the waveform.
The typical switching waveform can be seen in Figure 20. Channel 1 shows the VS pin at 2 V per division and
channel 2 shows the MOSFET drain to source voltage at 100 V per division. The scan was taken at 1.8-A load,
115-VAC, 60-Hz input voltage. At this operating point, the switching frequency is dithering between 58.8 kHz and
52.6 kHz due to valley skipping.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
25
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
The UCC28740 controller employs a unique control mechanism to help with EMI compliance. As shown in
Figure 21, the DRV pin, shown as channel 3, drives the gate of the MOSFET with a sequence of pulses in which
there will be two longer pulses, two medium pulses, and two shorter pulses at any operating point starting with
the amplitude modulation mode. The EMI dithering is not enabled at light load. Figure x shows the result of these
varying pulse widths on the CS signal, shown on channel 4. The longer pulses result in a peak current threshold
of 808 mV, the medium length pulses are shown measured at 780 mV, and the shorter pulses measure a
threshold voltage of 752 mV. This dithering adds to the frequency jitter caused by valley skipping and results in a
spread spectrum for better EMI compliance.
115 VAC, 60 Hz
0 A to 2 A
CH 1 = Load Current, 1 A/DIV
CH 4 = VOUT, cursor shows minimum limit
CH 1 = VS
IOUT = 1.8 A
Figure 19. Transient Response
CH 2 = VDS
VIN = 115 VAC, 60 Hz
Figure 20. Switching Waveform
0.95
115 V, 60 Hz
230 V, 50 Hz
Efficiency
0.9
0.85
0.8
0.75
0.7
0
1
1.5
Load Current (A)
2
2.5
D005
Figure 22. Efficiency
Figure 21. EMI Dithering
26
0.5
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
0.82
0.815
0.81
0.805
0.8
0.795
0.79
0.785
0.78
0.775
0.77
0.765
0.76
0.755
0.75
80
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
20
18
16
Input Power (mW)
Efficiency
www.ti.com
14
12
10
8
6
4
2
110
140
170
200
Input Voltage (V AC)
230
0
85
260
Figure 23. Average Efficiency
6
100
90
Switching Frequency (kHz)
5
Output Voltage (V)
4.5
4
3.5
3
2.5
2
85 VAC, 60 Hz
115 VAC, 60 Hz
230 VAC, 50 Hz
265 VAC, 50 Hz
1
0.5
145
175
205
Input Voltage (VAC)
235
265
D003
Figure 24. No Load Power Consumption
5.5
1.5
115
D004
120 VDC
163 VDC
325 VDC
375 VDC
80
70
60
50
40
30
20
10
0
0
0
0.5
1
1.5
Load Current (A)
2
2.5
0
0.3
0.6
0.9
1.2
Load Current (A)
D002
Figure 25. VOUT vs. IOUT
1.5
1.8
2.1
D001
Figure 26. Control Law
60
200
Gain (dB)
Phase (degrees)
100
0
0
-30
-60
10
Phase (q)
Gain (dB)
30
-100
100
1000
Frequency (Hz)
VIN = 115 VAC
-200
10000
g6_b
IOUT = 2 A
Figure 27. Bode Plot
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
27
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
9 Power Supply Recommendations
The UCC28740 is designed to be used with a Universal AC input, from 85 VAC to 265 VAC, at 47 Hz to 63 Hz.
Other input line conditions can be used provided the HV pin can be set up to provide 500 µA to charge the VDD
capacitor for start-up through the internal startup switch. Once the VDD reaches the 21-V UVLO turnon
threshold, the VDD rail should be kept within the limits of the Bias Supply Input section of the Electrical
Characteristics table. To avoid the possibility that the device might stop switching, VDD must not be allowed to
fall below the UVLO VVDD(off) range.
10 Layout
10.1 Layout Guidelines
In general, try to keep all high current loops as short as possible. Keep all high current/high frequency traces
away from other traces in the design. If necessary, high frequency/high current traces should be perpendicular to
signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up.
Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.
10.1.1 VDD Pin
The VDD pin must be decoupled to GND with good quality, low ESR, low ESL ceramic bypass capacitors with
short traces to the VDD and GND pins. The value of the required capacitance on VDD is determined as shown in
the Application and Implementation section.
10.1.2 VS Pin
The trace between the resistor divider and the VS pin should be as short as possible to reduce/eliminate possible
EMI coupling. The lower resistor of the resistor divider network connected to the VS pin should be returned to
GND with short traces. Avoid adding any external capacitance to the VS pin so that there is no delay of signal;
added capacitance would interfere with the accurate sensing of the timing information used to achieve valley
switching and also control the duty cycle of the transformer secondary current.
10.1.3 FB Pin
The PCB tracks from the opto-coupler to the FB pin should have minimal loop area. If possible, it is
recommended to provide screening for the FB trace with ground planes. A resistor to GND from the FB pin is
recommended to speed up the turnoff time of the opto-coupler during a heavy load step transient. This resistor
should be placed as close as possible to FB and GND with short traces, the value of this resistor, RFB4, is
detailed in the Application and Implementation section.
10.1.4 GND Pin
The GND pin is the power and signal ground connection for the controller. As with all PWM controllers, the
effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Place all
decoupling and filter capacitors as close as possible to the device pins with short traces. The IC ground and
power ground should meet at the bulk capacitor’s return. Try to ensure that high frequency/high current from the
power stage does not go through the signal ground.
10.1.5 CS Pin
A small filter capacitor may be placed on CS to GND, with short traces, to filter any ringing that may be present
at light load conditions when driving MOSFETs with large gate capacitance. This capacitor may not be required
in all designs; however, it is wise to put a place holder for it in your designs. The current sense resistor should be
returned to the ground terminal of the input bulk capacitor to minimize the loop area containing the input
capacitor, the transformer, the MOSFET, and the current sense resistor.
10.1.6 DRV Pin
The track connected to DRV carries high dv/dt signals. Minimize noise pickup by routing the trace to this pin as
far away as possible from tracks connected to the device signal inputs, FB and VS. There is no requirement for a
Gate to Source resistor with this device.
28
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Layout Guidelines (continued)
10.1.7 HV Pin
Sufficient PCB trace spacing must be given between the high-voltage connections and any low-voltage nets. The
HV pin may be connected directly, or through series resistance, to the rectified high voltage input rail.
10.2 Layout Example
CVDD
2
VS
3
FB
4
GND
HV
8
DRV
6
CS
5
MOSFET
VDD
RFB4
RLC
RCS
CFB
RFB
RS2
RS1
1
CCS
CCININ
Figure 28. Layout Example Schematic
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
29
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For design tools see the UCC28740 Design Calculator
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28740 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Device Nomenclature
11.1.2.1 Capacitance Terms in Farads
CBULK
The total input capacitance of CB1 and CB2.
CVDD
The minimum required capacitance on the VDD pin.
COUT
The minimum output capacitance required.
11.1.2.2 Duty Cycle Terms
DMAGCC
The secondary diode conduction duty-cycle limit in CC mode, 0.425.
DMAX
MOSFET on-time duty-cycle.
11.1.2.3 Frequency Terms in Hertz
fLINE
The minimum input-line frequency.
fMAX
The target full-load maximum switching frequency of the converter.
fMIN
The steady-state minimum switching frequency of the converter.
fSW(min)
The minimum possible switching frequency (see Electrical Characteristics).
11.1.2.4 Current Terms in Amperes
IOCC
The converter output constant-current target.
IPP(max)
The maximum transformer primary peak current.
ISTART
The startup bias-supply current (see Electrical Characteristics).
ITRAN
The required positive load-step current.
IVSL(run)
The VS-pin run current (see Electrical Characteristics).
11.1.2.5 Current and Voltage Scaling Terms
KAM
30
The maximum-to-minimum peak primary current ratio (see Electrical Characteristics).
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Device Support (continued)
KLC
The current-scaling constant for line compensation(see Electrical Characteristics).
11.1.2.6 Transformer Terms
LP
The transformer primary inductance.
NAS
The transformer auxiliary-to-secondary turns-ratio.
NPA
The transformer primary-to-auxiliary turns-ratio.
NPS
The transformer primary-to-secondary turns-ratio.
11.1.2.7 Power Terms in Watts
PIN
The converter maximum input power.
POUT
The full-load output power of the converter.
PSB
The total standby power.
11.1.2.8 Resistance Terms in Ohms
RCS
The primary peak-current programming resistance.
RESR
The total ESR of the output capacitor(s).
RPL
The preload resistance on the output of the converter.
RS1
The high-side VS-pin sense resistance.
RS2
The low-side VS-pin sense resistance.
11.1.2.9 Timing Terms in Seconds
tD
The total current-sense delay including MOSFET-turnoff delay; add 50 ns to MOSFET delay.
tDM(min)
The minimum secondary rectifier conduction time.
tON(min)
The minimum MOSFET on time.
tR
The resonant frequency during the DCM dead time.
tRESP
The maximum response time of the voltage-regulation control-loop to the maximum required loadstep.
11.1.2.10 Voltage Terms in Volts
VBLK
The highest bulk-capacitor voltage for standby power measurement.
VBULK(min)
The minimum valley voltage on CB1 and CB2 at full power.
VCCR
The constant-current regulation factor (see Electrical Characteristics).
VCST(max)
The CS-pin maximum current-sense threshold (see Electrical Characteristics).
VCST(min)
The CS-pin minimum current-sense threshold (see Electrical Characteristics).
VVDD(off)
The UVLO turnoff voltage (see Electrical Characteristics).
VVDD(on)
The UVLO turnon voltage (see Electrical Characteristics).
VDSPK
The MOSFET drain-to-source peak voltage at high line.
VF
The secondary-rectifier forward-voltage drop at near-zero current.
VFA
The auxiliary-rectifier forward-voltage drop.
VLK
The estimated leakage-inductance energy reset voltage.
VOΔ
The output voltage drop allowed during the load-step transient in CV mode.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
31
UCC28740
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
www.ti.com
Device Support (continued)
VOCBC
The target cable-compensation voltage added to VOCV (provided by an external adjustment circuit
applied to the shunt-regulator). Set equal to 0 V if not used.
VOCC
The converter lowest output voltage target while in constant-current regulation.
VOCV
The regulated output voltage of the converter.
VOV
The maximum allowable peak output voltage.
VOVP
The overvoltage-detection level at the VS input (see Electrical Characteristics).
VREVA
The peak reverse voltage on the auxiliary rectifier.
VREVS
The peak reverse voltage on the secondary rectifier.
VRIPPLE
The output peak-to-peak ripple voltage at full-load.
11.1.2.11 AC Voltage Terms in VRMS
VIN(max)
The maximum input voltage to the converter.
VIN(min)
The minimum input voltage to the converter.
VIN(run)
The converter startup (run) input voltage.
11.1.2.12 Efficiency Terms
η
The converter overall efficiency at full-power output.
ηSB
The estimated efficiency of the converter at no-load condition, excluding startup resistance or bias
losses. For a 5-V USB-charger application, 60% to 65% is a good initial estimate.
ηXFMR
The transformer primary-to-secondary power-transfer efficiency.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• 12-W Ultra-Wide Input Range Power Supply
• 36-W, Universal Input, >90% Efficiency, Dual Output, Auxiliary Supply Reference Design for Server PSU
• 60-W, 24-V, High-Efficiency Industrial Power Supply With Precision Voltage, Current, and Power Limit
• Choosing Standard Recovery Diode or Ultra-Fast Diode in Snubber
• Control Challenges for Low Power AC/DC Converters
• Integrated 30-W Sensorless BLDC Motor Drive Retrofit Reference Design With 90- to 265-V AC Input
• Using the UCC28740EVM-525 10 W Constant- Voltage, Constant-Current Charger Adaptor Module
• 100-W, 24-V, High Efficiency, High PF, Industrial Power Supply With Precision Current and Power Limit
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
32
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
UCC28740
www.ti.com
SLUSBF3D – JULY 2013 – REVISED MARCH 2018
Community Resources (continued)
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: UCC28740
33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC28740D
ACTIVE
SOIC
D
7
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U28740
UCC28740DR
ACTIVE
SOIC
D
7
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
U28740
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
