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UCC28880
SLUSC05D – JULY 2014 – REVISED MAY 2016
UCC28880 700-V, 100-mA Low Quiescent Current Off-Line Converter
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
Integrated Power MOSFET (Switch) Rated to
700-V Drain-to-Source Voltage
Integrated High-Voltage Current Source for
Internal Low-Voltage Supply Generation
Soft Start
Self-Biased Switcher (Start Up and Operation
Directly from Rectified Mains Voltage)
Supports Buck, Buck-Boost and Flyback
Topologies
100 μs and cycle-by-cycle is
progressively reduced up to tOFF(min) providing soft start.
7.4.2 Feedback and Voltage Control Loop
The feedback circuit consists of a voltage comparator with the positive input connected to an internal reference
voltage (referenced to GND) and the negative input connected to FB pin. When the feedback voltage at the FB
pin is below the reference voltage VFB_TH logic high is generated at the comparator output. This logic high
triggers the PWM controller, which generates the PWM signal turning on the MOSFET. When the feedback
voltage at the FB pin is above the reference voltage, it indicates that the output voltage of the converter is above
the targeted output voltage set by the external feedback circuitry and PWM is stopped.
14
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Device Functional Modes (continued)
7.4.3 PWM Controller
UCC28880 operates under on/off control. When the FB pin voltage is below internal reference 1 V, the converter
is switching and sending power to the load. When the FB pin voltage is above internal reference 1 V, the
converter shuts off and stops delivering power to the load.
The PWM controller does not need a clock signal. The PWM signal’s frequency is set to fSW(max) = (1/(tON(max) +
tOFF(min))) which occurs when the voltage on the FB pin is continuously below VFB_TH.
PWM duty cycle is determined by both the peak current and maximum on time. At each switching cycle, after
turn on, the MOSFET is turned off if its current reaches the fixed peak-current threshold or its on time reaches
the maximum value of on-time pulse tON(max).
Normally the converter would operate under frequency control, which means the converter is only enabled one
switching cycle and then disabled. Next switching cycle starts when output voltage decays and the feedback
enable the converter again. This way, the converter appears to operate under variable switching frequency
control.
The user might observe the converter operates in burst mode that converter is enabled for multiple switching
cycles and then stopped for multiple switching cycles. This causes larger output voltage ripple. However, due to
the infrequent switching it actually helps on the standby power at no load.
VFB
VFB_TH
t
FB_COMP_OUT
t
PWM
t
CURRENT LIMIT
t
RSTN
t
GATE
t
tON(max)
tOFF(min)
tON(max)
tOFF(min)
tON(max)
tOFF(min)
tON(max)
tOFF(min)
Figure 13. UCC28880 Timing Diagram
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Device Functional Modes (continued)
7.4.4 Current Limit
The current limit circuit senses the current through the power MOSFET. The sensing circuit is located between
the source of the power MOSFET and the GND pin. When the current in the power MOSFET exceeds the
threshold ILIMIT, the internal current limit signal goes high, which sets the internal RSTN signal low. This disables
the power MOSFET by driving its gate low. The current limit signal is set back low after the falling edge of the
PWM signal. After the rising edge of the GATE signal, there is a blanking time. During this blanking time, the
current limit signal cannot go high. This blanking time and the internal propagation delay result in minimum on
time, tMIN.
7.4.5 Inductor Current Runaway Protection
To protect the device from overload conditions, including a short circuit at the output, the PWM controller
incorporates a protection feature which prevents the inductor current from runaway. When the output is shorted
the inductor demagnetization is very slow, low di/dt, and when the next switching cycle starts energy stored in
the inductance is still high. After the MOSFET switches on, the current starts to rise from pre-existing DC value
and reaches the current-limit value in a short duration of time. Because of the intrinsic minimum on-time of the
device the MOSFET on-time cannot be lower than tMIN, in an overload or output short circuit the energy
inductance is not discharged sufficiently during MOSFET off-time, it is possible to lose control of the current
leading to a runaway of the inductor current. To avoid this, if the on-time is less than tON_TO (tON_TO is a device
internal time out), the controller increases the MOSFET off-time (tOFF). If the MOSFET on-time is longer than
tON_TO then tOFF is decreased. The controller increases tOFF, cycle-by-cycle, through discrete steps until the ontime continues to stay below tON_TO. The tOFF is increased up to tOFF(ovl) after that, if the on-time is still below
tON_TO the off-time is kept equal to tOFF(ovl). The controller decreases tOFF cycle-by-cycle until the on-time
continues to stay above tON_TO up to tOFF(min). This mechanism prevents control loss of the inductor current and
prevents over stress of the MOSFET (see typical waveforms in Figure 14 and Figure 15). At start up, the tOFF is
set to tOFF(ovl) and reduced cycle-by-cycle (if the on-time is longer than tON_TO) up to tOFF(min) providing a soft start
for the power stage.
I LIMIT
Inductor Current
Drain Current
tON_ MAX
t
tOFF
PWM
t
Current Limit
t
LEB
~200 ns
~200 ns
t
tON_TO
tON_TO
tON_TO
t
Increase tOFF
( Decrease fSW )
Decrease tOFF
(Increase fSW )
CNT_IN
t
Gate
tON
tON
t
Figure 14. Current Runaway Protection Logic Timing Diagram
16
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Device Functional Modes (continued)
Output Shorted Here
VFB
VFB_TH
ILIMIT
INDUCTOR
CURRENT
DRAIN
CURRENT
t
tON_TO
t
GATE
tON_TO
tON_TO
tON < tON_TO
tON > tON_TO
tON_TO
tON < tON_TO
tON_TO
t
tON < tON_TO
Figure 15. Current Runaway Protection, Inductor and MOSFET Current
A minimal value needs to be imposed on the inductance value to avoid nuisance tripping of the protection feature
that prevents the loss of control of the inductor current. Inadvertent operation of the protection feature limits the
output-power capability of the converter. This condition depends on the converter's maximum input operating
voltage and temperature. Use Equation 1 to calculate your minimum inductance value.
ª§ L
·º
L ! «¨ MIN ¸ »
«¬© VIN ¹ »¼
TJ TJ(max)
u VIN(max)
VIN(max)
ILIMIT
u tON _ TO
(1)
The value of Equation 1 can be found by characterization graph of Figure 10. Pick the value at the desired
maximum junction temperature
If the inductance value is too low, such that the MOSFET on-time is always less than tON_TO timeout and the
device progressively increases the MOSFET off-time up to tOFF(ovl), the output power is reduced and the
converter fails to supply the load.
7.4.6 Thermal Shutdown
If the junction temperature rises above TJ(stop), the thermal shutdown is triggered. This disables the power
MOSFET switching. To re-enable the switching of the MOSFET the junction temperature has to fall by TJ(hyst)
below the TJ(stop) where the device moves out of over temperature.
According to the electrical specs, the thermal shutdown threshold can be beyond the device's rated absolute
maximum junction temperature. Thermal shutdown is designed to prevent thermal run away that could result in
catastrophic failure. Prolonged operation above the recommended maximum junction temperature can impact
device lifetime.
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8 Application and Implementation
8.1 Application Information
The UCC28880 can be used in various application topologies with direct or isolated feedback. The device can be
used in low-side buck, where the output voltage is negative, or as a low-side buck-boost configuration, where the
output voltage is positive. In both configurations the common reference node is the positive input node (VIN+).
The device can also be configured as a LED driver in either of the above mentioned configurations. If the
application requires the AC-to-DC power supply output to be referenced to the negative input node (VIN-), the
UCC28880 can also be configured as a traditional high-side buck as shown in Figure 19. In this configuration,
the voltage feedback is sampling the output voltage VOUT, making the DC regulation less accurate and load
dependent than in low-side buck configuration, where the feedback is always tracking the VOUT. However, highconversion efficiency can still be obtained.
8.2 Typical Application
8.2.1 12-V, 100-mA Low-Side Buck Converter
Figure 16 shows a typical application example of a non-isolated power supply, where the UCC28880 is
connected in a low-side buck configuration having an output voltage that is negative with respect to the positive
input voltage (VIN+). The output voltage is set to 12 V in this example, but can easily be changed by changing
the value of RFB1. This application can be used for a wide variety of household appliances and automation, or
any other applications where mains isolation is not required.
RF
10
L2
1 mH
D2
1N4937
C2
4.7 PF
400 V
HVIN
C1
4.7 PF
400 V
VDD
RFB1
590 k:
+/- 1%
D1
600 V
tRR ”35 ns
L1
2.2 mH
330 mA
+
CL
4.7 PF
16 V
RL
402 k:
Q1
500 V
VOUT
12 V
100 mA
-
DRAIN
UCC28880
AC
(115 V/230 V)
CVDD
100 nF
10 V
FB
GND
RFB2
51 k:
+/- 1%
D3
1N4007
Figure 16. Universal Input, 12-V, 100-mA Output Low-Side Buck
8.2.1.1 Design Requirements
Table 2. Design Specification
DESCRIPTION
MIN
MAX
UNIT
DESIGN INPUT
VIN
AC input voltage
85
265
VRMS
fLINE
Line frequency
47
63
Hz
IOUT
Output current
0
100
mA
50
mW
DESIGN REQUIREMENTS
PNL
No-load input power
VOUT
Output voltage
ΔVOUT
Output voltage ripple
η
Converter efficiency
18
12
13
V
350
mV
68%
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the UCC28880 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
8.2.1.2.2 Input Stage (RF, D2, D3, C1, C2, L2)
•
•
•
Resistor RF is a flame-proof fusible resistor. RF limits the inrush current, and also provide protection in case
any component failure causes a short circuit. Value for its resistance is generally selected between 4.7 Ω to
15 Ω.
A half-wave rectifier is chosen and implemented by diode D2 (1N4937). It is a general purpose 1-A, 600-V
rated diode. It has a fast reverse recovery time (200 ns) for improved differential-mode-conducted EMI noise
performance. Diode D3 (1N4007) is a general purpose 1-A, 1-kV rated diode with standard reverse recovery
time (>500 ns), and is added for improved common-mode-conducted EMI noise performance. D3 can be
removed and replaced by a short if not needed.
EMI filtering is implemented by using a single differential-stage filter (C1-L2-C2).
Capacitors C1 and C2 in the EMI filter also acts as storage capacitors for the high-voltage input DC voltage
(VIN). The required input capacitor size can be calculated according Equation 2.
-° 1
§ VBULK(min) · ½°
2 u PIN
1
¸¾
u®
u arccos ¨
¨ 2 u VIN(min) ¸ °
fLINE(min) ° RCT 2 u S
©
¹¿
¯
CBULK min
2
2
2 u VIN(min)
VBULK(min)
where
•
•
•
•
•
•
CBULK(min) is minimum value for the total input capacitor value (C1 + C2 in the schematic of Figure 16).
RCT = 1 in case a half wave rectifier and RCT = 2 in case of full-wave rectifier (for the schematic reported in
Figure 22 RCT = 1 because of a half-wave rectifier).
PIN is the converter input power.
VIN(min) is the minimum RMS value of the AC input voltage.
VBULK(min) is the minimum allowed voltage value across bulk capacitor during converter operation.
fLINE(min) is the minimum line frequency when the line voltage is VIN(min).
The converter input power can be easily calculated as follow:
•
•
The converter maximum output power is: POUT = IOUT x VOUT = 0.1 A x 12.5 V = 1.25 W
Assuming the efficiency η = 68.% the input power is PIN = POUT/η = 1.765 W
Using the following values for the other parameters
•
•
•
VBULK(min) = 80 V
VIN(min) = 85 VRMS (from design specification table)
fLINE(min) = 57 Hz
(2)
CBULK(min) = 6.96 μF. Considering that electrolytic capacitors, generally used as bulk capacitor, have 20% of
tolerance in value, the minimum nominal value required for CBULK is:
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CBULKn(min) !
CBULK(min)
1 TOLCBULK
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8.7 PF
(3)
Select C1 and C2 to be 4.7 μF each (CBULK = 4.7 μF + 4.7 μF = 9.4 μF > CBULKn(min)).
By using a full-wave rectifier allows a smaller capacitor for C1 and C2, almost 50% smaller.
8.2.1.2.3 Regulator Capacitor (CVDD)
Capacitor CVDD acts as the decoupling capacitor and storage capacitor for the internal regulator. A 100-nF, 10-V
rated ceramic capacitor is enough for proper operation of the device's internal LDO.
20
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8.2.1.2.4 Freewheeling Diode (D1)
The freewheeling diode has to be rated for high-voltage with as short as possible reverse-recovery time (trr).
The maximum reverse voltage that the diode should experience in the application, during normal operation, is
given by Equation 4.
VD1(max)
2 u VIN(max)
2 u 265V 375V
(4)
A margin of 20% is generally considered.
The use of a fast recovery diode is required for the buck-freewheeling rectifier. When designed in CCM, the
diode reverse recovery time should be less than 35 ns to keep low reverse recovery current and the switching
loss. For example, STTH1R06A provides 25-ns reverse recovery time. When designed in DCM, slower diode can
be used, but the reverse recovery time should be kept less than 75 ns. MURS160 can fit the requirement.
8.2.1.2.5 Output Capacitor (CL)
The value of the output capacitor impacts the output ripple. Depending on the combination of capacitor value and
equivalent series resistor (RESR). A larger capacitor value also has an impact on the start-up time. For a typical
application, the capacitor value can start from 47 μF, to hundreds of μF. A guide for sizing the capacitor value
can be calculated by the following equations:
ILIMIT IOUT
260mA 100mA
CL ! 4 u
4u
30 PF
fSW(max) u 'VOUT
350mV u 66kHz
(5)
RESR
'VOUT
ILIMIT
1:
(6)
Take into account that both CL and RESR contribute to output voltage ripple. A first pass capacitance value can be
selected and the contribution of CL and RESR to the output voltage ripple can be evaluated. If the total ripple is
too high the capacitance value has to increase or RESR value must be reduced. In the application example CL
was selected (47 µF) and it has an RESR of 0.3 Ω. So the RESR contributes for 1/3 of the total ripple. The formula
that calculates CL is based on the assumption that the converter operates in burst of four switching cycles. The
number of bursts per cycle could be different, the formula for CL is a first approximation.
8.2.1.2.6 Load Resistor (RL)
The resistor should be chosen so that the output current in any standby/no-load condition is higher than the
leakage current through the integrated power MOSFET. If the standby load current is ensured to always be
larger than the specified ILEAKAGE, the RL is not needed. If OVP protection is required for safety reasons, then a
zener could be placed across the output (not fitted in the application example). In the application example RL =
402 kΩ. This ensures a minimum load current of at least ~30 µA when VOUT = 12 V.
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8.2.1.2.7 Inductor (L1)
Initial calculations:
Half of the peak-to-peak ripple current at full load:
'IL 2 u ILIMIT IOUT
(7)
When operating in DCM, the peak-to-peak current ripple is the peak current of the device.
Average MOSFET conduction minimum duty cycle at continuous conduction mode is:
VOUT Vd
DMIN
VIN(max) Vd
(8)
If the converter operates in discontinuous conduction mode:
I
VOUT Vd
DMIN 2 u OUT
ILIMIT VIN(max) Vd
(9)
Maximum allowed switching frequency at VIN(max) and full load:
DMIN
FSW _ VIN(max)
tON _ TO
(10)
Switching frequency has a maximum value limit of fSW(max).
The worst case ILIMIT = 140 mA, but assuming ΔIL = 100 mA.
The converter works in continuous conduction mode (ΔIL < ILIMIT) so the
VOUT Vd
DMIN
3.61%
VIN(max) Vd
(11)
The maximum allowed switching frequency is 61.7 kHz because the calculated value exceeds it.
DMIN
FSW _ VIN(max)
72kHz ! fSW(max) 61.7kHz
tON _ TO
(12)
The duty cycle does not force the MOSFET on time to go below tON_TO. If DMIN/TON_TO < fSW(max), the switching
frequency is reduced by current runaway protection and the maximum average switching frequency is lower than
fSW(max), the converter can't support full load.
The minimum inductance value satisfies both the following conditions:
VOUT Vd
L1 !
2mH
'IL u FSW _ VIN(max)
ª§ L
·º
L ! «¨ MIN ¸ »
¬«© VIN ¹ ¼»
TJ TJ(max)
u VIN(max)
2.65
PH
u 375 V # 1 mH
V
(13)
(14)
In the application example, 2.2 mH is selected as the minimum standard value that satisfy Equation 13 and
Equation 14. The value of Equation 14 can be found by characterization graph of Figure 10. Pick the value at the
desired maximum junction temperature.
22
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8.2.1.2.8 Feedback Path (Q1, RFB1, RFB2)
The feedback path of Q1, RFB1 and RFB2 implements a level-shifted direct feedback. RFB2 sets the current
through the feedback path, and RFB1 sets the output voltage. Q1 acts as the level shifter and needs to be rated
for high voltage. The output voltage is determined as follows:
R
VOUT VFB _ TH u FB1 VBE
RFB2
where
•
•
•
•
•
VOUT is the output voltage.
VFB_TH is the FB pin voltage threshold = VFB_TH.
VBE is the base-emitter saturation voltage of the external PNP transistor.
RFB1 is the external resistor setting the output voltage (depending on the current set by RFB2, and the Vbe).
RFB2 is the external resistor setting the current through the external feedback path.
(15)
For the application example a target of ~20-μA of current is selected through the external feedback path (IFB).
VFB _ TH
1.0 V
RFB2
50k:
IFB
| 20 PA
(16)
Choose a standard resistor size for RFB2 = 51 kΩ. For the high-voltage PNP transistor choose a 500-V rated
transistor with a VBE ≈ 0.5 V for the feedback current. To achieve the 12-V output voltage RFB1 needs to be:
V OUT VBE
12 V 0.5 V
RFB1
u RFB2
u 51 k: 586k:
VFB _ TH
1V
(17)
Choose a standard resistor size for RFB1 = 591 kΩ.
To change the output voltage, change the value for RFB1. For example, to target a 5-V output voltage, RFB1
should be changed to a 230-kΩ resistor.
Accuracy of the output-voltage level depends proportionally on the variation of VFB_TH, and on the absolute
accuracy of VBE according to Equation 16 and Equation 17.
The current through the feedback path is connected over the high voltage input (VIN), and this feedback current
is always on. Higher current provides less noise-sensitive feedback, the feedback current should be minimized in
order to minimize the total power consumption.
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8.2.1.3 Application Curves
Figure 17 shows the efficiency diagram of the converter, a design previous discussed. Figure 18 shows the
output voltage vs output current diagram. The two diagrams were obtained by measuring efficiency (Figure 17),
output current and output voltage (Figure 18) moving resistive load value from infinite (load disconnected) up to
zero (output shorted). The different curves of the diagram correspond to different AC input voltage.
14
90
80
85 V
115 V
230 V
265 V
12
Output Voltage (V)
Efficiency (%)
70
60
50
40
30
85 V
115 V
230 V
265 V
20
10
10
8
6
4
2
0
0
0
0.5
1
1.5
Output Power (W)
2
2.5
0
0.05
D016
Figure 17. Efficiency vs Output Power Diagrams
0.1
0.15
Ouput Current (A)
0.2
0.25
D017
Figure 18. Output Voltage vs Output Current Diagram
Table 3 shows converter efficiency. Table 4 shows the converter input power in no-load conditions and output
shorted conditions. The no-load condition shows the converter stand-by performance.
Table 3. Converter Efficiency
VIN_AC (VRMS)
115
230
LOAD (mA)
EFFICIENCY (%)
25
80.3
50
81.4
75
81.6
100
81.9
25
78.5
50
81.1
75
82.1
100
82.7
AVERAGE EFFICIENCY (%)
81.3
81.2
Table 4. No-Load and Output-Shorted Converter Input Power
VIN (VRMS)
24
NO LOAD PIN (mW)
OUTPUT SHORTED PIN (mW)
OUTPUT SHORTED IOUT (mA)
85
16
453
214
115
19.5
435
213
140
22.5
417
211
170
26
443
213
230
33
430
209
265
37.5
344
182
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8.2.2 12-V, 100-mA, High-Side Buck Converter
Figure 19 shows a typical application example of a non-isolated power supply, where the UCC28880 is
connected in a high-side buck configuration having an output voltage that is positive with respect to the negative
high-voltage input (VIN-).
RF
L2
D2
HVIN
VDD
UCC28880
CVDD
C1
+
DRAIN
RFB1
FB
VIN
C2
-
GND
CFB
RFB2
D4
L1
CL
D1
D3
RL
+
VOUT
-
Figure 19. High-Side Buck Converter Schematic
8.2.2.1 Design Requirements
Table 5. Design specification
DESCRIPTION
MIN
MAX
UNIT
DESIGN INPUT
VIN
AC input Voltage
85
265
fLINE
Line frequency
47
63
VRMS
Hz
IOUT
Output current
0
100
mA
50
mW
14
V
250
mV
DESIGN REQUIREMENTS
PNL
No-load input power
VOUT
Output voltage
ΔVOUT
Output voltage ripple
η
Converter efficiency
12
68%
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8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Introduction
The low-side buck converter and high-side buck converter design procedures are very similar.
8.2.2.2.2 Feedback Path (CFB, RFB1 and RFB2) and Load Resistor (RL)
In low-side buck converter the output voltage is always sensed by the FB pin and UCC28880 internal controller
can turn on the MOSFET on VOUT. In high-side buck converter applications the information on the output
voltage value is stored on CFB capacitor. This information is not updated in real time. The information on CFB
capacitor is updated just after MOSFET turn-off event. When the MOSFET is turned off, the inductor current
forces the freewheeling diode (D1 in Figure 19) to turn on and the GND pin of UCC28880 goes negative at -Vd1
(where Vd1 is the forward drop voltage of diode D1) with respect to the negative terminal of bulk capacitor (C1 in
Figure 19). When D1 is on, through diode D4, the CFB capacitor is charged at VOUT – Vd4 + Vd1. Set the output
voltage regulation level using Equation 18.
RFB1 VOUT(T) Vd4 Vd1 VFB _ TH VOUT(T) VFB _ TH
#
RFB2
VFB _ TH
VFB _ TH
where
•
•
•
•
•
WFB
VFB_TH is the FB pin reference voltage.
VOUT_T is the target output voltage.
RFB1, RFB2 is the resistance of the resistor divider connected with FB pin (see Figure 19)
The capacitor CFB after D1 is discharged with a time constant that is τfb = CFB x (RFB1 + RFB2 ).
Select the time constant τFB, given in Equation 19
CFB u RFB1 RFB2
1
#
u CL u RL
10
(18)
(19)
The time constant selection leads to a slight output-voltage increase in no-load or light-load conditions. In order
to reduce the output-voltage increase, increase τFB. The drawback of increasing τFB is t in high-load conditions
VOUT could drop.
26
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8.2.2.3 Application Curves
Figure 20 shows the output voltage vs output current. Different plots correspond to different converter AC input
voltages. Figure 21 shows efficiency changes vs output power. Different plots correspond to different converter
AC input voltages.
14
10
Efficiency (%)
Output Voltage (V)
12
8
6
4
85 V
115 V
230 V
265 V
2
0
0
0.025 0.05 0.075 0.1 0.125 0.15 0.175
Output Current (A)
0.2
0.225
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
85 V
115 V
230 V
265 V
0
0.25
0.5
D018
Figure 20. Output IV Characteristic
0.75
1
1.25 1.5
Output Power (W)
1.75
2
2.25
D020
Figure 21. Efficiency vs POUT
Table 6. Converter Efficiency
VIN_AC (VRMS)
LOAD (mA)
EFFICIENCY (%)
AVERAGE EFFICIENCY (%)
115
25
75.2
76.8
50
77.1
230
75
77.6
100
77.7
25
72.6
50
75.1
75
75.7
100
76.3
74.8
Table 7. No-Load and Output Shorted Converter Input Power
VIN (VRMS)
NO LOAD PIN (mW)
OUTPUT SHORTED PIN (mW)
OUTPUT SHORTED IOUT (mA)
85
31
415
212
115
34
399
209
140
36
414
211
170
38
401
208
230
44
394
195
265
47
333
174
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8.2.3 Additional UCC28880 Application Topologies
8.2.3.1 Low-Side Buck and LED Driver – Direct Feedback (Level Shifted)
Features include:
• Output Referenced to Input
• Negative Output (VOUT) with Respect to VIN+
• Step Down: VOUT < VIN
• Direct Level-Shifted Feedback
RFB1
D1
+
CL
+
VDD
VIN
-
Q1
L1
HVIN
VOUT
DRAIN
UCC28880
FB
GND
RFB2
Figure 22. Low-Side Buck, Direct Feedback (Level Shifted)
RSENSE
C1
R2
D1
RFB1
CL
R1
Q2
+
Current Feedback
VIN
-
L1
HVIN
VDD
VOUT
DRAIN
Q1
UCC28880
FB
GND
RFB1
Figure 23. Low-Side Buck LED Driver, Direct Feedback (Level Shifted) image.
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8.2.3.2 12-V, 100-mA High-Side Buck Converter
Features include:
• Output Referenced to Input
• Positive Output (V ) with Respect to VIN• Step Down (VOUT < VIN)
HVIN
VDD
+
DRAIN
UCC28880
VIN
FB
-
10
GND
D2
CFB
RFB2
L1
+
CL
D1
VOUT
-
Figure 24. High-Side Buck Converter Schematic
8.2.3.3 Non-Isolated, Low-Side Buck-Boost Converter
Features Include:
• Output Referenced to Input
• Positive Output (VOUT) with Respect to VIN+
• Step Up, Step Down: VOUT VIN
• Direct Level-Shifted Feedback
CL
VOUT
D1
VDD
+
VIN
-
-
L1
HVIN
+
DRAIN
UCC28880
FB
GND
RFB2
Figure 25. Low-Side Buck-Boost Converter
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8.2.3.4 Non-Isolated, High-Side Buck-Boost Converter
Features include:
• Output Referenced to Input
• Positive Output (VOUT) with Respect to VIN• Step Up, Step Down: VOUT VIN
HVIN
VDD
DRAIN
UCC28880
+
FB
VIN
RFB1
GND
-
CFB
RFB2
D1
D2
+
VOUT
-
CL
L1
Figure 26. High-Side Buck-Boost Converter
8.2.3.5 Non-Isolated Flyback Converter
Features include:
• Output Referenced to Input
• Positive Output (VOUT) with Respect VIN• Direct Feedback
RFB2
RFB1
CL
HVIN
+
VDD
VIN
-
+
VOUT
-
DRAIN
UCC28880
CVDD
FB
GND
RFB2
Figure 27. Non-Isolated Flyback Configuration
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8.2.3.6 Isolated Flyback Converter
Features include:
• Output Isolated from Input
• Direct Feedback
RFB2
CL
HVIN
+
VDD
VIN
-
+
VOUT
-
DRAIN
UCC28880
CVDD
FB
GND
RFB
Figure 28. Isolated Flyback Converter
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9 Power Supply Recommendations
The VDD capacitor recommended value is 100 nF to ensure high-phase margin of the internal 5-V regulator and
it should be placed close to VDD pin and GND pins to minimize the series resistance and inductance.
The VDD pin provides a regulated 5-V output but it is not intended as a supply for external load. Do not supply
VDD pin with external voltage source (for example the auxiliary winding of flyback converter).
Always keep GND pin 1 and GND pin 2 connected together with the shortest possible connection.
10 Layout
10.1 Layout Guidelines
•
•
•
•
In both buck and buck-boost low-side configurations, the copper area of the switching node DRAIN should be
minimized to reduce EMI.
Similarly, the copper area of the FB pin should be minimized to reduce coupling to feedback path. Loop CL,
Q1, RFB1 should be minimized to reduce coupling to feedback path.
In high-side buck and buck boost the GND, VDD and FB pins are all part of the switching node so the copper
area connected with these pins should be optimized. Large copper area allows better thermal management,
but it causes more common mode EMI noise. Use the minimum copper area that is required to handle the
thermal dissipation.
Minimum distance between 700-V coated traces is 1.41 mm (60 mils).
10.2 Layout Example
Figure 29 shows and example PCB layout for UCC28880 in low-side buck configuration.
L2
D2
RF
C1
C2
D3
60 mils
AC
INPUT
GND
DRAIN
L1
GND
D1
FB
NC
HVIN
VDD
VDD
RFB2
RFB1
Q1
= top layer
CL
= bottom layer
RL
= connect top and bot
DC
OUTPUT
Figure 29. UCC28880 Layout Example
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SLUSC05D – JULY 2014 – REVISED MAY 2016
11 Device and Documentation Support
11.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the UCC28880 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Trademarks
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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33
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC28880D
ACTIVE
SOIC
D
7
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28880
UCC28880DR
ACTIVE
SOIC
D
7
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28880
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28880DR
Package Package Pins
Type Drawing
SOIC
D
7
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28880DR
SOIC
D
7
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0007A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
8
1
.100
[2.54]
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X .050
[1.27]
4
5
B
7X .012-.020
[0.31-0.51]
.010 [0.25]
.150-.157
[3.81-3.98]
NOTE 4
C A B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4220728/A 01/2018
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0007A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
7X (.024)
[0.6]
4X (.050 )
[1.27]
SYMM
(.100 )
[2.54]
5
4
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220728/A 01/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0007A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7X (.061 )
[1.55]
SYMM
1
8
7X (.024)
[0.6]
4X (.050 )
[1.27]
SYMM
(.100 )
[2.54]
5
4
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4220728/A 01/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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