SLUS542F − OCTOBER 2003 − REVISED JULY 2009
FEATURES
D Low Output Jitter
D Soft−Stop Shutdown of MAIN and AUX
D Ideal for Active Clamp/Reset Forward,
D
D
D
D
D
D
D
D
D
DESCRIPTION
The UCC2891/2/3/4 family of PWM controllers is
designed to simplify implementation of the various
active clamp/reset switching power topologies.
Flyback Converters
Provides Complementary Auxiliary Driver
with Programmable Deadtime (Turn-On
Delay) between AUX and MAIN Switches
Peak Current-Mode Control with
Cycle-by-Cycle Current Limiting
110-V Input Startup Regulator on UCC2891/3
TrueDrivet 2-A Sink, 2-A Source Outputs
Accurate Line UV and Line OV Threshold
Programmable Slope Compensation
1.0-MHz Synchronizable Oscillator
Precise Programmable Maximum Duty Cycle
Programmable Soft Start
The UCC289x is a peak current-mode, fixedfrequency, high-performance pulse width modulator.
It includes the logic and the drive capability for the
auxiliary switch with a simple method of
programming the critical delays for proper active
clamp operation.
The UCC2891/3 includes a 110-V start-up
regulator for initial start-up and to provide
keep-alive power during stand-by.
Additional features include an internal
programmable slope compensation circuit,
precise DMAX limit, and a single resistor
programmable synchronizable oscillator. An
accurate line monitoring function also programs
the converter’s ON and OFF transitions with
regard to the bulk input voltage. Along with the
UCC2897, this UCC289x family allows the power
supply designer to eliminate many of the external
components, reducing the size and complexity of
the design.
APPLICATIONS
D 150-W to 700-W SMPS
D High-Efficiency, Low EMI/RFI Off-Line or
D
D
DC/DC Converters
Server, 48-V Telecom, Datacom
High Power Adapter, LCD-TV and PDP-TV
R DEL
1
UCC2891
VIN
RDEL
BIAS
WINDING
2
RTON
3
RTOFF
LINE UV
15
VDD
14
R OFF
4
VREF
OUT
SYNC
6
GND
7
CS
8
RSLOPE
AUX
12
PGND
11
SS/SD
FB
D3
10
C CLAMP
C AUX
Q2
Co
LOAD
D1
D2
Q3
SR
DRIVE
R CS
C SS
D AUX
SECONDARY
SIDE E/A
9
R SLOPE
D4
Q1
R OUT
13
C VREF
5
C BIAS
Lo
Q4
C BULK
R ON
CF
+VIN
16
RF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
Copyright 2003 − 2009, Texas Instruments Incorporated
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1
SLUS542F − OCTOBER 2003 − REVISED JULY 2009
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Line input voltage, VIN
Supply voltage, VDD
(IDD < 10 mA)
Analog inputs
FB, CS, SYNC, LINEOV, LINEUV
Output source current (peak), IO_SOURCE
Output sink current (peak), IO_SINK
120
V
16.5
V
−0.3 to (VREF + 0.3)
not to exceed 6
V
2.5
OUT, AUX
Operating junction temperature range, TJ
−55 to 150
Storage temperature, Tstg
−65 to 150
ESD rating
A
−2.5
Human body model, (HBM)
2000
Change device model (CDM)
500
°C
V
Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into and negative out of, the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
Line input voltage, VIN
18
Supply voltage, VDD
8.5
Supply bypass capacitance
NOM
12.0
MAX
UNIT
110
V
16.0
V
µF
1
Timing resistance, RON = ROFF (for 250-kHz
operation)
75
kΩ
Operating junction temperature, TJ
−40
105
°C
Reference bypass capacitance, CREF
0.1
1
µF
ORDERING INFORMATION
PART NUMBERS
TA
APPLICATION
AUX
OUTPUT
POLARITY
DC−DC
DC-DC/Sec. Side
−40°C to 125°C
P-Channel
DC−DC
Off−Line
N-Channel
CS
THRESHOLD
(INCLUDES
SLOPE COMPENSATION)
110-V START-UP
CIRCUIT
SOIC−16
(D)
TSSOP−16
(PW)
0.75 V
Yes
UCC2891D
UCC2891PW
1.27 V
No
UCC2892D
UCC2892PW
0.75 V
Yes
UCC2893D
UCC2893PW
1.27 V
No
UCC2894D
UCC2894PW
† The D and PW packages are available taped and reeled. Add R suffix to device type (e.g. UCC2891DR) to order quantities of 2,500
devices per reel (for the D package) and 2,000 devices per reel (for the PW package). Bulk quantities are 40 units per tube (for the D
package) and 90 units per tube (for the PW package).
2
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
THERMAL RESISTANCE INFORMATION
PACKAGE
THERMAL RESISTANCE
SOIC−16 (D)
TSSOP−16 (PW)
θjc
36.9 to 38.4
θja (0 LFM)
73.1 to 111.6
θjc
33.6 to 35.0
θja (0 LFM)
108.4 to 147.0
UNITS
°C/W
°C/W
PIN ASSIGNMENTS
UCC2892 AND UCC2894
D AND PW PACKAGE
(TOP VIEW)
UCC2891 AND UCC2893
D and PW PACKAGEs
(TOP VIEW)
RTDEL
RTON
RTOFF
VREF
SYNC
GND
CS
RSLOPE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RTDEL
RTON
RTOFF
VREF
SYNC
GND
CS
RSLOPE
VIN
LINEUV
VDD
OUT
AUX
PGND
SS/SD
FB
1
2
3
4
5
6
7
8
LINEOV
LINEUV
VDD
OUT
AUX
PGND
SS/SD
FB
16
15
14
13
12
11
10
9
ELECTRICAL CHARACTERISTICS
VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,
RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
ISTARTUP
Start-up current
IDD
Operating supply current(1)(2)
VDD < VUVLO
VFB = 0 V,
VCS = 0 V,
Outputs not switching
300
500
µA
2
3
mA
HIGH-VOLTAGE BIAS SECTION (UCC2891, UCC2893)
IDD−ST
VDD startup current
IVIN
JFET leakage current
UNDERVOLTAGE LOCKOUT
Current available from VDD during Startup, VIN = 36 V, TA = −40°C to 85°C (3)
4
11
VIN = 120 V; VDD = 14 V
Start threshold voltage(1)
mA
75
µA
12.2
12.7
13.2
Minimum operating voltage after start
7.6
8.0
8.4
Hysteresis
4.4
4.7
5.0
Line UV and Line OV voltage threshold
1.243
1.268
1.293
V
Line UV and Line OV hysteresis current
11.8
12.5
14.5
µA
V
LINE MONITOR
VLINEUV
ILINEHYS
SOFT-START
ISS
ISS
Charge current
Discharge current
RTON = 75 kΩ
RTON = 75 kΩ
−10.5
−18.5
10.5
18.5
µA
A
VSS/SD
Discharge/shutdown threshold voltage
0.4
0.5
0.6
V
(1) Set VDD above the start threshold before setting at 12 V.
(2) Does not include current of the external oscillator network.
(3) The power supply starts with IDD−ST load on VDD, part will start up with no load up to 125°C. For more detailed information, see pin descriptions
for VIN and VDD.
(4) ISSC and ISS/SD are directly proportional to IRON. See equation 7.
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3
SLUS542F − OCTOBER 2003 − REVISED JULY 2009
ELECTRICAL CHARACTERISTICS
VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,
RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Reference
VREF
TJ = 25°C
0 A < IREF < 5 mA,
4.85
5.00
5.15
4.75
5.00
5.25
−20
−11
−8
FB = High
-10%
R CS
R SLOPE
+10%
Oscillator frequency
TJ = 25°C
237
250
263
Total variation
−40 °C < TJ 125°C; 8.5 V < 14.5 V
225
Reference voltage
ISC
Short circuit current
INTERNAL SLOPE COMPENSATION
m
REF = 0 V,
Slope(3)
over temperature
TJ = 25°C
V
mA
OSCILLATOR
fOSC
VP_P
Oscillator amplitude (peak-to-peak)
SYNCHRONIZATION
VSYNCH
tDEL
270
2
SYNC theshold voltage
1.6
SYNC-to-output delay
2.3
kHz
V
3.0
50
V
ns
PWM
Maximum duty cycle
66%
70%
74%
0.43
0.50
0.61
0.40
0.50
0.60
4.8
5.0
5.2
Minimum duty cycle
0%
PWM offset
CS = 0 V
V
CURRENT SENSE
VLVL
VERR(max)
Current sense level shift voltage
VCS
Current sense threshold
UCC2891
UCC2893
0.71
0.75
0.79
VCS
Current sense threshold
UCC2892
UCC2894
1.23
1.27
1.31
Maximum voltage error (clamped)
(1) Set VDD above the start threshold before setting at 12 V.
(2) Does not include current of the external oscillator network.
4
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V
SLUS542F − OCTOBER 2003 − REVISED JULY 2009
ELECTRICAL CHARACTERISTICS
VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,
RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT (OUT AND AUX)
tR
tF
Rise time
CLOAD = 2 nF
19
28
Fall time
CLOAD = 2 nF
14
23
tDEL1
tDEL2
Delay time (AUX to OUT)
CLOAD = 2 nF,
RDEL = 10 kΩ
110
Delay time (OUT to AUX)
CLOAD = 2 nF,
RDEL = 10 kΩ
115
IOUT(src)
IOUT(sink)
Output source current
VOUT(low)
VOUT(high)
Low-level output voltage
−2
Output sink current
IOUT = 150 mA
IOUT = −150 mA
50%
0.4
50%
t
50%
50%
(N−channel)
50%
50%
(P−channel)
tDEL1
V
11.1
OUT
AUX
A
2
High-level output voltage
AUX
ns
t
t
tDEL2
Figure 1. Output Timing Diagram
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
FUNCTIONAL BLOCK DIAGRAM
TYP: VREF = 5.0 V
VREF
0.05 * IRDEL
1/2 x VREF
0.05 * IRDEL
IRDEL
RDEL
92/94
VREF
CLOCK
UV
1−DMAX
OUT
VDD
13
OUT
12
AUX
11
PGND
10
SS/SD
+
PWM
OFF
IRTON
CT
VDD
4
14
VDD
OK
1.27 V
VDD
1/2 x VREF
VREF
LINEUV
91/93
13 V/ 8 V
3
15
1.27 V
+
2
RTOFF
VIN (UCC2891/3)
LINEOV (UCC2892/4)
+
OV
1
1/2 x VREF
RTON
16
VREF
SYNC
IRDEL
VDD
OUT
REF
GEN
PWM Offset
0.5 V
+
SYNC
5
S
Q
R
Q
TURN−ON
DELAY
+
VREF
75k
VREF
91/92
P−Ch.
IRDEL
VDD
5 * ISLOPE
GND
6
CS
7
TURN−ON
DELAY
+
93/94
N−Ch.
OV OFF
1−DMAX
VREF
UV OFF
ISS = 0.43 x IRTON
UCC2892/4
1.27 V
UCC2891/3
0.75 V
CT
3*R
+
VDD
2*R
UV
ISLOPE
VREF
OV
RSLOPE
8
ENABLE
9
+
6
UVLO
AND
SS
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FB
SLUS542F − OCTOBER 2003 − REVISED JULY 2009
TERMINAL FUNCTIONS
TERMINAL
UCC2891
UCC2893
UCC2892
UCC2894
I/O
AUX
12
12
O
This output drives the auxiliary clamp MOSFET which is turned on when the main PWM
switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A
source turn-on current and 2-A sink turn-off current.
CS
7
7
I
This pin is used to sense the peak current utilized for current mode control and for current
limiting functions. The peak signal which can be applied to this pin before pulse-by-pulse
current limiting activates is approximately 0.75 V for the UCC2891 and UCC2893 and 1.27 V
for the UCC2892 and UCC2894.
FB
9
9
I
This pin is used to bring the error signal from an external optocoupler or error amplifier into
the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoupler is used to pull the control pin closer to GND to reduce the pulse width of the OUT output
driving the main power switch of the converter.
GND
6
6
−
This pin serves as the fundamental analog ground for the PWM control circuitry. This pin
should be connected to PGND directly at the device.
LINEOV
−
16
I
For the UCC2892/4, provides the LINE overvoltage function.
NAME
DESCRIPTION
LINEUV
15
15
I
This pin provides a means to accurately enable/disable the power converter stage by monitoring the bulk input voltage or another parameter. When the circuit initially starts (or restarts
from a disabled condition), a rising input on LINEUV enables the outputs when the threshold
of 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables the
outputs when the same threshold is reached. The hysteresis between the two levels is programmed using an internal current source.
OUT
13
13
O
This output pin drives the main PWM switching element MOSFET in an active clamp controller. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sink
turn-off current. A 10−kΩ resistor is recommended to connect this pin to PGND.
PGND
11
11
−
The PGND should serve as the current return for the high-current output drivers OUT and
AUX. Ideally, the current path from the outputs to the switching devices, and back would be
as short as possible, and enclose a minimal loop area.
RSLOPE
8
8
I
A resistor connected from this pin to GND programs an internal current source that sets the
slope compensation ramp for the current mode control circuitry.
RTDEL
1
1
I
A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to
accommodate the resonant transitions of the active clamp power converter.
RTOFF
3
3
I
A resistor connected from this pin to GND programs an internal current source that discharges the internal timing capacitor.
RTON
2
2
I
A resistor connected from this pin to GND programs an internal current source that charges
the internal timing capacitor.
SS/SD
10
10
I
A capacitor from SS/SD to ground is charged by an internal current source of IRTON to program the soft-start interval for the controller. During a fault condition this capacitor is discharged by a current source equal to IRTON.
SYNC
5
5
I
The SYNC pin serves as a unidirectional synchronization input for the internal oscillator. The
synchronization function is implemented such that the user programmable maximum duty
cycle (set by RTON and RTOFF) remains accurate during synchronized operation.
VDD
14
14
I
This is the power supply for the device. There should be a 1-µF capacitor directly from VDD
to PGND. The capacitor value should be minimum 10 times greater than that on VREF.
PGND and GND should be connected externally and directly from PGND to GND.
VIN
16
−
I
For the UCC2891 and UCC2893, this pin is connected to the input power rail directly. Inside
the device, a high-voltage start-up device is utilized to provide the start-up current for the
controller until a bootstrap type bias rail becomes available.
VREF
4
4
O
This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA.
Since this reference provides the supply rail for internal logic, it should be bypassed to
AGND as close as possible to the device. The VREF bias profile may not be monotonic
before VDD reached 5 V.
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
DETAILED PIN DESCRIPTIONS
RDEL (pin 1)
This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND (pin 6) sets the
turn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for both
switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX
(pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as:
t DEL1 + t DEL2 + 11.1
10 *12
R DEL ) 15
10 *9 seconds
(1)
For proper selection of the delay time refer to the various references describing the design of active clamp power
converters.
RTON (pin 2)
This pin is internally connected to an approximately 2.5-V DC source. A resistor (RON) to GND (pin 6) sets the
charge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are used
to set the operating frequency and maximum operating duty cycle of the UCC2891 family.
RTOFF (pin3)
This pin is internally connected to an approximately 2.5-V DC source. A resistor (ROFF) to GND (pin 6) sets the
discharge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switching
period (TSW) and maximum operating duty cycle (DMAX) according to the following equations:
t ON + 36.1
t OFF + 15
10 *12
10 *12
R ON * t DEL1 seconds
R OFF ) t DEL1 ) 170
(2)
10 *9 seconds
T SW + t ON ) t OFF
D MAX +
(3)
(4)
t ON
T SW
(5)
VREF (pin 4)
The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good quality
ceramic bypass capacitor (CVREF) to GND (pin 6) for noise filtering and to provide compensation to the regulator
circuitry. The recommended CVREF value is 0.22-µF. The minimum bypass capacitor value is 0.022-µF limited
by stability considerations of the bias regulator, while the maximum is approximately 22-µF. Also, capacitor
value on VDD should be minimum 10 times greater than that on VREF.
The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias
is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC289x controllers.
For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional
Description section of this datasheet.
8
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
DETAILED PIN DESCRIPTIONS (continued)
SYNC (pin 5)
This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator
of the UCC289x family of controllers. The synchronizing frequency must be higher than the free running
frequency of the onboard oscillator ǒT SYNC t T SWǓ. The acceptable minimum pulse width of the
synchronization signal is approximately 50 ns (positive logic), and it should remain shorter than
ǒ1 * DMAXǓ T SYNC where DMAX is set by RON and ROFF. If the pulse width of the synchronization signal stays
within these limits, the maximum operating duty ratio remains valid as defined by the ratio of RON and ROFF,
and DMAX is the same in free running and in synchronized modes of operation. If the pulse width of the
synchronization signal would exceed the ǒ1 * D MAXǓ T SYNC limit, the maximum operating duty cycle is
defined by the synchronization pulse width.
For more information on synchronization of the UCC2891 family refer to the Functional Description section of
this datasheet.
GND (pin 6)
This pin provides a reference potential for all small signal control and programming circuitry inside the UCC2891
family.
CS (pin 7)
This is a direct input to the PWM and current limit comparators of the UCC2891 family of controllers. The CS
pin should never be connected directly across the current sense resistor (RCS) of the power converter. A small,
customary R−C filter between the current sense resistor and the CS pin is necessary to accommodate the
proper operation of the onboard slope compensation circuit and in order to protect the internal discharge
transistor connected to the CS pin (RF, CF).
Slope compensation is achieved across RF by a linearly increasing current flowing out of the CS pin. The slope
compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT)
of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the
timing capacitor. This time interval is ǒ1 * D MAXǓ T SW long and represents the guaranteed off time of the
main power switch.
RSLOPE (pin 8)
A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation
current. During the on time of the main gate drive output (OUT) the voltage across RSLOPE is a representation
of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPE
also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope
compensation is proportional to this current flowing through RSLOPE.
Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and
inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized.
For more information on how to program the internal slope compensation refer to the Setup Guide section of
this datasheet.
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
DETAILED PIN DESCRIPTIONS (continued)
FB (pin 9)
This pin is an input for the control voltage of the pulse width modulator of the UCC2891 family. The control
voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage
reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located
on the secondary side of the isolated power converter and its output voltage is sent across the isolation
boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor
to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry.
The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to
make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is
between approximately 1.25 V and 4.5 V. Control voltages below the 1.25-V threshold result in zero duty cycle
(pulse skipping) while voltages above 4.5 V result in full duty cycle (DMAX) operation.
SS/SD (pin 10)
A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft start time of the power
converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by
the RON resistor connected to pin 2. The soft-start current is defined as:
I SS + 0.43
I RTON + 0.43
V REF
2
1
R ON
(6)
This DC current charges CSS from 0 V to approximately 5 V. Internal to the UCC2891 family of controllers, the
soft start capacitor voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower
of the two voltages manipulates the controller’s PWM engine through the voltage divider described with regards
to the FB pin. Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin
and it is between 1.25 V and 4.5 V approximately.
PGND (pin 11)
This pin serves as a dedicated connection to all high-current circuits inside the UCC2891 family of parts. The
high-current portion of the controller consists of the two high-current gate drivers, and the various bias
connections except VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, a
low-impedance, external connection between the two ground pins is also required. It is recommended to form
a separate ground plane for the low current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS and
the emitter of the opto-coupler in the feedback circuit). This separate ground plane (GND) should have a single
connection to the rest of the ground of the power converter (PGND) and this connection should be between pin
6 and pin 11 of the controller.
AUX (pin 12)
This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for the
power stage. The auxiliary output (AUX) of the UCC2891 and UCC2892 drives a P-channel device as the clamp
switch therefore it requires an active low operation (the switch is ON when the output is low). The UCC2893
and UCC2894 controllers are optimized for N-channel auxiliary switch therefore it employs the traditional active
high drive signal.
10
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
DETAILED PIN DESCRIPTIONS (continued)
OUT (pin 13)
This high-current output drives an external N-channel MOSFET. Each controller in the UCC2891 family uses
active high drive signals for the main switch of the converter.
Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance
of the external circuit components connected to these pins should be carefully minimized. A potential way of
avoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximity
to the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are
connected by wide, overlapping traces.
VDD (pin 14)
The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and
for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic
capacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate
filtering. The recommended CHF value is 1-µF for most applications but its value might be affected by the
properties of the external MOSFET transistors used in the power stage.
In addition to the low-impedance, high-frequency filtering, the controller’s bias rail requires a larger value energy
storage capacitor (CBIAS) connected parallel to CHF. The energy storage capacitor must provide the hold up time
to operate the UCC2891 family (including gate drive power requirements) during start up. In steady state
operation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary
bias supply. In case of an independent auxiliary bias supply, the energy storage is provided by the output
capacitance of the bias supply. When using the internal JFET for startup, the external load on VDD must be
limited to less than 4 mA.
LINEUV (pin 15)
This input monitors the incoming power source to provide an accurate undervoltage lockout function with user
programmable hysteresis for the power supply controlled by the UCC2891 family. The unique property of the
UCC2891 family is to use only one pin to implement these functions without sacrificing on performance. The
input voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockout
comparator by an external resistor divider (RIN1, RIN2 in Figure 7). Once the line monitor’s input threshold is
exceeded, an internal current source gets connected to the LINEUV pin. The current generator is programmed
by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as:
I HYST +
V REF
2
1
R DEL
0.05
(7)
As this current flows through RIN2 of the input divider, the undervoltage lockout hysteresis is a function of IHYST
and RIN2 allowing accurate programming of the hysteresis of the line monitoring circuit.
For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet.
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DETAILED PIN DESCRIPTIONS (continued)
VIN (pin 16 − UCC2891 and UCC2893 only)
The UCC2891 and UCC2893 controllers are equipped with a high voltage, P-channel JFET start up device to
initiate operation from the input power source of the converter in applications where the input voltage does not
exceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connected
directly to the positive terminal of the input power source. The internal JFET start up transistor provides
approximately 15-mA charge current for the energy storage capacitor (CBIAS) connected across the VDD (pin
14) and PGND (pin 11) terminals. Note that the start up device is turned off immediately when the voltage on
the VDD pin exceeds approximately 13.5 V, the controller’s undervoltage lockout threshold for turn-on. The
JFET is also disabled at all times when the high-current gate drivers are switching to protect against excessive
power dissipation and current through the device. When using the internal JFET for startup, the external load
on VDD must be limited to less than 4 mA.
For more information on biasing the UCC2891 family, refer to the Setup Guide and Additional Application
Information Sections of this datasheet.
LINEOV (pin 16 − UCC2892 and UCC2894 only)
In the UCC2892 and UCC2894 controllers the high-voltage start-up device is not utilized thus pin 16 is used
for a different function. This input monitors the incoming power source to provide an accurate overvoltage
protection with user programmable hysteresis for the power supply controlled by the controller. The circuit
implementation of the overvoltage protection function is identical to the technique used for monitoring the input
power rail for undervoltage lockout. This allows implementing an accurate threshold and hysteresis using only
one pin. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage
protection comparator by an external resistor divider (RIN3, RIN4 in Figure 7). Once the line monitor’s input
threshold is exceeded, an internal current source gets connected to the LINEOV pin. The current generator is
programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as:
I HYST +
V REF
2
1
R DEL
0.05
(8)
As this current flows through RIN4 of the input divider, the overvoltage protection hysteresis is a function of IHYST
and RIN4 allowing accurate programming of the hysteresis of the line monitoring circuit.
For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet.
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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
FUNCTIONAL DESCRIPTION
JFET Control and UVLO
The UCC2891 and UCC2893 controllers include a high voltage JFET start up transistor. The steady state power
consumption of the of the control circuit which also includes the gate drive power loss of the two power switches
of an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should
only be used for initial start up of the control circuitry and to provide keep-alive power during stand-by mode
when the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own control
algorithm implemented on board the UCC2891 and UCC2893. The following timing diagram illustrates the
operation of the JFET start up device.
V ON
V IN
13.5V
10.0V
8V 4.5V)
the voltage on the CS pin is below the current limit threshold
the control voltage is above the zero duty cycle boundary (VFB > 1.25 V)
the input voltage is in the valid operating range (VVON