UCC28951PWT

UCC28951 SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 UCC28951 Phase-Shifted Full-Bridge Controller for Wide-Input Voltage Range Applications 1 Features 3 Description • • • The UCC28951 controller is an enhanced version of the UCC28950. It is a fully compatible drop-in replacement for the UCC28950. The UCC28951 uses advanced control of the full-bridge in addition to active control of the synchronous rectifier (SR) output stage. Enhanced zero-voltage switching (ZVS) range Direct synchronous rectifier (SR) control Light-load efficiency management including: – Burst mode operation – Discontinuous conduction mode (DCM), dynamic SR on/off control with programmable threshold – Programmable adaptive delay Average- or peak-current mode control with programmable slope compensation and voltagemode control Closed-loop soft-start and enable function Programmable switching frequency up to 1 MHz with bidirectional synchronization (±3%) cycle-by-cycle current limit protection with hiccup mode support 150-µA start-up current VDD undervoltage lockout Wide temperature range: –40°C to +125°C • • • • • • • Programmable delays ensure ZVS operation over a wide range of operating conditions, while the load current naturally tunes the switching delays of the secondary-side synchronous rectifiers(SR). This functionality maximizes overall system efficiency. The 24-pin, TSSOP package complies with RoHS requirements. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) UCC28951 TSSOP (24) 7.80 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • Phase-shifted full-bridge converters Server power supply Industrial power systems High-density power architectures + VBIAS CREF VIN CIN ± R3 R6 VREF GND 24 2 EA+ VDD 23 3 EA- OUTA 22 A 4 COMP OUTB 21 B CSS 5 SS/EN OUTC 20 C CVDD C1 R4 VSENSE 1 R2 R1 R5 RLF2 VDD VDD VDD QA QC A CT RAB 6 DELAB OUTD 19 D RCD 7 DELCD OUTE 18 E REF 8 DELEF OUTF 17 F C T1 ENABLE VDD VDD QD LOUT QB B RTMIN 9 TMIN SYNC 16 RT VREF 10 RT D SYNC RAHI VOUT CS 15 + RAEFHI RSUM 11 RSUM ADEL 14 QE RDCMHI E 12 DCM VREF UCC27324 UCC27324 COUT QF F ADELEF 13 RA DA RCS RDCM RLF1 CLF ± RAEF VSENSE Simplified Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Timing Requirements.................................................. 9 6.7 Dissipation Ratings..................................................... 9 6.8 Typical Characteristics.............................................. 11 7 Detailed Description......................................................18 7.1 Overview................................................................... 18 7.2 Functional Block Diagram......................................... 19 7.3 Feature Description...................................................20 7.4 Device Functional Modes..........................................36 8 Application and Implementation.................................. 37 8.1 Application Information............................................. 37 8.2 Typical Application.................................................... 40 9 Power Supply Recommendations................................69 10 Layout...........................................................................70 10.1 Layout Guidelines................................................... 70 10.2 Layout Example...................................................... 71 11 Device and Documentation Support..........................72 11.1 Device Support........................................................72 11.2 Documentation Support.......................................... 72 11.3 Receiving Notification of Documentation Updates.. 72 11.4 Community Resources............................................72 11.5 Trademarks............................................................. 72 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (September 2018) to Revision A (December 2021) Page • Updated legacy terminology to leader and follower throughout the document...................................................1 • Updated the numbering format for tables, figures, and cross-references throughout the document .................1 • Changed note in Soft-Start and Enable (SS/EN) section ................................................................................ 21 • Updated all equations in Soft-Start and Enable (SS/EN) section .................................................................... 21 • Updated mo calculation equation...................................................................................................................... 28 • Updated all equations in Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode section.............31 • Updated ICINRMS calculation equation...............................................................................................................52 • Updated resistor RT calculation equation......................................................................................................... 56 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 5 Pin Configuration and Functions VREF 1 24 GND EA+ 2 23 VDD EA– 3 22 OUTA COMP 4 21 OUTB SS/EN 5 20 OUTC DELAB 6 19 OUTD DELCD 7 18 OUTE DELEF 8 17 OUTF TMIN 9 16 SYNC RT 10 15 CS RSUM 11 14 ADEL DCM 12 13 ADELEF Figure 5-1. PW Package, 24-Pin TSSOP (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. ADEL 14 I Dead-time programming for the primary switches over CS voltage range, tABSET and tCDSET. ADELEF 13 I Delay-time programming between primary side and secondary side switches, tAFSET and tBESET. COMP 4 I/O CS 15 I Current sense for cycle-by-cycle overcurrent protection and adaptive delay functions. DCM 12 I DCM threshold setting. DELAB 6 I Dead-time delay programming between OUTA and OUTB. DELCD 7 I Dead-time delay programming between OUTC and OUTD. DELEF 8 I Delay-time programming between OUTA to OUTF, and OUTB to OUTE. EA+ 2 I Error amplifier noninverting input. EA– 3 I Error amplifier inverting input. GND 24 — OUTA 22 O OUTB 21 O OUTC 20 O OUTD 19 O OUTE 18 O OUTF 17 O RSUM 11 I Slope compensation programming. Voltage mode or peak current mode setting. RT 10 I Oscillator frequency set. leader or follower mode setting. Soft-start programming, device enable and hiccup mode protection circuit. Error amplifier output and input to the PWM comparator. Ground. All signals are referenced to this node. 0.2-A sink and source primary switching output. SS/EN 5 I SYNC 16 I/O TMIN 9 I Minimum duty cycle programming in burst mode. VDD 23 I Bias supply input. VREF 1 O 5-V, ±1.5%, 20-mA reference voltage output. Synchronization out from leader controller to input of follower controller. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 3 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Input supply voltage, VDD (3) –0.4 20 V OUTA, OUTB, OUTC, OUTD, OUTE, OUTF –0.4 VDD + 0.4 V Input voltage on DELAB, DELCD, DELEF, SS/EN, DCM, TMIN, RT, SYNC, RSUM, EA+, EA-, COMP, CS, ADEL, ADELEF –0.4 VREF + 0.4 V Output voltage on VREF –0.4 5.6 V Continuous total power dissipation See Section 6.7 Operating virtual junction temperature, TJ –40 150 °C Operating ambient temperature, TA –40 125 °C 300 °C 150 °C Lead temperature (soldering, 10 s) Storage temperature, Tstg (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These devices are sensitive to electrostatic discharge; follow proper device handling procedures. All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Section Mechanical, Packaging, and Orderable Information for thermal limitations and considerations of packages. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Charged device model (CDM), per JEDEC specification VALUE UNIT ±2000 V ±500 V JESD22-C101(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD TYP 8 12 MAX UNIT 17 V –40 125 °C Converter switching frequency setting, FSW(nom) 50 1000 kHz Programmable delay between OUTA, OUTB and OUTC, OUTD set by resistors DELAB and DELCD and parameter KA (1) 30 1000 ns Programmable delay between OUTA, OUTF and OUTB, OUTE set by resistor DELEF, and parameter KEF (1) 30 1400 ns Programmable DCM as percentage of voltage at CS(1) 5% 30% Programmable TMIN 100 800 Operating junction temperature (1) 4 MIN ns Verified during characterization only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 6.4 Thermal Information UCC28951 THERMAL METRIC(1) PW (TSSOP) UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 93.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 24.2 °C/W RθJB Junction-to-board thermal resistance 47.9 °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 47.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 5 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 6.5 Electrical Characteristics VDD = 12 V, TA = TJ = –40°C to +125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124 kΩ, RTMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz) (unless otherwise noted). All component designations are from Figure 8-3. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDERVOLTAGE LOCKOUT (UVLO) UVLO_RTH Start threshold UVLO_FTH Minimum operating voltage after start UVLO_HYST Hysteresis 6.75 TA = 25°C 7.9 7.3 6.15 TA = 25°C 7.2 6.7 0.53 TA = 25°C 0.75 0.6 V V V SUPPLY CURRENTS IDD(off) Startup current IDD Operating supply current VDD = 5.2 V 270 VDD = 5.2 V, TA = 25°C 150 10 TA = 25°C 5 µA mA VREF OUTPUT VOLTAGE VREF VREF total output range ISCC Short circuit current 0 ≤ IR ≤ 20 mA, 8 V ≤ VDD ≤ 17 V 4.925 0 ≤ IR ≤ 20 mA, 8 V ≤ VDD ≤ 17 V, TA = 25°C VREF = 0 V 5.075 5 –53 –23 92 108 V mA SWITCHING FREQUENCY (½ OF INTERNAL OSCILLATOR FREQUENCY FOSC) FSW(nom) Total range DMAX Maximum duty cycle TA = 25°C 100 kHz 97% TA = 25°C 95% SYNCHRONIZATION PHSYNC FSYNC Total range Total range RT = 59 kΩ between RT and GND, Input pulses 200 kHz, D = 0.5 at SYNC 85 °PH RT = 59 kΩ between RT and GND, Input pulses 200 kHz, D = 0.5 at SYNC, TA = 25°C RT = 59 kΩ between RT and 5 V; –40 °C ≤ TJ ≤ 125°C 90 180 TA = 25°C TPW 6 Pulse width 95 220 2.2 TA = 25°C Submit Document Feedback kHz 200 2.8 2.5 µs Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 VDD = 12 V, TA = TJ = –40°C to +125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124 kΩ, RTMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz) (unless otherwise noted). All component designations are from Figure 8-3. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VICM range ensures parameters, the functionality ensured for 3.6 V < VICM < VREF + 0.4 V, and –0.4 V < VICM < 0.5 V 0.5 3.6 –7 7 mV –1 1 µA ERROR AMPLIFIER VICM Common-mode input voltage range VIO Offset voltage IBIAS Input bias current V(EA+) – V(EA–) = 500 mV, IEAOUT = –0.5 mA EAHIGH High-level output voltage EALOW Low-level output voltage ISOURCE Error amplifier source current ISINK Error amplifier sink current IVOL GBW V 3.9 V(EA+) – V(EA–) = 500 mV, IEAOUT = –0.5 mA, TA = 25°C V 4.25 V(EA+) – V(EA–) = –500 mV, IEAOUT = 0.5 mA 0.35 V(EA+) – V(EA–) = –500 mV, IEAOUT = 0.5 mA, TA = 25°C V 0.25 –8 TA = 25°C –0.5 –3.75 2.7 5.75 TA = 25°C 4.6 Open-loop DC gain TA = 25°C 100 Unity gain bandwidth(1) TA = 25°C 3 mA mA dB MHz CYCLE-BY-CYCLE CURRENT LIMIT VCS_LIM CS pin cycle-by-cycle threshold 1.94 TA = 25°C 2.06 2 V INTERNAL HICCUP MODE SETTINGS IDS Discharge current to set cycle- VCS = 2.5 V, VVSS = 4 V by-cycle current limit duration VCS = 2.5 V, VVSS = 4 V, TA = 25°C VHCC Hiccup OFF time threshold IHCC Discharge current to set Hiccup Mode OFF Time 15 25 20 3.2 TA = 25°C 4.2 3.6 1.9 TA = 25°C 3.2 2.55 µA V µA SOFT START/ENABLE ISS Charge current VSS_STD Shutdown, restart threshold VSS_PU Pullup threshold VSS_CL Clamp voltage VSS = 0 V 20 TA = 25°C 30 25 0.25 TA = 25°C 0.7 0.5 3.3 TA = 25°C 4.3 3.7 4.2 TA = 25°C 4.95 4.65 µA V V V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 7 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 VDD = 12 V, TA = TJ = –40°C to +125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ , REF = 13.3 kΩ, RSUM = 124 kΩ, RTMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200 kHz) (unless otherwise noted). All component designations are from Figure 8-3. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.37 0.39 0.41 V 0.364 0.39 0.416 V 0.35 0.39 0.43 V LIGHT-LOAD EFFICIENCY CIRCUIT VDCM = 0.4 V, Sweep CS confirm there are OUTE and OUTF pulses, TA = 25°C VDCM DCM threshold VDCM = 0.4 V, Sweep CS, confirm there are OUTE and OUTF pulses, 0°C ≤ TA ≤ 85°CDCM threshold, (6) VDCM = 0.4 V, Sweep CS, confirm there are OUTE and OUTF pulses, –40°C ≤ TA ≤ 125°C(6) IDCM_SRC DCM Sourcing Current CS < DCM threshold 14 CS < DCM threshold, TA = 25°C 26 20 µA OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF ISINK/SRC Sink and source peak current(6) RSRC Output source resistance RSINK Output sink resistance TA = 25°C IOUT = 20 mA 0.2 10 IOUT = 20 mA, TA = 25°C IOUT = 20 mA IOUT = 20 mA, TA = 25°C A 35 20 5 30 10 Ω Ω THERMAL SHUTDOWN Rising threshold(6) TA = 25°C 160 °C threshold(6) TA = 25°C 140 °C 20 °C Falling Hysteresis (1) (2) (3) (4) (5) (6) 8 See Figure 7-1 for timing diagram and TABSET1, TABSET2, TCDSET1, TCDSET2 definitions. See Figure 7-4 for timing diagram and TAFSET1, TAFSET2, TBESET1, TBESET2 definitions. Pair of outputs OUTC, OUTE and OUTD, OUTF always going high simultaneously. Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high. All delay settings are measured relative to 50% of pulse amplitude. Verified during characterization only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 6.6 Timing Requirements MIN NOM MAX UNIT CYCLE-BY-CYCLE CURRENT LIMIT Propagation delay from CS to OUTC and OUTD outputs Input pulse between CS and GND from zero to 2.5 V TCS 100 ns PROGRAMMABLE DELAY TIME SET ACCURACY AND RANGE(1) (2) (3) (4) (5) TABSET1 Short delay time set accuracy between OUTA and OUTB CS = ADEL = ADELEF = 1.8 V 32 45 56 ns TABSET2 Long delay time set accuracy between OUTA and OUTB CS = ADEL = ADELEF = 0.2 V 216 270 325 ns TCDSET1 Short delay time set accuracy between OUTC and OUTD CS = ADEL = ADELEF = 1.8 V 32 45 56 ns TCDSET2 Long delay time set accuracy between OUTC and OUTD CS = ADEL = ADELEF = 0.2 V 216 270 325 ns TAFSET1 Short delay time set accuracy between falling OUTA, OUTF CS = ADEL = ADELEF = 0.2 V 22 35 48 ns TAFSET2 Long delay time set accuracy between falling OUTA, OUTF CS = ADEL = ADELEF = 1.8 V 190 240 290 ns TBESET1 Short delay time set accuracy between falling OUTB, OUTE CS = ADEL = ADELEF = 0.2 V 22 35 48 ns TBESET2 Long delay time set accuracy between falling OUTB, OUTE CS = ADEL = ADELEF = 1.8 V 190 240 290 ns ΔTADBC Pulse matching between OUTA rise, OUTD fall and OUTB rise, OUTC fall CS = ADEL = ADELEF = 1.8 V, COMP = 2 V –50 0 50 ns ΔTABBA Half cycle matching between OUTA rise, OUTB rise and OUTB rise, OUTA rise CS = ADEL = ADELEF = 1.8 V, COMP = 2 V –50 0 50 ns ΔTEEFF Pulse matching between OUTE fall, OUTE rise and OUTF fall, OUTF rise CS = ADEL = ADELEF = 0.2 V, COMP = 2 V –60 0 60 ns ΔTEFFE Pulse matching between OUTE fall, OUTF rise and OUTF fall, OUTE rise CS = ADEL = ADELEF = 0.2 V, COMP = 2 V –60 0 60 ns 425 525 625 ns LIGHT-LOAD EFFICIENCY CIRCUIT TMIN Total range, RTMIN = 88.7 kΩ OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF TR Rise time, CLOAD = 100 pF 9 25 ns TF Fall time, CLOAD = 100 pF 7 25 ns 6.7 Dissipation Ratings over operating free-air temperature range (unless otherwise noted) PACKAGE PW DERATING FACTOR POWER RATING ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C 10.7 mW/°C 1.07 W 0.59 W 0.429 W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 9 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 VDD 7.3-V rise, 6.7-V fall VDD_GOOD VREF VREF_GOOD 4.8-V rise, 4.6-V fall SS > 0.5 V, then release COMP, DCM, CS , Outputs A,B,C,D,E and F CLK TMIN TMIN COMP RAMP PWM Add 0.85 V offset to RAMP No PWM pulses shorter than TMIN except during cycle-by-cycle current limit PWM TMIN 2 VP-P A B C D E F Burst Mode at the beginning of start up until PWM> TMIN pulses No output delay shown, COMP-to-RAMP offset not included. There is no pulse on OUTE during burst mode at start-up. Two falling edge PWM pulses are required before enabling the synchronous rectifier outputs. Narrower pulse widths (less than 50% duty cycle) may be observed in the 1st OUTD pulse of a burst. The user must design the bootstrap capacitor charging circuit of the gate driver device so that the first OUTC pulse is transmitted to the MOSFET gate in all cases. Transformer based gate driver circuits are not affected. This behavior is described in more detail in the Gate Drive Outputs on the UCC28950 and UCC28951 During Burst Mode Operation (SLAU787) application note. Figure 6-1. UCC28951 Start-Up Timing 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 VDD failed and VDD_GOOD goes low, Everything is shutdown 7.3V rise, 6.7V fall VDD VDD_GOOD 4.8V rise, 4.6V fall VREF VREF_GOOD TMIN CLK TMIN Add 0.85V offset to RAMP COMP 2Vp-p RAMP PWM No PWM pulses shorter than TMIN except during cycle-by-cycle current limit A B C D E F No output delay shown, COMP-to-RAMP offset not included. Figure 6-2. UCC28951 Steady-State and Shutdown Timing Diagram 6.8 Typical Characteristics 640 UVLO - Under Voltage Lockout Hysteresis - mV UVLO - Under Voltage Lockout Thresholds - V 7.6 UVLO_RTH 7.4 7.2 7.0 UVLO_FTH 6.8 6.6 6.4 630 620 UVLO_HYST 610 600 590 580 6.2 -40 125 25 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C Figure 6-3. UVLO Thresholds vs Temperature Figure 6-4. UVLO Hysteresis vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 11 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 250 3.8 200 IDD - Startup Current - PA IDD - Operating Supply Current - mA 3.9 3.7 3.6 100 3.5 50 3.4 -40 -40 125 25 25 Figure 6-6. Start-Up Current vs Temperature Figure 6-5. Supply Current vs Temperature 5.010 5.001 ILOAD = 10µA 5.000 ILOAD = 1 mA 4.995 ILOAD = 10 mA 4.990 4.985 VREF _ 10 mA _ 12 VDD 4.999 VREF - Line Voltage Regulation - V 5.005 ILOAD = 20 mA 4.980 4.997 4.995 VREF _ 10 mA _ 10 VDD 4.993 4.991 VREF _ 10 mA _ 8 VDD 4.989 4.975 4.987 25 -40 125 4.985 -40 TJ - Temperature - °C 25 125 TJ - Temperature - °C Figure 6-7. Voltage Reference (VDD = 12 V) vs Temperature 12 125 TJ - Temperature - °C TJ - Temperature - °C VREF - Voltage Reference - V 150 Figure 6-8. Line Voltage Regulation (ILOAD = 10 mA) vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 38.5 95.4 95.2 DMAX - Maximum Duty Cycle - % Short Circuit Current - mA 38.0 37.5 37.0 36.5 36.0 95.0 94.8 94.6 94.4 94.2 94.0 35.5 93.8 35.0 93.6 -40 25 125 -40 TJ - Temperature - °C Figure 6-9. Short-Circuit Current vs Temperature 125 Figure 6-10. Maximum Duty Cycle vs Temperature 1079 FSW(max) - Maximum Switching Frequency - kHz 95.4 FSW(nom) - Nominal Switching Frequency - kHz 25 TJ - Temperature - °C 95.0 94.6 94.0 1059 1039 1019 999 93.6 -40 25 125 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C Figure 6-11. Nominal Switching Frequency vs Temperature Figure 6-12. Maximum Switching Frequency vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 13 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 125 0.00 120 AVOL - Voltage Error Amplifier - dB Error Amplifier OFFSET voltage - mV -0.05 -0.10 -0.15 -0.20 VIO = 500 mV -0.25 VIO = 3.6 V -0.30 -0.35 VIO = 2.5 V -0.40 115 110 105 100 95 90 -0.45 85 -0.50 -40 -40 125 25 Figure 6-13. Error Amplifier Offset Voltage vs Temperature VSS(std) - Shutdown/Restart/Reset Threshold - V 0.60 25.5 ISS - Charge Current – µA 125 Figure 6-14. Voltage Error Amplifier (Open-Loop Gain) vs Temperature 26.0 25.0 24.5 24.0 23.5 0.55 0.50 0.45 0.40 0.35 0.30 -40 25 125 -40 TJ - Temperature - °C 25 125 TJ - Temperature - °C Figure 6-15. ISS Charge Current vs Temperature 14 25 TJ - Temperature - °C TJ - Temperature - °C Figure 6-16. Shutdown, Restart, and Reset Threshold vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 4.692 3.715 4.688 3.710 VSS(CL) - SS Clamp Voltage - V VSS(pu) - SS Pullup Threshold - V 4.690 3.705 4.686 4.684 4.682 4.680 3.700 4.678 4.676 3.695 4.674 -40 25 -40 125 TJ - Temperature - °C TJ - Temperature - °C Figure 6-17. SS Pullup Threshold vs Temperature Figure 6-18. SS Clamp Voltage vs Temperature 110 TCS(prop) - Current Sense Propagation Delay - ns 1.996 VCS(lim) - Current Sense Cycle-By-Cycle Limit - V 125 25 1.994 1.992 1.990 1.988 1.986 1.984 107 104 101 98 95 -40 25 125 -40 TJ - Temperature - °C 25 125 TJ - Temperature - °C Figure 6-19. Current Sense Cycle-by-Cycle Limit vs Temperature Figure 6-20. Current Sense Propagation Delay vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 15 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 17.5 RSINK - Outputs Sink Resistance – Ω RSINK - Outputs Sink Resistance – Ω 17.5 RSINK_OUTF RSINK_OUTD 15.5 RSINK_OUTA 13.5 11.5 9.5 7.5 RSINK_OUTE RSINK_OUTC 15.5 RSINK_OUTB 13.5 11.5 9.5 7.5 -40 25 125 -40 Figure 6-21. Outputs Sink Resistance vs Temperature Figure 6-22. Outputs Sink Resistance vs Temperature 25 25 RSRC_OUTF RSRC_OUTC 23 RSRC_OUTA 21 19 17 125 RSRC_OUTE RSRC_OUTD 23 RSRC_OUTB 21 19 17 15 15 -40 25 125 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C Figure 6-23. Outputs Source Resistance vs Temperature 16 25 TJ - Temperature - °C RSRC - Outputs Source Resistance – Ω RSRC - Outputs Source Resistance – Ω TJ - Temperature - °C Figure 6-24. Outputs Source Resistance vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 50 280 TCDSET2 270 TOFFTIME - Dead Time Delay - ns TOFFTIME - Dead Time Delay - ns TCDSET1 TABSET1 45 40 TAFSET1 35 TABSET2 260 250 TAFSET2 240 TBESET2 230 TBESET1 30 220 25 -40 125 -40 TJ - Temperature - °C 25 125 TJ - Temperature - °C Figure 6-25. Dead Time Delay vs Temperature Figure 6-26. Dead Time Delay vs Temperature 0.405 0.400 DCM Threshold - V 0.395 0.390 0.385 0.380 0.380 0.375 -40 25 125 TJ - Temperature - °C Figure 6-27. DCM Threshold vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 17 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7 Detailed Description 7.1 Overview The UCC28951 controller combines all the functions necessary to control a phase-shifted, full-bridge, power stage in a 24-pin TSSOP package. The controller includes two synchronous-rectifier (SR), gate-drive outputs as well as the outputs needed to drive all four switches in the full-bridge circuit. The dead times between the upper and lower switches in the full bridge may be set using the DELAB and DELCD inputs. Further, this dead time may be dynamically adjusted according to the load level using the ADEL pin. This adjustment allows the user to optimize the dead time for their particular power circuit and to achieve ZVS over the entire operating range. In a similar manner, the dead times between the full-bridge switches and the secondary SRs may be optimized using the DELEF input. This dead time may also be dynamically adjusted according to the load, using the ADELEF input to the controller. A DCM (discontinuous conduction mode) option disables the SRs at a user settable light load to improve power circuit efficiency. The controller enters a light-load-burst mode if the feedback loop demands a conduction time less than a user settable level (TMIN). At higher-power levels, two or more UCC28951 controllers may be easily synchronized in a leader/follower configuration. A SS/EN input may be used to set the length of the soft start process and to turn the controller on and off. The controller may be configured for voltage mode or current mode control. Cycle-by-cycle current limiting is provided in voltage mode and peak current mode. Users can set the switching frequency over a wide range making this controller suited to both IGBT and MOSFET based designs. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.2 Functional Block Diagram ADEL 14 VDD VDD VDD Thermal Shutdown UVLO comparator – 23 EN Reference Generator + + – VREF 1 COMP 4 EA– 3 EA+ 2 ON/OFF 7.3-V Rise 6.7-V Fall Programmable Delay AB PWM comparator – Programmable Delay CD – 21 OUTB 20 OUTC 7 DELCD 19 OUTD 13 ADELEF 18 OUTE 8 DELEF 17 OUTF Logic Block Oscillator RAMP 2.8 V 0.8 V Ramp Summing 11 – + CS CS DELAB + + CLK RSUM 6 5-V LDO Lower "+" Input is Dominant 10 OUTA VDD + RT 22 Cycle-by-Cycle 15 ILIM Synchronization Block + – Programmable Delay EF CS Light-Load Efficiency Block 2V Soft-start and Enable with 0.55-V Threshold 16 24 12 9 5 SYNC GND DCM TMIN SS/EN Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 19 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.3 Feature Description 7.3.1 Start-Up Protection Logic Before the UCC28951 controller will start up, the following conditions must be met: • • • • VDD voltage exceeds rising UVLO threshold 7.3-V typical. The 5-V reference voltage is available. Junction temperature is below the thermal shutdown threshold of 140°C. The voltage on the soft-start capacitor is not below 0.55-V typical. If all those conditions are met, an internal enable signal EN is generated that initiates the soft-start process. The duty cycle during the soft start is defined by the voltage at the SS pin, and cannot be lower than the duty cycle set by TMIN, or by cycle-by-cycle current limit circuit depending on load conditions. 7.3.2 Voltage Reference (VREF) The accurate (±1.5%) 5-V reference voltage regulator with a short-circuit protection circuit supplies internal circuitry and provides up to 20-mA external output current. Place a low ESR and ESL, preferably ceramic decoupling capacitor CREF in 1-µF to 2.2-µF range from this pin to GND as close to the related pins as possible for best performance. The only condition where the reference regulator is shut down internally is during undervoltage lockout. 7.3.3 Error Amplifier (EA+, EA–, COMP) The error amplifier has two uncommitted inputs, EA+ and EA–, with a 3-MHz unity gain bandwidth, which allows flexibility in closing the feedback loop. The EA+ is a noninverting input, the EA– is an inverting input and the COMP is the output of the error amplifier. The input voltage common-mode range, where the parameters of the error amplifier are ensured, is from 0.5 V to 3.6 V. The output of the error amplifier is connected internally to the noninverting input of the PWM comparator. The range of the error amplifier output of 0.25 V to 4.25 V far exceeds the PWM comparator input ramp-signal range, which is from 0.8 V to 2.8 V. The soft-start signal serves as an additional noninverting input of the error amplifier. The lower of the two noninverting inputs of the error amplifier is the dominant input and sets the duty cycle where the output signal of the error amplifier is compared with the internal ramp at the inputs of the PWM comparator. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.3.4 Soft-Start and Enable (SS/EN) The soft-start pin (SS/EN) is a multi-function pin used for the following operations: • • • Closed-loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steadystate duty cycle required by the regulated output voltage. Setting hiccup mode conditions during cycle-by-cycle overcurrent limit. On/off control for the converter. During the soft-start sequence, one of the voltages at the SS/EN or EA+ pins, whichever is lower (SS/EN – 0.55 V) or EA+ voltage (see Section 7.2), sets the reference voltage for a closed feedback loop. Both SS/EN and EA+ signals are noninverting inputs of the error amplifier with the COMP pin being its output. Thus the soft-start time always goes under the closed feedback loop and the voltage at COMP pin sets the duty cycle. The duty cycle defined by the COMP pin voltage can not be shorter than TMIN pulse width set by the user. However, if the shortest duty cycle is set by the cycle-by-cycle current limit circuit, then it becomes dominant over the duty cycle defined by the COMP pin voltage or by the TMIN block. The soft-start duration is defined by an external capacitor CSS, connected between the SS/EN pin and ground, and the internal charge current that has a typical value of 25 µA. Pulling the soft-start pin externally below 0.55 V shuts down the controller. The release of the soft-start pin enables the controller to start, and if there is no current limit condition, the duty cycle applied to the output inductor gradually increases until it reaches the steady-state duty cycle defined by the regulated output voltage of the converter. This increase happens when the voltage at the SS/EN pin reaches and then exceeds by 0.55 V, the voltage at the EA+ pin. Thus for the given soft-start time TSS, the CSS value can be defined by Equation 1 or Equation 2: CSS leader = TSS × 25 µA 0.55 + V EA + CSS follower = 825 kΩ × ln (1) TSS × 25 µA (2) 20.6 20.6 − 0.55 − V EA + For example, in Equation 1, if the soft-start time TSS is 10 ms, and the EA+ pin is 2.5 V, then the soft-start capacitor CSS is equal to 82 nF. Note If the converter is configured to operate in follower mode, connect a 825-kΩ (±5%) resistor from the SS pin to ground. 7.3.5 Light-Load Power Saving Features The UCC28951 offers four different light-load management techniques for improving the efficiency of a power converter over a wide load current range. 1. Adaptive Delay, a. ADEL, which sets and optimizes the dead-time control for the primary switches over a wide load current range. b. ADELEF, which sets and optimizes the delay-time control between the primary side switches and the secondary side switches. 2. TMIN, sets the minimum pulse width as long as the part is not in current limit mode. 3. Dynamic synchronous rectifier on/off control in DCM Mode, For increased efficiency at light loads. The DCM Mode starts when the voltage at CS pin is lower than the threshold set by the user. In DCM Mode, the synchronous output drive signals OUTE and OUTF are brought down low. 4. Burst Mode, for maximum efficiency at very light loads or no load. Burst Mode has an even number of PWM TMIN pulses followed by off time. Transition to the Burst Mode is defined by the TMIN duration set by the user. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 21 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.3.6 Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL)) The resistor RAB from the DELAB pin, DELAB to GND, along with the resistor divider RAHI from CS pin to ADEL pin and RA from ADEL pin to GND sets the delay TABSET between one of outputs OUTA or OUTB going low and the other output going high Figure 7-1. The total resistance of this resistor divider should be in the range between 10 kΩ and 20 kΩ OUTA (OUTC) TABSET2 TABSET2 TCDSET2 TCDSET2 TABSET1 TABSET1 TCDSET1 TCDSET1 OUTB (OUTD) Figure 7-1. Delay Definitions Between OUTA and OUTB, OUTC and OUTD This delay gradually increases as a function of the CS signal from TABSET1, which is measured at VCS = 1.8 V, to TABSET2, which is measured at the VCS = 0.2 V. This approach ensures there will be no shoot-through current during the high-side and low-side MOSFET switching and optimizes the delay for acheiving ZVS condition over a wide load current range. The ratio between the longest and shortest delays is set by the resistor divider RAHI and R A. The maximum ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then the delay is fixed, defined only by the resistor RAB from DELAB to GND. The delay TCDSET1 and TCDSET2 settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The difference is that resistor RCD connected between DELCD pin and GND sets the delay TCDSET. The ratio between the longest and shortest delays is set by the resistor divider RAHI and RA. The delay time TABSET is defined by the following Equation 3. æ ö 5 ´ R AB TABSET = ç ÷ ns è 0.26 V + CS ´ K A ´ 1.3 ø (3) where • • • • RAB is in kΩ CS is the voltage at the CS pin in Volts KA is a numerical coefficient in the range from 0 to 1 the delay time TABSET is in ns and is measured at the IC pins The same equation is used to define the delay time TCDSET in another leg, except RAB is replaced by RCD (see Equation 4). æ ö 5 ´ RCD TCDSET = ç ÷ ns è 0.26 V + CS ´ K A ´ 1.3 ø (4) where • • • • 22 RCD is in kΩ CS is the voltage at the CS pin in Volts KA is a numerical coefficient in the range from 0 to 1 the delay time TCDSET is in ns and is measured at the IC pins Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 These equations are empirical and they are approximated from measured data. Thus, there is no unit agreement in the equations. As an example, assume RAB = 15 kΩ, CS = 1 V and KA = 0.5. Then the TABSET is approximately 90 ns. In both Equation 3 and Equation 4, KA is the same and is defined as Equation 5: KA = RA R A + R AHI (5) KA sets how the delay varies with the CS pin voltage as shown in Figure 7-2 and Figure 7-3. TI recommends starting by setting KA = 0 and set TABSET and TCDSET relatively large using equations or plots in this data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D set by resistors RAB and RCD accordingly. Program the optimal delays at light load first. Then by changing KA set the optimal delay for the outputs A, B at maximum current. KA for outputs C, D is the same as for A, B. Usually outputs C, D always have ZVS if sufficient delay is provided. Note The allowed resistor range on DELAB and DELCD, RAB and RCD is 13 kΩ to 90 kΩ. RA and RAHI define the portion of voltage at pin CS applied to the pin ADEL (see Figure 8-3). KA defines how significantly the delay time depends on CS voltage. KA varies from 0, where ADEL pin is shorted to ground (RA = 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (RAHI = 0). Setting KA, RAB, and RCD provides the ability to maintain optimal ZVS conditions of primary switches over load current because the voltage at CS pin includes the load current reflected to the primary side through the current-sensing circuit. The plots in Figure 7-2 and Figure 7-3 show the delay time settings as a function of CS voltage and KA for two different conditions: RAB = RCD = 13 kΩ (Figure 7-2) and RAB = RCD = 90 kΩ (Figure 7-3). 350 2000 KA = 0 KA = 0.1 KA = 0.25 KA = 0.5 KA = 0.75 KA = 1 250 1600 TABSET, TCDSET - Time Delay - ns TABSET, TCDSET - Time Delay - ns 300 KA = 0 KA = 0.1 KA = 0.25 KA = 0.5 KA = 0.75 KA = 1 1800 200 150 100 1400 1200 1000 800 600 400 50 200 0 0 0 0.2 0.4 0.6 0.8 1 1.2 CS Voltage - V 1.4 1.6 1.8 2 0 G001 0.5 1 CS Voltage - V 1.5 2 G001 Figure 7-2. Delay Time Set TABSET and TCDSET (Over Figure 7-3. Delay Time set TABSET and TCDSET (Over CS Voltage Variation and Selected KA for RAB and CS Voltage Variation and selected KA for RAB and RCD Equal 90 kΩ) R Equal 13 kΩ) CD Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 23 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.3.7 Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF) The resistor REF from the DELEF pin to GND along with the resistor divider RAEFHI from CS pin to ADELEF pin and RAEF from ADELEF pin to GND sets equal delays TAFSET and TBESET between outputs OUTA or OUTB going low and related output OUTF or OUTE going low Figure 7-4. The total resistance of this resistor divider should be in the range between 10 kΩ and 20 kΩ. OUTA (OUTB) OUTD (OUTC) TAFSET1 TBESET1 OUTF (OUTE) TAFSET2 TBESET2 Figure 7-4. Delay Definitions Between OUTA and OUTF, OUTB and OUTE These delays gradually increase as function of the CS signal from TAFSET1, which is measured at VCS = 0.2 V, to TAFSET2, which is measured at VCS = 1.8 V. This is opposite to the DELAB and DELCD behavior and this delay is longest (TAFSET2) when the signal at CS pin is maximized and shortest (TAFSET1) when the CS signal is minimized. This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current range thus improving efficiency. The ratio between the longest and shortest delays is set by the resistor divider RAEFHI and RAEF. If CS and ADELEF are tied, the ratio is maximized. If ADELEF is connected to GND, then the delay is fixed, defined only by resistor REF from DELEF to GND. The delay time TAFSET is defined by the following Equation 6. Equation 6 also defines the delay time TBESET. ææ ö ö 5 ´ REF TAFSET = ç ç ns + 4ns ÷ ÷ ç ÷ è è 2.65 V - CS ´ K EF ´ 1.32 ø ø (6) where • • • • REF is in kΩ the CS, which is the voltage at pin CS, is in volts KEF is a numerical gain factor of CS voltage from 0 to 1 the delay time TAFSET is in ns and is measured at the IC pins Equation 6 is an empirical approximation of measured data, thus, there is no unit agreement in it. As an example, assume REF = 15 kΩ, CS = 1 V and KEF = 0.5. Then the TAFSET is going to be 41.7 ns. KEF is defined as Equation 7: K EF = R AEF R AEF + R AEF(hi) (7) RAEF and RAEFHI define the portion of voltage at pin CS applied to the pin ADELEF (see Figure 8-3). KEF defines how significantly the delay time depends on CS voltage. KEF varies from 0, where ADELEF pin is shorted to ground (RAEF = 0) and the delay does not depend on CS voltage, to 1, where ADELEF is tied to CS (RAEFHI = 0). 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Note The allowed resistor range on DELEF, REF is 13 kΩ to 90 kΩ. The plots in Figure 7-5 and Figure 7-6 show delay time settings as function of CS voltage and KEF for two different conditions: REF = 13 kΩ (Figure 7-5) and REF = 90kΩ (Figure 7-6) 2000 350 KA = 0 KA = 2.5 KA = 0.5 KA = 0.75 KA = 0.9 KA = 1 1600 TAFSET, TBESET - Time Delay (ns) TAFSET, TBESET - Time Delay (ns) 300 KA = 0 KA = 2.5 KA = 0.5 KA = 0.75 KA = 0.9 KA = 1 1800 250 200 150 100 1400 1200 1000 800 600 400 50 200 0 0 0 0.2 0.4 0.6 0.8 1 1.2 CS Voltage (V) 1.4 1.6 1.8 0 0.2 D007 0.4 0.6 0.8 1 1.2 CS Voltage (V) 1.4 1.6 1.8 D008 Figure 7-5. Delay Time TAFSET and TBESET (Over CS Figure 7-6. Delay Time TAFSET and TBESET (Over CS Voltage and Selected KEF for REF Equal 13 kΩ) Voltage and Selected KEF for REF Equal 90 kΩ) 7.3.8 Minimum Pulse (TMIN) The resistor RTMIN from the TMIN pin to GND sets a fixed minimum pulse width. This pulse is applied to the transformer and enables ZVS at light load. If the output PWM pulse demanded by the feedback loop is shorter than TMIN, then the controller proceeds to burst mode operation where an even number of TMIN pulses are followed by the off time dictated by the feedback loop. The proper selection of the TMIN duration is dictated by the time it takes to raise sufficient magnetizing current in the power transformer to maintain ZVS. The TMIN pulse is measured from the rising edge of OUTA to the falling edge of OUTD – or from the rising edge of OUTB to the falling edge of OUTC. The minimum pulse TMIN is then defined by Equation 8. TMIN = (5.92 ´ RTMIN ) ns (8) where • • TMIN is in ns RTMIN is in kΩ Various propagation and response time delays in the power circuit modify (usually increase) the pulse width that is measured at the transformer. Select the correct TMIN setting using an iterative process due to the propagation and response time delays in the power circuit. Note The minimum allowed resistance on the TMIN pin, RTMIN is 10 kΩ. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 25 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 The related plot is shown in Figure 7-7. 800 700 600 TMIN (ns) 500 400 300 200 100 0 0 20 40 60 80 RTMIN (k:) 100 120 140 D001 Figure 7-7. Minimum Time TMIN Over Setting Resistor RTMIN The value of minimum duty cycle DMIN is determined by Equation 9. ( ) DMIN = TMIN ´ FSW (osc ) ´ 10-4 % (9) where • • • FSW(osc) is oscillator frequency in kHz TMIN is the minimum pulse in ns and DMIN is in percent 7.3.9 Burst Mode If the converter is commanding a duty cycle lower than TMIN, then the controller will go into Burst Mode. The controller will always deliver an even number of Power cycles to the Power transformer. The controller always stops its bursts with an OUTB and an OUTC power delivery cycle. If the controller is still demanding a duty cycle less than TMIN, then the controller goes into shut down mode. Then it waits until the converter is demanding a duty cycle equal or higher than TMIN before the controller puts out TMIN or a PWM duty cycle as dictated by COMP voltage pin. 7.3.10 Switching Frequency Setting Connecting an external resistor RT between the RT pin and VREF pins sets the fixed frequency operation and configures the controller as a leader providing synchronization output pulses at SYNC pin with 0.5 duty cycle and frequency equal to the internal oscillator. Connect an external resistor RT between the RT and GND pins to configure the controller as a follower. When the controller is used in follower mode, connect a 825 kΩ ±5% resistor from the SS pin to the ground pin in parallel with the SS_EN capacitor. The follower controller operates with 90° phase shift relative to the leader converter if their SYNC pins are tied together. The switching frequency of the converter is equal to the frequency of output pulses. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Equation 10 defines the nominal switching frequency of the converter configured as a leader (resistor RT between the RT pin and VREF). On the UCC28951 there is an internal clock oscillator frequency which is twice as that of the controller's output frequency. FSW (nom) æ ö ç ÷ 2.5 ´ 103 ç ÷ kHz = çæ ö RT kW ÷ + 1´ çç ç ÷÷ V ø ÷ø è è VREF - 2.5 V (10) where • • • RT is in kΩ VREF is in volts FSW(nom) is in kHz This is also an empirical approximation and thus, there is no unit agreement. Assume for example, VREF = 5 V, RT = 65 kΩ. Then the switching frequency FSW(nom) is going to be 92.6 kHz. Equation 11 defines the nominal switching frequency of converter if the converter configured as a follower and the resistor RT is connected between the RT pin and GND. FSW (nom) æ ö ç ÷ 3 2.5 ´ 10 ÷ kHz =ç ç æ RT kW ö ÷ + 1´ çç ÷ V ÷ø ø è è 2.5 V (11) where • • RT is in kΩ FSW(nom) is in kHz Notice that for VREF = 5 V, Equation 10 and Equation 11 yield the same results. The plot in Figure 7-8 shows how FSW(nom) depends on the resistor RT value when the VREF = 5 V. As it is seen from Equation 10 and Equation 11, the switching frequency FSW(nom) is set to the same value for either leader or follower configuration provided the same resistor value RT is used. 1000 FSW(nom) - Switching Frequency - kHz 900 800 700 600 500 400 300 200 100 0 5 15 25 35 45 55 65 75 85 95 105 115 125 RT - Resistor - kΩ Figure 7-8. Converter Switching Frequency FSW(nom) Over Resistor RT Value Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 27 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.3.11 Slope Compensation (RSUM) Slope compensation prevents a sub-harmonic oscillation in the controller during in peak current mode (PCM) control operation or during cycle-by-cycle current limit at duty cycles above 50% (some publications suggest it may happen at D < 50%). Slope compensation in the controller adds an additional ramp signal to the CS signal and is applied to: • • the PWM comparator in the case of peak current mode control the input of the cycle-by-cycle comparator At low duty cycles and light loads, the slope compensation ramp reduces the noise sensitivity during peak current mode control operation. Placing a resistor from the RSUM pin to ground allows the controller to operate in PCM control. Connecting a resistor from RSUM to VREF switches the controller to voltage mode control (VMC) with the internal PWM ramp. In VMC the resistor at RSUM provides CS signal slope compensation for operation in cycle-by-cycle current limit. That is, in VMC, the slope compensation is applied only to the cycle-by-cycle comparator while in PCM the slope compensation is applied to both the PWM and cycle-by-cycle current limit comparators. The operation logic of the slope compensation circuit is shown in Figure 7-9. COMP 4 + + Oscillator VREF VCM 0.85 V CLK PCM Ramp Generator VMC RAMP Cycle-by-Cycle ILIM RSUM 11 Two Direction Current Sense Ramp Summing CS_SLOPECOMP + CS 15 2V + - Mode Select GND PCM 7 GND Figure 7-9. The Operation Logic of Slope Compensation Circuit Too much slope compensation reduces the benefits of PCM control. In the case of cycle-by-cycle current limit, the average current limit becomes lower and this might reduce the start-up capability into large output capacitances. The optimum compensation ramp varies, depending on duty cycle, LOUT and LMAG. A good starting point in selecting the amount of slope compensation is to set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time). The inductor current ramp downslope (as seen at the CS pin input, and neglecting the effects of any filtering at the CS pin) is calculated in Equation 12: where • • • • 28 V RCS mo = LOUT × a1 × CT OUT RAT (12) VOUT is the output voltage of the converter LOUT is the output inductor value a1 is the transformer turns ratio (NP/NS) CTRAT is the current transformer ratio (IP/IS, typically 100:1) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Selection of LOUT, a1 and CTRAT are described later in this document. The total slope compensation is 0.5 m0. Some of this ramp is due to magnetizing current in the transformer, the rest is added by an appropriately chosen resistor from RSUM to ground. The slope of the additional ramp, me, added to the CS signal by placing a resistor from RSUM to ground is defined by Equation 13. æ öV 2.5 me = ç ÷ è 0.5 ´ RSUM ø ms (13) where • • RSUM is in kΩ me is in V/μs If the resistor from the RSUM pin is connected to the VREF pin, then the controller operates in voltage mode control, still having the slope compensation ramp added to the CS signal used for cycle-by-cycle current limit. In this case the slope is defined by Equation 14. æ (V - 2.5 V) ö V me = ç REF ÷ è 0.5 ´ RSUM ø ms (14) where • • • VREF is in volts RSUM is in kΩ me is in V/μs These are empirically derived equations without units agreement. As an example, substituting VREF = 5 V and RSUM = 40 kΩ, yields the result 0.125 V/μs. The related plot of me as a function of RSUM is shown in Figure 7-10, Because VREF = 5 V, the plots generated from Equation 13 and Equation 14 coincide. 0.50 0.45 0.40 Slope - V/µs 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 5 20 40 60 80 100 120 140 160 180 200 Rsum - Resistor - kΩ Figure 7-10. Slope of the Added Ramp Over Resistor RSUM Note The recommended resistor range for RSUM is 10 kΩ to 1 MΩ. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 29 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.3.12 Dynamic SR ON/OFF Control (DCM Mode) The voltage at the DCM pin provided by the resistor divider RDCMHI between VREF pin and DCM, and RDCM from DCM pin to GND, sets the percentage of 2-V current limit threshold for the Current Sense pin, (CS). If the CS pin voltage falls below the DCM pin threshold voltage, then the controller initiates the light load power saving mode, and shuts down the synchronous rectifiers, OUTE and OUTF. If the CS pin voltage is higher than the DCM pin threshold voltage, then the controller runs in CCM mode. Connecting the DCM pin to VREF makes the controller run in DCM mode and shuts both Outputs OUTE and OUTF. Shorting the DCM pin to GND disables the DCM feature and the controller runs in CCM mode under all conditions. VREF 1 20 mA RDCM(hi) CS DCM R = 77 kW PWM DCM_COMP 15 2-Cycle Counter + R = 77 kW 0 = DCM 1 = CCM 12 C = 6.5 pF RDCM C = 6.5 pF Other Blocks Figure 7-11. DCM Functional Block Moving into DCM Mode 0.8 VS(max) 0.6 Duty Cycle - % VS(min) TMIN Setting 0.4 0.2 Burst Mode Area 0 0 1 2 3 4 5 6 7 8 9 10 Load Current - A Figure 7-12. Duty Cycle Change Over Load Current Change A nominal 20-µA switched current source is used to create hysteresis. The current source is active only when the system is in DCM Mode. Otherwise, it is inactive and does not affect the node voltage. Therefore, when in the DCM region, the DCM threshold is the voltage divider plus ΔV explained in Equation 15. When in the CCM region, the threshold is the voltage set by the resistor divider. When the CS pin reaches the threshold set on the DCM pin, the system waits to see two consecutive falling edge PWM cycles before switching from CCM to DCM and vice-versa. The magnitude of the hysteresis is a function of the external resistor divider impedance. The hysteresis can be calculated using Equation 15: 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 DV = 2 ´ 10 -5 RDCMHI ´ RDCM RDCMHI + RDCM (15) PWM DCM Threshold + Hysteresis CS E F Figure 7-13. Moving From DCM to CCM Mode PWM DCM Threshold + Hysteresis CS E F Figure 7-14. Moving From CCM to DCM Mode DCM must be used to prevent reverse current in the output inductor which could cause the synchronous FETS to fail. The controller must switch to DCM mode at a level where the output inductor current is positive. If the output inductor current is negative when the controller switches to DCM mode then the synchronous FETs will see a large VDS spike and may fail. 7.3.13 Current Sensing (CS) The signal from the current sense pin is used for cycle-by-cycle current limit, peak-current mode control, light-load efficiency management and setting the delay time for outputs OUTA, OUTB, OUTC, OUTD and delay time for outputs OUTE, OUTF. Connect the current sense resistor RCS between CS and GND. Depending on layout, to prevent a potential electrical noise interference, TI recommends pulling a small R-C filter between the RCS resistor and the CS pin. There is a 200-Ω pulldown at the CS pin which is turned on after the PWM comparator has tripped. This helps to reset the CS signal prior to the following switching cycle. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode The cycle-by-cycle current limit provides peak current limiting on the primary side of the converter when the load current exceeds its predetermined threshold. For peak current mode control, a certain leading edge blanking time is needed to prevent the controller from false tripping due to switching noise. An internal 30-ns filter at the CS input is provided. The total propagation delay TCS from CS pin to outputs is 100 ns. An external RC filter is still needed if the power stage requires more blanking time. The 2.0-V ±3% cycle-by-cycle current limit threshold is optimized for efficient current transformer based sensing. The duration when a converter operates at cycle-by-cycle current limit depends on the value of soft-start capacitor and how severe the overcurrent condition is. This is achieved by the internal discharge current IDS Equation 16 and Equation 17 at SS pin. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 31 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 IDS leader = −25 × 1 − D + 5  µA (16) IDS follower = −25 × 1 − D  µA (17) The soft-start capacitor value also determines the so-called hiccup mode off-time duration. The behavior of the converter during different modes of operation, along with related soft-start capacitor charge and discharge currents are shown in Figure 7-15. SS Pin (V) SS Clamp Voltage 4.65 Pull Up Threshold 3.70 3.60 Soft Start Cycle-by-Cycle ILIM Normal . Operation OFF Time Before Restart 25 mA Soft Restart Fast Pull Up by 1 kW Switch IDS = (-25 x (1-D)+5) mA Output Enable Threshold 0.55 0.00 ISS=25 mA IHCC = 2.5 mA Output Pulses (D) Figure 7-15. Timing Diagram of Soft-Start Voltage VSS The largest discharge current of 20 µA is when the duty cycle is close to zero. This current sets the shortest operation time during the cycle-by-cycle current limit and is defined in Equation 18 and Equation 19 C × 4.65 V − 3.7 V TCL on_leader = SS 20 µA (18) C × 4.65 V − 3.7 V TCL on_follower = SS 25 µA (19) Thus, if the soft-start capacitor CSS = 100 nF is selected, then the TCL(on) time is 5 ms. To calculate the hiccup off time TCL(off) before the restart, use Equation 20 or Equation 21. C × 4.65 V − 3.7 V TCL off _leader = SS 2.5 µA (20) C × 4.65 V − 3.7 V TCL off _follower = SS 2.5 µA (21) With the same soft-start capacitor value at 100 nF, the off-time before the restart is 122 ms. If the overcurrent condition occurs before the soft-start capacitor voltage reaches the 3.7-V threshold during start-up, the controller limits the current but the soft-start capacitor continues to be charged. As soon as the 3.7-V threshold is reached, the soft-start voltage is quickly pulled up to the 4.65-V threshold by an internal 1-kΩ RDS(on) switch and the cycle-by-cycle current limit duration timing starts by discharging the soft-start capacitor. Depending on specific design requirements, the user can override this default behavior by applying external charge or discharge currents to the soft-start capacitor. The whole cycle-by-cycle current limit and hiccup operation is shown in Figure 7-15. In this example, the cycle-by-cycle current limit lasts about 5 ms followed by 122 ms of off-time. Similarly to the overcurrent condition, the hiccup mode with the restart can be disabled by the user if a pullup resistor of 261 k Ω is connected between the SS and VREF pins. The controller remains in the latch-off mode if 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 an overcurrent condition occurs. In this case, calculate an external soft-start capacitor value with the additional pullup current taken into account. The latch-off mode can be reset externally if the soft-start capacitor is forcibly discharged below 0.55 V or the VDD voltage is lowered below the UVLO threshold. 7.3.15 Synchronization (SYNC) The UCC28951 allows flexible configuration of converters operating in synchronized mode by connecting all SYNC pins together and by configuration of the controllers as leader and/or followers. The controller configured as leader (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency equal to 2X the converter frequency FSW(nom) and 0.5 duty cycle. The controller configured as a follower (resistor between RT and GND and 825-kΩ resistor between SS_EN pin to GND) does not generate the synchronization pulses. The follower controller synchronizes its own clock to the falling edge of the synchronization signal thus operating 90° phase shifted versus the leader converter’s frequency FSW(nom). The output inductor in a full bridge converter sees a switching frequency which is twice that seen by the transformer. In the case of the UCC28951 this means that the output inductor operates at 2 × FSW(nom). This means that the 90° phase shift between leader and follower controllers gives a 180° phase shift between the currents in the output inductors and hence maximum ripple cancellation. For more information about synchronizing more than two UCC28951 devices, see Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers (SLUA609). If the synchronization feature is not used then the SYNC pin may be left floating, but connecting the SYNC pin to GND through a 10-kΩ resistor will reduce noise pickup and switching frequency jitter. • • • • • • If any converter is configured as a follower, the SYNC frequency must be greater than or equal to 1.8 times the converter frequency. follower converter does not start until at least one synchronization pulse has been received. If any or all converters are configured as followers, then each converter operates at its own frequency without synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of synchronization pulses at the follower converter, then the controller uses its own internal clock pulses to maintain operation based on the RT value that is connected to GND in the follower converter. In leader mode, SYNC pulses start after SS pin passes its enable threshold which is 0.55 V. follower starts generating SS/EN voltage even though synchronization pulses have not been received. TI recommends that the SS on the leader controller starts before the SS on the follower controller; therefore SS/EN pin on leader converter must reach its enable threshold voltage before SS/EN on the follower converter starts for proper operation. On the same note, TI also recommends that the TMIN resistors on both leader and follower are set at the same value. CLK SYNC_OUT A B Figure 7-16. SYNC_OUT (leader Mode) Timing Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 33 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 SYNC_IN CLK A B Figure 7-17. SYNC_IN (follower Mode) Timing Diagram 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF) • • • • • • All MOSFET control outputs have 0.2-A drive capability. The control outputs are configured as P-MOS and N-MOS totem poles with typical RDS(on) 20 Ω and 10 Ω, accordingly. The control outputs are capable of charging 100-pF capacitor within 12 ns and discharge within 8 ns. The amplitude of output control pulses is equal to VDD. Control outputs are designed to be used with external gate MOSFET/IGBT drivers. The design is optimized to prevent the latch-up of outputs and verified by extensive tests. The UCC28951 controler has outputs OUTA, OUTB driving the active leg, initiating the duty cycle leg of power MOSFETs in a phase-shifted full bridge power stage, and outputs OUTC, OUTD driving the passive leg, completing the duty cycle leg, as it is shown in the typical timing diagram in Figure 8-1. Outputs OUTE and OUTF are optimized to drive the synchronous rectifier MOSFETs (see Figure 8-3). These outputs have 200-mA peak-current capabilities and are designed to drive relatively small capacitive loads like inputs of external MOSFET or IGBT drivers. Recommended load capacitance should not exceed 100 pF. The amplitude of the output signal is equal to the VDD voltage. 7.3.17 Supply Voltage (VDD) Connect this pin to a bias supply in the range from 8 V to 17 V. Place high-quality, low ESR and ESL and at least 1-µF ceramic bypass capacitor CVDD from this pin to GND. TI recommends using a 10-Ω resistor in series from the bias supply to the VDD pin to form an RC filter with the CVDD capacitor. 7.3.18 Ground (GND) All signals are referenced to this node. TI recommends having a separate quiet analog plane connected in one place to the power plane. The analog plane connects the components related to the pins VREF, EA+, EA-, COMP, SS/EN, DELAB, DELCD, DELEF, TMIN, RT, RSUM. The power plane connects the components related to the pins DCM, ADELEF, ADEL, CS, SYNC, OUTF, OUTE, OUTD, OUTC, OUTB, OUTA, and VDD. Figure 7-18 shows an example of layout and ground planes connection. 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 CREF R1 R2 VREF GND 24 2 EA+ VDD 23 3 EA- OUTA 22 A 4 COMP OUTB 21 B CSS 5 SS/EN OUTC 20 C RAB 6 DELAB OUTD 19 D RCD 7 DELCD OUTE 18 E REF 8 DELEF OUTF 17 F RT(min) 9 TMIN SYNC 16 SYNC C1 R3 VSENSE VDD R5 R4 R6 CVDD 1 C3 C2 ENABLE Analog Plane 10 RT RT Power Plane CS 15 RAHI RSUM 11 RSUM ADEL 14 RA RDCMHI VREF 12 DCM ADELEF 13 RAEFHI Current Sense R7 RCS RDCM RAEF Figure 7-18. Layout Recommendation for Analog and Power Planes Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 35 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 7.4 Device Functional Modes The UCC28951 offers many operational modes. These modes are described in detail in Section 7.3. • • • • • • • • • • Current mode1. The UCC28951 controller operates in current mode control when the RSUM pin is connected to GND through a resistor (RSUM) . The resistor sets the amount of slope compensation. Voltage mode1. The controller operates in voltage mode control when the RSUM pin is connected to VREF through a resistor (RSUM). The chosen resistor value gives the correct amount of slope compensation for operation in current limit mode (cycle-by-cycle current limit). DCM mode. The controller enters DCM mode when the signal at the CS pin falls below the level set by the resistor at the DCM pin. The SR drives (OUTE and OUTF) turn off and secondary rectification occurs through the body diodes of the SRs. Burst mode. The controller enters burst mode when the pulse width demanded by the feedback signal falls below the width set by the resistor at the TMIN pin. Leader mode. This is the default operation mode of the controller and is used when there is only one UCC28951 controller in the system. Connect the timing resistor (RT) from the RT pin to VREF. In a system with more than one UCC28951 controller, configure one as the leader and the others as followers1. Follower mode. The follower controller operates with a 90° phase shift relative to the leader (providing their SYNC pins are tied together). Connect the timing resistor (RT) from the RT pin to GND and connect an 825-kΩ ±5% resistor from the SS/EN pin to GND1. Synchronized mode. When a UC28950 controller is configured as a follower, its SYNC pin is used as an input. The follower synchronizes its internal oscillator at 90° to the signal at its SYNC pin. The application note, Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers, discusses how multiple follower controllers may be synchronized to a single leader oscillator. Hiccup mode. This mode provides overload protection to the power circuit. The UCC28951 controller stops switching after a certain time in current limit. It starts again (soft-start) after a delay time. The user can control the time spent in current limit before switching is stopped and the delay time before the soft start happens. Current-limit mode. The UCC28951c ontroller provides cycle-by-cycle current limiting when the signal at the CS pin reaches 2 V. Latch-off mode. Connect a resistor between the SS pin and VREF. The UCC28951 controller then latches off when the controller enterscurrent-limit mode. 1 1 36 Current mode control and voltage mode control are mutually exclusive as are leader and follower modes. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The high efficiency of a phase-shifted full-bridge DC-DC converter using the UCC28951 is achieved by using synchronous rectification, a control algorithm providing ZVS condition over the entire load current range, accurate adaptive timing of the control signals between primary and secondary FETs and special operating modes at light load. A simplified electrical diagram of this converter is shown in Figure 8-3. The UCC28951controller is located on the secondary side of converter, although it could be placed on the primary side as well. The secondary side lication allows easy power system level communication and better handling of some transient conditions that require fast direct control of the synchronous rectifier MOSFETs. The power stage includes primary side MOSFETs, QA, QB, QC, QD and secondary side synchronous rectifier MOSFETs, QE and QF. For example, for the 12-V output converters in server power supplies use of the center-tapped rectifier scheme with L-C output filter is a popular choice. To maintain high efficiency at different output power conditions, the converter operates in synchronous rectification mode at mid and high output power levels, transitioning to diode rectifier mode at light load and then into burst mode as the output power becomes even lower. All of these transitions are based on current sensing on the primary side using a current sense transformer in this specific case. The major waveforms of the phase-shifted converter during normal operation are shown in Figure 8-1. The upper six waveforms in Figure 8-1 show the output drive signals of the controller. In normal mode, the outputs OUTE and OUTF overlap during the part of the switching cycle when both rectifier MOSFETs are conducting and the windings of the power transformer are shorted. Current, IPR, is the current flowing through the primary winding of the power transformer. The bottom four waveforms show the drain-source voltages of rectifier MOSFETs, VDS_QE and VDS_QF, the voltage at the output inductor, V LOUT, and the current through the output inductor, I LOUT. Proper timing between the primary switches and synchronous rectifier MOSFETs is critical to achieve highest efficiency and reliable operation in this mode. The controller adjusts the turn OFF timing of the rectifier MOSFETs as a function of load current to ensure minimum conduction time and reverse recovery losses of their internal body diodes. ZVS is an important feature of relatively high input voltage converters in reducing switching losses associated with the internal parasitic capacitances of power switches and transformers. The controller ensures ZVS conditions over the entire load current range by adjusting the delay time between the primary MOSFETs switching in the same leg in accordance to the load variation. The controller also limits the minimum ON-time pulse applied to the power transformer at light load, allowing the storage of sufficient energy in the inductive components of the power stage for the ZVS transition. As the load current reduces from full load down to the no-load condition, the controller selects the most efficient power saving mode by moving from the normal operation mode to the discontinuous-current diode-rectification mode and, eventually, at very light-load and at no-load condition, to the burst mode. These modes and related output signals, OUTE, OUTF, driving the rectifier MOSFETs, are shown in Figure 8-2. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 37 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 TSW(nom) TABSET2 OUTA TABSET1 TCDSET2 OUTB TSW(osc) OUTC TCDSET1 OUTD IPR VOUTx(1-D) /D VLOUT VOUT ILOUT IOUT Figure 8-1. Phase-Shifted Converter Waveforms OUTE (CCM Mode) OUTF (CCM Mode) OUTE OUTE and OUTF are disabled if VCS < VDCM OUTF OUTE and OUTF are disabled if VCS < VDCM Burst Mode at light load with TMIN maintaining ZVS (The time scale is different versus above diagram) Transformer Winding Magnetizing Current Figure 8-2. Major Waveforms During Transitions Between Different Operating Modes 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output inductor at light load, during parallel operation and at some transient conditions. Such reverse current results in circulating of some extra energy between the input voltage source and the load and, therefore, causes increased losses and reduced efficiency. Another negative effect of such reverse current is the loss of ZVS condition. The suggested control algorithm prevents reverse current flow, still maintaining most of the benefits of synchronous rectification by switching off the drive signals of rectifier MOSFETs in a predetermined way. At some pre-determined load current threshold, the controller disables outputs OUTE and OUTF by bringing them down to zero. Synchronous rectification using MOSFETs requires some electrical energy to drive the MOSFETs. There is a condition below some light-load threshold when the MOSFET drive related losses exceed the saving provided by the synchronous rectification. At such light load, it is best to disable the drive circuit and use the internal body diodes of rectifier MOSFETs, or external diodes in parallel with the MOSFETs, for more efficient rectification. In most practical cases, the drive circuit needs to be disabled close to DCM mode. This mode of operation is called discontinuous-current diode-rectification mode. At very light-load and no-load conditions, the duty cycle, demanded by the closed-feedback-loop control circuit for output voltage regulation, can be very low. This level leads to the loss of ZVS condition and increased switching losses. To avoid the loss of ZVS, the control circuit limits the minimum ON-time pulse applied to the power transformer using resistor from TMIN pin to GND. Therefore, the only way to maintain regulation at very light load and at no-load condition is to skip some pulses. The controller skips pulses in a controllable manner to avoid saturation of the power transformer. Such operation is called burst mode. In Burst Mode there are always an even number of pulses applied to the power transformer before the skipping off time. Thus, the flux in the core of the power transformer always starts from the same point during the start of every burst of pulses. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 39 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8.2 Typical Application A typical application for the UCC28951 is a controller for a phase-shifted full-bridge converter that converts a 390-VDC input to a regulated 12-V output using synchronous rectifiers to achieve high efficiency. + CT VBIAS VIN CIN CREF R1 R2 1 VREF GND 24 R3 C1 2 EA+ VDD 23 3 EA- OUTA 22 A 4 COMP OUTB 21 B RLF2 VDD CVDD ± VDD VDD R5 VSENSE C2 R6 R4 C3 QA QC A C NP CSS 5 SS/EN OUTC 20 C RAB 6 DELAB OUTD 19 D RCD 7 DELCD OUTE 18 E REF 8 DELEF OUTF 17 F RTMIN 9 TMIN SYNC 16 SYNC RAHI NS ENABLE VREF 10 RT NS VDD VDD QB RT T1 LOUT B QD D VOUT + CS 15 RSUM 11 RSUM ADEL 14 RDCMHI VREF UCC27324 RAEFHI QE UCC27324 QF E 12 DCM F ADELEF 13 RA DA R7 RCS RDCM RLF1 CLF COUT ± RAEF VSENSE Figure 8-3. Typical Application 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8.2.1 Design Requirements Table 8-1 lists the requirements for this application. Table 8-1. UCC28951 Typical Application Design Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 370 390 410 V 2 A 12.6 V INPUT CHARACTERISTICS VIN DC input voltage range IIN(max) Maximum input current VIN= 370 VDC to 410 VDC OUTPUT CHARACTERISTICS VOUT Output voltage VIN= 370 VDC to 410 VDC IOUT Output current VIN= 370 VDC to 410 VDC Output voltage transient 90% load step Continuous output power VIN= 370 VDC to 410 VDC 600 W Load regulation VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 140 mV Line regulation VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 140 mV Output ripple voltage VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A 200 mV POUT 11.4 12 50 600 A mV SYSTEM FSW Switching Frequency Full-load efficiency 100 VIN= 370 VDC to 410 VDC, POUT= 500 W 93% kHz 94% Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 41 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8.2.2 Detailed Design Procedure In high-power server applications to meet high-efficiency and green standards some power-supply designers have found it easier to use a phase-shifted, full-bridge converter. This is because the phase-shifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converter, reducing switching losses, and EMI and increasing overall efficiency. This is a review of the design of a 600-W, phase-shifted, full-bridge converter for one of these power systems using the UCC28951 device, which is based on typical values. In a production design, the values may need to be modified for worst-case conditions. TI has provided a MathCAD Design Tool and an Excel Design Tool to support the system designer. Both tools can be accessed in the Tools and Software tab of the UCC28951 product folder on TI.com, or can be downloaded through the following links: MathCAD Design Tool, Excel Design Tool. Note The term fSW refers to the switching frequency applied to the power transformer. The output inductor experiences a switching frequency that is 2 × fSW . 8.2.2.1 Power Loss Budget To meet the efficiency goal, a power loss budget must be set (see Equation 22). æ 1- h ö PBUDGET = POUT ´ ç ÷ » 45.2 W è h ø (22) 8.2.2.2 Preliminary Transformer Calculations (T1) Transformer turns ratio (a1) is: a1 = NP NS (23) Estimate FET voltage drop (VRDSON) as: VRDSON = 0.3 V Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give some room for dropout if a PFC front end is used (see Equation 24 and Equation 25). a1 = a1 = NP NS (24) (VINMIN - 2 ´ VRDSON )´ DMAX VOUT + VRDSON » 21 (25) Turn the ratio and round is to the nearest whole turn: a1 = 21 Calculate the typical duty cycle (DTYP) based on average input voltage in Equation 26. DTYP = (VOUT + VRDSON )´ a1 » 0.66 (VIN - 2 ´ VRDSON ) (26) Output inductor peak-to-peak ripple current is set to 20% of the output current using Equation 27. 42 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 DILOUT = POUT ´ 0.2 = 10 A VOUT (27) Take care in selecting the correct amount of magnetizing inductance (LMAG). Equation 28 calculates the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in current-mode control. As LMAG reduces, the increasing magnetizing current becomes an increasing proportion of the signal at the CS pin. If the magnetizing current increases enough, it can swamp out the current sense signal across RCS and the converter will operate increasingly as if it were in voltage mode control rather than current mode. LMAG ³ VIN ´ (1 - DTYP ) » 2.78mH DILOUT ´ 0.5 ´ 2 ´ FSW a1 (28) Figure 8-4 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents with respect to the synchronous rectifier gate drive currents. IQE and IQF are the same as the secondary winding currents of T1. Variable D is the duty cycle of the converter. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 43 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 IPP IMP2 » IPP - DILOUT / (2 ´ a1) IMP2 IPRIMARY IMP 0A D On QEg Off On QFg Off IQE 0A IQF IPS IMS2 IMS IMS2 » IPS - DILOUT /2 0A DILOUT /2 Figure 8-4. T1 Primary and QE and QF FET Currents 44 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Calculate T1 secondary RMS current (ISRMS) in Equation 29 through Equation 31: IPS = POUT DILOUT + » 55 A VOUT 2 (29) POUT DILOUT » 45 A VOUT 2 (30) IMS = IMS2 = IPS - ΔILOUT » 50 A 2 (31) Secondary RMS current (ISRMS1) when energy is being delivered to the secondary (see Equation 32): (I - I ) æD öé ISRMS1 = ç MAX ÷ êIPS ´ IMS + PS MS 3 è 2 ø êë 2 ù ú » 29.6 A úû (32) Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are both on (see Equation 33). ISRMS2 2 IPS - IMS2 ) ù ( æ 1 - DMAX ö é ú » 20.3 A = ç ÷ êIPS ´ IMS2 + 2 3 è ø êë úû (33) Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling period calculated in Equation 34. Refer to Figure 8-4. ISRMS3 = DILOUT æ 1 - DMAX ö ç 2 ´ 3 ÷ » 1.1A 2 è ø (34) Total secondary RMS current (ISRMS) is calculated in Equation 35: ISRMS = ISRMS12 + ISRMS22 + ISRMS3 2 » 36.0 A (35) Calculate T1 Primary RMS Current (IPRMS) using Equation 36 through Equation 40: D ILMAG = VINMIN ´ DMAX » 0.47 A LMAG ´ 2 ´ FSW (36) æ P DI IPP = ç OUT + LOUT 2 è VOUT ´ h ö1 ÷ + DILMAG » 3.3 A ø a1 (37) æ P DI IMP = ç OUT - LOUT 2 è VOUT ´ h ö1 ÷ + DILMAG » 2.8A ø a1 (38) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 45 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 é IPRMS1 = (DMAX )êêIPP ´ IMP + (IPP - IMP )2 ùú 3 ë æ DI IMP2 = IPP - ç LOUT è 2 ú û » 2.5 A (39) ö1 ÷ a1 » 3.0 A ø (40) T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary (see Equation 41). é IPRMS1 = (DMAX )êêIPP ´ IMP + ë (IPP - IMP )2 ùú 3 ú û » 2.5 A (41) T1 Primary RMS (IPRMS2) current when the converter is free wheeling. This is calculated in Equation 42: IPRMS2 2 é IPP - IMP2 ) ù ( ú » 1.7 A = (1 - DMAX )êIPP ´ IMP2 + 3 êë úû (42) The total T1 primary RMS current (IPRMS) is calculated using Equation 43: IPRMS = IPRMS12 + IPRMS22 » 3.1A (43) For this design, a Vitec™ transformer was selected for part number 75PR8107 with the following specifications: • • • • • • a1 = 21 LMAG = 2.8 mH measured leakage inductance on the Primary (LLK) is 4 µH transformer Primary DC resistance (DCRP) is 0.215 Ω transformer Secondary DC resistance (DCRS) is 0.58 mΩ estimated transformer core losses (PT1) calculated in Equation 44 are twice the copper loss (which is an estimate and the total losses may vary based on magnetic design) ( ) PT1 » 2 ´ IPRMS 2 ´ DCRP + 2 ´ ISRMS 2 ´ DCRS » 7.0 W (44) Calculate remaining power budget using Equation 45: PBUDGET = PBUDGET - PT1 » 38.1W (45) 8.2.2.3 QA, QB, QC, QD FET Selection In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon are chosen for QA..QD. The FET drain to source on resistance is: Rds(on)QA = 0.220 W (46) The FET Specified COSS is: 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 COSS _ QA _ SPEC = 780pF (47) The voltage across drain-to-source (VdsQA) where COSS was measured as a data sheet parameter: VdsQA = 25 V (48) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 47 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Calculate average Coss [2] using Equation 49: COSS _ QA _ AVG = COSS _ QA _ SPEC VdsQA » 193pF VINMAX (49) The QA FET gate charge is: QA g = 15nC (50) The voltage applied to FET gate to activate FET is: Vg = 12 V (51) Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg) using Equation 52: PQA IPRMS2 u RDS(on)QA 2 u QAg u Vg u fSW | 2.1W (52) Recalculate the power budget using Equation 53: PBUDGET = PBUDGET - 4 ´ PQA » 29.7 W (53) 8.2.2.4 Selecting LS Calculating the value of the shim inductor (LS) is based on the amount of energy required to achieve zero voltage switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. Equation 54 selects LS to achieve ZVS at 100% load down to 50% load based on the primary FET’s average total COSS at the switch node. Note The actual parasitic capacitance at the switched node may differ from the estimate and LS may have to be adjusted accordingly. VINMAX 2 - LLK » 26 mH LS ³ (2 ´ COSS _ QA _ AVG ) 2 æ IPP DILOUT ö ç 2 - 2 ´ a1 ÷ è ø (54) For this design, a 26-µH Vitec inductor was chosen for LS, part number 60PR964. The shim inductor has the following specifications: LS = 26 mH (55) The LS DC Resistance is: DCRLS = 27mW (56) Estimate LS power loss (PLS) and readjust remaining power budget using Equation 57 through Equation 58: PLS = 2 ´ IPRMS 2 ´ DCRLS » 0.5 W 48 (57) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 PBUDGET = PBUDGET - PLS » 29.2 W (58) 8.2.2.5 Selecting Diodes DB and DC There is a potential for high voltage ringing on the secondary rectifiers, caused by the difference in current between the transformer and the shim inductor when the transformer comes out of freewheeling. Diodes DB and DC provide a path for this current and prevent any ringing by clamping the transformer primary to the primary side power rails. Normally these diodes do not dissipate much power, but must be sized to carry the full primary current. The worse case power dissipated in these diodes is calculated using Equation 59: P = 0.5 ´ LS ´ I2PRMS ´ FSW (59) Choose ultra-fast type diodes rated for the input voltage of the converter – VIN (410 VDC in this case). The MURS360 diode accomodates this power level. 8.2.2.6 Output Inductor Selection (LOUT) Inductor LOUT is designed for 20% inductor ripple current (∆ILOUT) calculated in Equation 60 and Equation 61: DILOUT = LOUT POUT ´ 0.2 600 W ´ 0.2 = » 10 A VOUT 12 V VOUT u (1 DTYP ) | 2 PH 'ILOUT u 2 u fSW (60) (61) Calculate output inductor RMS current (ILOUT_RMS) using Equation 62: 2 ILOUT _ RMS 2 æ P ö æ DI ö = ç OUT ÷ + ç LOUT ÷ = 50.1A è VOUT ø è 2 3 ø (62) A 2-µH inductor from Vitec Electronics Corporation, part number 75PR8108, is suitable for this design. The inductor has the following specifications: LOUT = 2 mH (63) The output inductor DC resistance is: DCRLOUT = 750 mW (64) Estimate output inductor losses (PLOUT) using Equation 65 and recalculate the power budget using Equation 66. Note PLOUT is an estimate of inductor losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It is advisable to double check the magnetic loss with the magnetic manufacture. PLOUT = 2 ´ ILOUT _ RMS 2 ´ DCRLOUT » 3.8 W (65) PBUDGET = PBUDGET - PLOUT » 25.4 W (66) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 49 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8.2.2.7 Output Capacitance (COUT) The output capacitor is selected based on holdup and transient (VTRAN) load requirements. The time it takes LOUT to change 90% of its full load current is calculated in Equation 67: tHU LOUT ´ POUT ´ 0.9 VOUT = = 7.5 ms VOUT (67) During load transients most of the current will immediately go through the capacitors equivalent series resistance (ESRCOUT). Equation 68 and Equation 69 are used to select ESRCOUT and COUT based on a 90% load step in current. The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output capacitance (COUT) is selected for 10% of VTRAN. ESRCOUT £ COUT VTRAN ´ 0.9 = 12mW POUT ´ 0.9 VOUT (68) POUT ´ 0.9 ´ tHU VOUT ³ » 5.6mF VTRAN ´ 0.1 (69) Before selecting the output capacitor, the output capacitor RMS current (ICOUT_RMS) must be calculated using Equation 70. ICOUT _ RMS = DILOUT 3 » 5.8 A (70) To meet the design requirements five 1500-µF, aluminum electrolytic capacitors are chosen for the design from United Chemi-Con™, part number EKY-160ELL152MJ30S. These capacitors have an ESR of 31 mΩ. The number of output capacitors (n) is 5. The total output capacitance is calculated usingEquation 71: COUT = 1500 mF ´ n » 7500 mF (71) The effective output capacitance ESR is calculated usingEquation 72: ESRCOUT = 31mW = 6.2mW n (72) Calculate output capacitor loss (PCOUT) using Equation 73: PCOUT = ICOUT _ RMS 2 ´ ESRCOUT » 0.21W (73) Recalculate the remaining Power Budget using Equation 74: PBUDGET = PBUDGET - PCOUT » 25.2 W 50 Submit Document Feedback (74) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8.2.2.8 Select FETs QE and QF Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics. QEg = 152nC (75) Rds(on)QE = 3.2mW (76) Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage in the design (VdsQE) that will be applied to the FET in the application. The voltage across FET QE and QF when they are of isf: VdsQE = 2VINMAX = 39 V a1 (77) The voltage where FET COSS is specified and tested in the FET data sheet: Vds _ spec = 25 V (78) The specified output capacitance from FET data sheet is: COSS _ SPEC = 1810pF (79) The average QE and QF COSS [2] is calculated using Equation 80: COSS _ QE _ AVG = COSS _ SPEC Vds _ SPEC VdsQE » 1.9nF (80) The QE and QF RMS current are: IQE _ RMS = ISRMS = 36.0 A (81) To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at the end of the miller plateau (QEMILLER_MAX) for the given VDS. The maximum gate charge at the end of the miller plateau is: QEMILLER _ MAX » 100nC (82) The minimum gate charge at the beginning of the miller plateau is: QEMILLER _ MIN » 52nC (83) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 51 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Note The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (IP) of gate drive current. IP » 4 A (84) Estimated FET Vds rise and fall time using Equation 85: tr » t f = 100nC - 52nC 48nC = » 24ns IP 4A 2 2 (85) Estimate QE and QF FET Losses (PQE) using Equation 86: PQE IQE _RMS2 u Rds(on)QE POUT u VdsQE tr VOUT t f fSW 2 u COSS _ QE _ AVG u VdsQE2fSW 2 u QgQE u VgQEfSW (86) PQE » 9.3 W (87) Recalculate the power budget using Equation 88. PBUDGET = PBUDGET - 2 ´ PQE » 6.5 W (88) 8.2.2.9 Input Capacitance (CIN) The input voltage in this design is 390 VDC, which is typically fed by the output of a PFC boost pre-regulator. It is typical to select input capacitance based on holdup and ripple requirements. Note The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP). Calculate tank frequency using Equation 89: fR = 1 2p LS ´ (2 ´ COSS _ QA _ AVG ) (89) Estimate the delay time using Equation 90: tDELAY = 2 » 314ns f R ´4 (90) The effective duty cycle clamp (DCLAMP) is calculated in Equation 91: DCLAMP 52 § 1 ¨ © 2 u fSW · tDELAY ¸ u 2 u fSW ¹ 94% Submit Document Feedback (91) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 VDROP is the minimum input voltage where the converter can still maintain output regulation (see Equation 92). The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator. æ 2 ´ DCLAMP ´ VRDSON + a1´ (VOUT + VRDSON ) ö VDROP = ç ÷ = 276.2 V DCLAMP è ø (92) CIN was calculated in Equation 93 based on one line cycle of holdup: 2 ´ POUT ´ CIN ³ (V IN 2 1 60Hz - VDROP 2 ) » 364 mF (93) Calculate the high-frequency input capacitor RMS current (ICINRMS) using Equation 94. POUT ICINRMS = IPRMS12 − V = 1.8 A VIN min ×  η (94) To meet the input capacitance and RMS current requirements for this design, a 330-µF capacitor was chosen from Panasonic part number EETHC2W331EA: CIN = 330 µF This capacitor has a high frequency (ESRCIN) of 150 mΩ and is measured with an impedance analyzer at 200 kHz. ESRCIN = 0.150 Ω Estimate the CIN power dissipation (PCIN) using Equation 95: PCIN = ICINRMS 2 ´ ESRCIN = 0.5 W (95) And recalculate the remaining power budget using Equation 96: PBUDGET = PBUDGET - PCIN » 6.0 W (96) There is approximately 6.0 W that remains in the power budget for the current-sensing network, to bias the control device, and for all resistors supporting the control device. 8.2.2.10 Current Sense Network (CT, RCS, R7, DA) The CT chosen for this design has a turns ratio (CTRAT) of 100:1 in Equation 97: CTRAT = IP = 100 IS (97) Calculate nominal peak current (IP1) at VINMIN: The peak primary current is calculated using Equation 98: æ P DI IP1 = ç OUT + LOUT 2 è VOUT ´ h ö1 VINMIN ´ DMAX » 3.3 A ÷ + ´ ´ a1 L 2 F MAG SW ø (98) The CS pin voltage where peak current limit will trip is: Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 53 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 VP = 2 V (99) Calculate current sense resistor (RCS) and leave 300 mV for slope compensation using Equation 100. Include a 1.1 factor for margin: RCS = VP - 0.3 V » 47 W IP1 ´ 1.1 CTRAT (100) Select a standard resistor for RCS: RCS = 47 W (101) Estimate the power loss for RCS using Equation 102: 2 PRCS æI ö = ç PRMS1 ÷ ´ RCS » 0.03 W è CTRAT ø (102) Calculate maximum reverse voltage (VDA) on DA using Equation 103: VDA = VP DCLAMP » 29.8 V 1 - DCLAMP (103) Estimate the DA power loss (PDA) using Equation 104: PDA = POUT ´ 0.6 V » 0.01W VINMIN ´ h ´ CTRAT (104) Calculate reset resistor R7: Resistor R7 is used to reset the current sense transformer CT: R7 = 100 ´ RCS = 4.7kW (105) Resistor RLF1 and capacitor CLF form a low-pass filter for the current sense signal (Pin 15). For this design, chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz, (which is appropriate for most applications) but may be adjusted to suit individual layouts and EMI present in the design. RLF1 = 1kW (106) CLF = 330pF (107) fLFP = 1 = 482kHz 2pf ´ RLF1 ´ CLF (108) The UCC28951 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. This pin needs at least 1 µF of high-frequency bypass capacitance (CREF). CREF = 1 mF 54 (109) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (R1, R2), for this design example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1 and then calculate resistor value R2. UCC28951 reference voltage: VREF = 5 V (110) Set voltage amplifier reference voltage: V1 = 2.5 V (111) R1 = 2.37kW (112) R2 = R1´ (VREF - V1) V1 = 2.37kW (113) The voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-). Select a standard resistor for R3: R3 = 2.37kW (114) Calculate R4 using Equation 115: R4 = R3 ´ (VOUT - V1) V1 » 9kW (115) Then choose a standard resistor for R4 using Equation 116: R4 = R3 ´ (VOUT - V1) V1 » 9.09kW (116) Note TI recommends using an RCD clamp to protect the output synchronous FETs from overvoltage due to switch node ringing. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 55 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Figure 8-5. Daughter Board Schematic 8.2.2.10.1 Voltage Loop Compensation Recommendation For best results in the voltage loop, TI recommends using a Type 2 or Type 3 compensation network (Figure 8-6). A Type 2 compensation network does not require passive components CZ2 and RZ2. Type 1 compensation 56 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 is not versatile enough for a phase-shifted full bridge. When evaluating the COMP pin for best results, TI recommends placing a 1-kΩ resistor between the scope probe and the COMP pin of the UCC28951. VOUT VREF CZ2 EA+ RI + EA1 k: RD RZ2 R CZ1 RZ1 CP1 R When evaluating COMP, for best results put a 1-k: resistor between COMP and probe. Figure 8-6. Type 3 Compensation Evaluation Compensating the feedback loop can be accomplished by properly selecting the feedback components (R5, C1 and C2). These components are placed as close as possible to pin 3 and 4 of the controller. A Type 2 compensation network is designed in this example. Calculate load impedance at 10% load (RLOAD) : RLOAD VOUT 2 = = 2.4 W POUT ´ 0.1 (117) Approximate control to output transfer function (GCO(f)) as a function of frequency: GCO (f ) » æ 1 + 2pj ´ f ´ ESRCOUT ´ COUT ö R DVOUT = a1´ CTRAT ´ LOAD ´ ç ÷´ RCS è 1 + 2pj ´ f ´ RLOAD ´ COUT ø DVC 1 æ S(f ) ö S(f ) 1+ +ç ÷ 2p ´ fPP è 2p ´ fPP ø Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 2 (118) 57 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Calculate double pole frequency of GCO(f): FSW = 50kHz 2 fPP » (119) Calculate angular velocity: S(f ) = 2p ´ j ´ f (120) Compensate the voltage loop with Type 2 feedback network. The following transfer function is the compensation gain as a function of frequency (GC(f)): GC (f ) = DVC = DVOUT 2pj ´ f ´ R5 ´ C2 + 1 æ 2pj ´ f ´ C2 ´ C1´ R5 ö + 1÷ 2pj ´ f ´ (C2 + C1)R4 ç C2 + C1 è ø (121) Calculate voltage loop feedback resistor (R5) based on the crossing the voltage loop (fC) over at a 10th of the double pole frequency (fPP): fC = fPP = 5kHz 10 R5 = (122) R4 » 27.9kW æ fPP ö GCO ç ÷ è 10 ø (123) The standard resistor selcted for R5 is 27.4 kΩ. Calculate the feedback capacitor (C2) to give added phase at crossover: C2 = 1 f 2 ´ p ´ R5 ´ C 5 » 5.8nF (124) The standard capacitance value (C2) selected for the design is 5.6 nF. Put a pole at two times fC: C1 = 1 » 580pF 2 ´ p ´ R5 ´ fC ´ 2 (125) The standard capacitance value (C1) selected for the design is 560 pF. Use Equation 126 to calculate the loop gain as a function of frequency (TV(f)) in dB. TV dB(f ) = 20log (GC (f ) ´ GCO (f ) ) (126) Plot a theoretical loop gain and phase to graphically confirm loop stability. The theoretical loop gain crosses over at roughly 3.7 kHz with a phase margin of greater than 90 degrees. 58 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 80 180 60 135 40 90 20 45 0 0 -20 -45 -40 -90 TvdB(f) -60 Phase in Degrees Gain in dB www.ti.com -135 &Tv(f) -80 100 1000 10000 -180 100000 Frequency in Hz Figure 8-7. Loop Gain and Phase vs Frequency Note TI recommends confirming the loop stability of the final design with transient testing and/or a network analyzer. Adjust the compensation (GC(f)) feedback as necessary. LMAG ³ VIN ´ (1 - DTYP ) » 2.78mH DILOUT ´ 0.5 ´ 2 ´ FSW a1 (127) where • • loop gain (TVdB(f)) loop phase (ΦTV(f)) To limit overshoot during the power up sequence, the UCC28951 has a soft-start function (SS, Pin 5). In this application the soft-start time is 15 ms (tSS). CSS = t SS ´ 25 mA » 123nF V1 + 0.55 (128) The standard capacitor (CSS) selected for this design is 150 nF. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 59 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 This application presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. Adaptive delays can be generated by connecting the ADEL and ADELEF pins to the CS pin as shown in Figure 8-8 . RAHI CS 15 RAEFHI ADEL 14 RA RAEF ADELEF 13 Figure 8-8. Adaptive Delays When the converter is operating below 50% load, the converter operates in valley switching. To achieve zero voltage switching on switch node of QBd, the turn-on (tABSET) delays of FETs QA and QB must be initially set based on the interaction of LS and the theoretical switch node capacitance. The following equations are used to set tABSET initially. Equate shim inductance to two times COSS capacitance using Equation 129: 2p ´ fRLS = 1 2p ´ fR ´ (2 ´ COSS _ QA _ AVG ) (129) Calculate tank frequency using Equation 130: fR = 1 2p LS ´ (2 ´ COSS _ QA _ AVG ) (130) Set initial tABSET delay time and adjust as necessary. Note The 2.25 factor of the tABSET equation was derived from empirical test data and may vary based on individual design differences. t ABSET = 2.25 » 346ns f R ´4 (131) The resistor divider formed by RA and RAHI programs the tABSET, tCDSET delay range of the controller. The standard resistor value RAHI selected is 8.25 kΩ. tABSET can be programmed between 30 ns to 1000 ns. 60 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 The voltage at the ADEL input of the controller (VADEL) must be set with RA based on the following conditions: • If tABSET > 155 ns, set VADEL = 0.2 V. tABSET can be programmed between 155 ns and 1000 ns. • If tABSET ≤ 155 ns, set VADEL = 1.8 V. tABSET can be programmed between 29 ns and 155 ns. Based on VADEL selection, calculate RA: RA = R AHI ´ VADEL » 344 W 5V - VADEL (132) The closest standard resistor value for RA selected is 348 Ω. Recalculate VADEL based on resistor divider selection: VADEL = 5 V ´ RA = 0.202 V R AHI + R A (133) Resistor RAB programs tABSET. Variable CS is the voltage at the CS pin with respect to ground and ratio KA was calculated in Equation 5: R AB = TABSET ´ (0.26 + CS ´ K A ´ 1.3 ) » 30.6kW 5 (134) The standard resistor value for RAB selected for the design is 30.1 kΩ. Note After a prototype oprational, fine tune tABSET during light-load operation to the peak and valley of the resonance between LS and the switch node capacitance. In this design, the delay was set at 10% load. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 61 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Set t ABSET at resonant tank Peak and Valley t ABSET = t 1 - t 0 t ABSET = t 4 - t 3 QB d QA g Miller Plateau tMILLER = t QB 2 - t1 Miller Plateau g t MILLER = t 5 - t 4 t0 t1 t2 t3 t4 t5 Figure 8-9. tABSET to Achieve Valley Switching at Light Loads 62 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 Initially, set the QC and QD turn-on delays (tCDSET) for the same delay as the QA and QB turn-on delays (Pin 6). The following equations program the QC and QD turn-on delays (tCDSET) by properly selecting resistor RDELCD (Pin 7). t ABSET = t CDSET (135) Resistor RCD programs tCDSET: RCD = TCDSET ´ (0.26 + CS ´ K A ´ 1.3 ) » 30.6kW 5 (136) The standard resistor RCD selected for this design is 30.1 kΩ. Note After a prototype operational, fine tune tCDSET during light-load operation. In this design, the CD node was set to valley switch at roughly 10% load.. Obtaining ZVS at lighter loads with switch node QDd is easier due to the reflected output current present in the primary of the transformer at FET QD and QC during the turnoff or turnon period. This behavior is due to more peak current available to energize LS before this transition, compared to the QA and QB turnoff and turnon period. Set t t CDSET QD QC =t 1 CDSET t CDSET - t0 =t 4 - t3 d g Miller Plateau t MILLER QD at resonant tank Peak and Valley =t 2 -t1 Miller Plateau g t MILLER t 0 t1 t 2 =t 5 -t4 t 3 t4 t 5 Figure 8-10. tCDSET to Achieve Valley Switching at Light Loads Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 63 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff of FET QE after FET QB turnoff (tBESET). Set these delays to 50% of tABSET to ensure that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large, it causes OUTE and OUTF not to overlap correctly and creates excess body diode conduction on FETs QE and QF. t AFSET = tBESET = t ABSET ´ 0.5 (137) The resistor divider formed by RAEF and RAEFHI programs the tAFSET and tBESET delay range of the controller. The standard resistor value selected for RAEFHI is 8.25 kΩ. Note tAFSET and tBESET can be programmed between 32 ns to 1100 ns. The voltage at the ADELEF pin of the controller (VADELEF) needs to be set with RAEF based on the following conditions. • • If tAFSET < 170 ns set VADEL = 0.2 V, tABSET can be programmed between 32 ns and 170 ns. If tABSET > or = 170 ns set VADEL = 1.7 V, tABSET can be programmed between 170 ns and 1100 ns. Based on VADELEF selection, calculate RAEF: R AEF = R AEFHI ´ VADELEF » 4.25kW 5 V - VADELEF (138) The closest standard resistor value for RAEF is 4.22 kΩ. Recalculate VADELEF based on resistor divider selection: VADELEF = 5 V ´ R AEF = 1.692 V R AEFHI + R AEF (139) The following equation was used to program tAFSET and tBESET by properly selecting resistor REF. REF = (t AFSET ´ 0.5 - 4ns ) ´ (2.65 V - VADELEF ´ 1.32 )´ 103 ´ ns 5 1 » 14.1kW 1A (140) The standard resistor value selected for REF is 14 kΩ. Resistor RTMIN programs the minimum on time (tMIN) that the UCC28951 (Pin 9) can demand before entering burst mode. If the UCC28951 controller tries to demand a duty cycle on time of less than tMIN the power supply goes into burst mode operation. For this design set the minimum on-time (tMIN) to 75 ns. Set the minimum on-time by selecting RTMIN : RTMIN = tMIN » 12.7kW 5.92 (141) The standard resistor value for RTMIN is 13 kΩ. A resistor from the RT pin to ground sets the converter switching frequency calculated in Equation 142. RT = 64 2.5 × 106 × Ω Hz V −Ω V f SW 2 × VREF − 2.5 V = 60 kΩ Submit Document Feedback (142) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 The standard resistor value selected for RT is 61.9 kΩ. The UCC28951 provides slope compensation. The amount of slope compensation is set by the resistor RSUM. As suggested earlier, set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time), reflected through the main transformer and current sensing networks as explained earlier in Section 7.3.11. Calculate required slope compensation ramp: me 0.5 u VOUT u RCS LOUT u a1 u CTRAT 0.5 u 12 u 47 2 u 10 6 u 21 u 100 67 mV Ps (143) The magnetizing current of the power transformer provides part of the slope compensation ramp. The slope of this current is calculated using Equation 144 where VINHU is the minimum voltage for VOUT holdup purposes. It is the voltage at which the converter is operating at the maximum dudy cycle (DMAX) while maintaining VOUT: m MAG = VINHU ´ RCS 260 ´ 47 mV = » 44 3 ms LMAG ´ CTRAT 2.76 x10 ´ 100 (144) Calculate the required compensating ramp: m SUM = me - m MAG = (67 - 44 ) mV mV = 23 ms ms (145) The value for the resistor, RSUM, may be found from the graph in Figure 7-10, calculated from rearranged versions of Equation 13, or calculated by Equation 13, depending on whether the controller is operating in current mode or voltage control mode. This design uses current mode control and Equation 146 is rearranged and evaluated: R SUM = 2.5 2.5 = » 200 k W 0.5 ´ m SUM 0.5 ´ 23 x10 - 3 (146) Confirm that the 300 mV allowed for the slope compensation ramp is sufficient when choosing RCS in Equation 100. DVSLOPE -COMP = mSUM ´ DMAX 2 ´ FSW mV ´ 0.7 ms = = 80 mV 2 ´ 100 kHz 23 (147) To increase efficiency at lighter loads the UCC28951 is programmed (Pin 12, DCM) under light-load conditions to disable the synchronous FETs on the secondary side of the converter (QE and QF). This threshold is programmed with resistor divider formed by RDCMHI and RDCM. This DCM threshold needs to be set at a level before the inductor current goes discontinuous. Equation 148 sets the level at which the synchronous rectifiers are disabled at roughly 15% load current. VRCS æ POUT ´ 0.15 DILOUT ö + ç ÷ ´ RCS VOUT 2 ø è = = 0.29 V a1´ CTRAT (148) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 65 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 The standard resistor value selected for RDCM is 1 kΩ. Calculate resistor value RDCMHI. RDCMHI = RDCM (VREF - VRCS ) » 16.3kW VRCS (149) The standard resistor value for RDCMHI is 16.9 kΩ. 66 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 8.2.3 Application Curves Switch node QBd is valley switching and node QDd has achieved ZVS. Please refer to Figure 8-13 and Figure 8-14. It is not uncommon for switch node QDd to obtain ZVS before QBd. This is because during the QDd switch node voltage transition, the reflected output current provides immediate energy for the LC tank at the switch node. Where at the QBd switch node transition the primary has been shorted out by the high-side or low-side FETs in the H bridge. This transition is dependent on the energy stored in LS and LLK to provide energy for the LC tank at switch node QBd making it take longer to achieve ZVS. Valley Switching QB QD d d Valley Switching QD g QB g QB = off QB = on QD = off QD = on QC = on QC = off 0V 0V QA= on QA/QB = off t ABSET t CDSET t D Slight Delay after t t D Slight Delay after t ABSET VIN = 390 V VIN = 390 V IOUT = 5 A Figure 8-11. Full-Bridge Gate Drives and Primary Switch Nodes (QBd and QDd) Valley Switching QB d QD d QD g ZVS 0V QA/QB = off tABSET tD Slight Delay after t before Miller Plateau 0V QD = off QB = on QA = on VIN = 390 V IOUT = 5 A Figure 8-12. Full-Bridge Gate Drives and Primary Switch Nodes (QDg QDd) QB g QB = off CDSET before Miller Plateau before Miller Plateau QD = on 0V QC = on QC = off t CDSET ABSET VIN = 390 V IOUT = 10 A Figure 8-13. Full-Bridge Gate Drives and Switch Nodes (QBg QBd) tD Slight Delay after t before Miller Plateau CDSET IOUT = 10 A Figure 8-14. Full-Bridge Gate Drives and Switch Nodes (QDg QDd) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 67 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 ZVS Achieved QBd QD d QD g ZVS QBg QB = off QD = off QB = on QD = on 0V 0V QA = on QC = on QA/QB = off t ABSET VIN = 390 V QC= off t CDSET IOUT = 25 A VIN = 390 V Figure 8-15. Full-Bridge Gate Drives and Switch Nodes (QBg QBd) IOUT = 25 A Figure 8-16. Full-Bridge Gate Drives and Switch Nodes (QDg QDd) When the converter is running at 25 A, both switch nodes are operating into zero voltage switching (ZVS). It is also worth mentioning that there is no evidence of the gate miller plateau during gate driver switching. This is because the voltage across the drains and sources of FETs QA through QD transitioned earlier. ZVS QB d QD d QD g ZVS QB g QB = off QD = off QB = on QA = on 0V QC = on QA/QB = off t ABSET VIN = 390 V QC = off t CDSET IOUT = 50 A Figure 8-17. Full-Bridge Gate Drives and Switch Nodes (QBg QBd) 68 QD = on 0V VIN = 390 V ZVS maintained from 50% to 100% output power IOUT = 50 A Figure 8-18. Full-Bridge Gate Drives and Switch Nodes (QDg QDd) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 9 Power Supply Recommendations Operate the UCC28951 controller from a VDD rail within the limits given in the Section 6.3 section of this data sheet. To avoid the possibility that the controller might stop switching, do not allow the VDD to fall into the UVLO_FTH range. To minimize power dissipation in the controller, ensure that VDD is not unnecessarily high. Maintaining VDD at 12 V is a good compromise between these competing constraints. The gate drive outputs from the controller deliver large-current pulses into their loads. This indicates the need for a low-ESR decoupling capacitor to be connected as directly as possible between the VDD and GND terminals. TI recommends ceramic capacitors with stable dielectric characteristics over temperature, such as X7R. Avoid capacitors which have a large drop in capacitance with applied DC voltage bias. For example, use a component that has a low-voltage co-efficient of capacitance. The recommended decoupling capacitance is 1 μF, X7R, with at least a 25-V rating with a 0.1-µF NPO capacitor in parallel. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 69 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 10 Layout 10.1 Layout Guidelines To increase the reliability and robustness of the design, TI recommends the following layout guidelines: • • • • • • • • • • • 70 For the VREF pin: decouple this pin to GND with a good quality ceramic capacitor. A 1-µF, X7R, 25-V capacitor is recommended. Keep VREF PCB tracks as far away as possible from sources of switching noise. For the EA+ pin: this is the noninverting input to the error amplifier. It is a high impedance pin and is susceptible to noise pickup. Keep tracks from this pin as short as possible. For theEA– pin: this is the inverting input to the error amplifier. It is a high impedance pin and is susceptible to noise pickup. Keep tracks from this pin as short as possible. For theCOMP pin: the error amplifier compensation network is normally connected to this pin. Keep tracks from this pin as short as possible. For theSS/EN pin: keep tracks from this pin as short as possible. If the Enable signal is coming from a remote source then avoid running it close to any source of high dv/dt (MOSFET Drain connections for example) and add a simple RC filter at the SS/EN pin. For the DELAB, DELCD, DELEF, TMIN, RT, RSUM, DCM, ADELEF and ADEL pins: the components connected to these pins are used to set important operating parameters. Keep these components close to the IC and provide short, low impedance return connections to the GND pin. For the CS pin: this connection is arguably the most important single connection in the entire PSU system. Avoid running the CS signal traces near to sources of high dv/dt. Provide a simple RC filter as close to the pin as possible to help filter out leading edge noise spikes which occur at the beginning of each switching cycle. For the SYNC pin: this pin is essentially a digital I/O port. If it is unused, then it may be left open circuit or tied to ground through a 1-kΩ resistor. If Synchronisation is used, then route the incoming Synchronisation signal as far away from noise sensitive input pins as possible. For the OUTA, OUTB, OUTC, OUTD, OUTE and OUTF pins: these are the gate drive output pins. They have a high dv/dt rate associated with their rising and falling edges. Keep the tracks from these pins as far away from noise sensitive input pins as possible. Ensure that the return currents from these outputs do not cause voltage changes in the analog ground connections to noise sensitive input pins. Follow the layout recommendation for analog and power ground planes in Figure 7-18. For the VDD pin: this pin must be decoupled to GND using ceramic capacitors as detailed in the Section 9 section. Keep this capacitor as close to the VDD and GND pins as possible. For the GND pin: this pin provides the ground reference to the controller. Use a ground plane to minimize the impedance of the ground connection and to reduce noise pickup. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 10.2 Layout Example VREF pin decoupled to GND (C1), close to the device R28 R6 C8 R2 R7 C3 VDD decoupling as close to the device as possible. (C6, C5) Top Side C1 R9 C6 C5 R15 U1 C4 R5 R1 OUTA through OUTE signals routed as far as possible from signal pins. (pins 17 through 22) R12 R11 R13 R16 R24 C7 R14 R27 R25 R17 R26 R28 RC filter close to CS pin. (C7, R27, pin 15) R22 R23 Short tracks at EA+, EA-, COMP, SS/EN, DELAB, DELCD, TMIN, RT, RSUM, DCM, ADELEF, and ADEL pins. (pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14) Figure 10-1. Layout Example (Top Side) Bottom Side R29 C2 J1 R3 R4 R20 R8 R10 Figure 10-2. Layout Example (Bottom Side) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 71 UCC28951 www.ti.com SLUSDB2A – AUGUST 2018 – REVISED DECEMBER 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support UCC28950 MathCAD Design Tool. UCC28950 Excel Design Tool. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers (SLUA609) • Making the Correct Choice: UCC28950-Q1 or UCC28951-Q1 (SLUA853) • Gate Drive Outputs on the UCC28950 and UCC28951-Q1 During Burst Mode Operation (SLAU787) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources 11.5 Trademarks Vitec™ is a trademark of Vitec Electronics Corporation. United Chemi-Con™ is a trademark of United Chemi-Con, Inc.. All trademarks are the property of their respective owners. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 72 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCC28951 PACKAGE OPTION ADDENDUM www.ti.com 7-Dec-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC28951PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC28951 UCC28951PWT ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC28951 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of