UCC2895-Q1
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SLUS783C – MAY 2008 – REVISED AUGUST 2012
BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER
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FEATURES
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Programmable Output Turn-On Delay
Bidirectional Oscillator Synchronization
Voltage-Mode, Peak-Current-Mode, or
Average-Current-Mode Control
Programmable Soft Start/Soft Stop and Chip
Disable Via a Single Pin
0% to 100% Duty-Cycle Control
7-MHz Error Amplifier
Operation to 1 MHz
Typical 5-mA Operating Current at 500 kHz
Very Low 150-μA Current During Undervoltage
Lockout (UVLO)
APPLICATIONS
•
•
•
•
Phase-Shifted Full-Bridge Converters
Off-Line, Telecom, Datacom, and Servers
Distributed Power Architecture
High-Density Power Modules
UCC2895
DESCRIPTION
The UCC2895-Q1 is a phase-shift pulse-width
modulation (PWM) controller that implements control
of a full-bridge power stage by phase shifting the
switching of one half-bridge with respect to the other.
It allows constant-frequency PWM in conjunction with
resonant zero-voltage switching to provide high
efficiency at high frequencies. The device can be
used either as a voltage-mode or current-mode
controller.
Although the UCC2895-Q1 maintains the functionality
of the UC3875/6/7/8 family and UC3879, it improves
on that controller family with additional features such
as enhanced control logic, adaptive delay set, and
shutdown capability. Because it is built using the
BCDMOS process, it operates with dramatically less
supply current than its bipolar counterparts. The
UCC2895-Q1 can operate with a maximum clock
frequency of 1 MHz.
Q1
7
EAP 20
1
EAN
2
EAOUT SS/DISB 19
3
RAMP
OUTA
18
4
REF
OUTB
17
5
GND
PGND
16
6
SYNC
7
CT
OUTC 14
8
RT
OUTD
9
DELAB
VCC 15
VOUT
A
VIN
VBIAS
B
10 DELCD
C
D
13
CS 12
ADS
11
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2012, Texas Instruments Incorporated
UCC2895-Q1
SLUS783C – MAY 2008 – REVISED AUGUST 2012
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ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – DW
ORDERABLE PART NUMBER
Reel of 2000
UCC2895QDWRQ1
TOP-SIDE MARKING
UCC2895Q
For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DW PACKAGE
(TOP VIEW)
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
ADS
ABSOLUTE MAXIMUM RATINGS (1)
TA = –40°C to 125°C, all voltage values are with respect to the network ground terminal (unless otherwise noted)
VALUE
VDD
Supply voltage
IDD
Supply current
IDD < 10 mA
30 mA
17 V
IREF
Reference current
15 mA
IO
Output current
100 mA
Analog input voltage range
EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB
–0.3 V to REF + 0.3 V
–0.3 V to VDD + 0.3 V
Drive output voltage range
OUTA, OUTB, OUTC, OUTD
PD
Power dissipation
TA = 25°C
Tstg
Storage temperature range
TJ
Junction temperature range
650 mW
–65°C to 150°C
–55°C to 150°C
Human-body model (HBM)
ESD
(1)
Electrostatic discharge
protection
800 V
Machine model (MM)
200 V
Charged-device model (CDM)
2000 V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (1)
MIN
VDD
Supply voltage
NOM
10
MAX
UNIT
16.5
V
10 ×
CREF
CVDD
Supply voltage bypass capacitor (2)
CREF
Reference bypass capacitor (3)
CT
Timing capacitor
For 500-kHz switching frequency
220
pF
RT
Timing resistor
For 500-kHz switching frequency
82
kΩ
(1)
(2)
(3)
2
0.1
μF
4.7
μF
It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a
separate ground plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 should be
located over this ground plane. Any connections associated with these pins to ground should be connected to this ground plane.
The VDD capacitor should be a low-ESR, -ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk
capacitor should be located as physically close as possible to the VDD pins.
The VREF capacitor should be a low-ESR, -ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is
desired for VREF, then it should be located near the VREF capacitor and connected to the VREF pin with a resistor of 51 Ω or greater. The
bulk capacitor on VDD must be a factor of 10 geater than the total VREF capacitance.
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RECOMMENDED OPERATING CONDITIONS(1) (continued)
MIN
RDEL_AB
Delay resistor
RDEL_CD
Operating junction temperature (4)
TJ
(4)
NOM
MAX
UNIT
2.5
40
kΩ
–55
125
°C
It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
ELECTRICAL CHARACTERISTICS
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF, no load on the outputs,
TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.2
11
11.8
V
8.2
9
9.8
V
1
2
3
V
150
250
μA
5
6
mA
Undervoltage Lockout (UVLO)
UVLO(on)
Start-up voltage threshold
UVLO(off)
Minimum operating voltage after startup
UVLO(hys)
Hysteresis
Supply
ISTART
Start-up current
IDD
Operating current
VDD_CLAMP
VDD clamp voltage
VDD = 8 V
IDD = 10 mA
16.5
17.5
18.5
V
Voltage Reference
TJ = 25°C
4.94
5
5.06
VREF
Output voltage
10 V < VDD < VDD_CLAMP,
0 mA < IREF < 5 mA, TJ = –40°C to 125°C
4.85
5
5.15
ISC
Short-circuit current
REF = 0 V, TJ = 25°C
10
20
V
mA
Error Amplifier
–0.1
3.6
VIO
Common-mode input voltage
Offset voltage
–7
7
mV
IBIAS
Input bias current (EAP, EAN)
–1
1
μA
VOH_EAOUT
High-level output voltage
EAP – EAN = 500 mV, IEAOUT = –0.5 mA
4
4.5
5
V
VOL_EAOUT
Low-level output voltage
EAP – EAN = –500 mV, IEAOUT = 0.5 mA
0
0.2
0.4
ISOURCE
Error amplifier output source current
EAP – EAN = 500 mV, EAOUT = 2.5 V
1
1.5
mA
ISINK
Error amplifier output sink current
EAP – EAN = –500 mV, EAOUT = 2.5 V
2.5
4.5
mA
AVOL
Open-loop dc gain
75
85
dB
GBW
Unity gain bandwidth (1)
5
7
MHz
1.5
2.2
V/μs
No-load comparator turn-off threshold
0.45
0.5
0.55
V
No-load comparator turn-on threshold
0.55
0.6
0.69
V
0.035
0.1
0.165
V
1 V < EAN < 0 V, EAP = 500 mV,
0.5 V < EAOUT < 3 V
Slew rate (1)
No-load comparator hysteresis
V
V
Oscillator
fOSC
Frequency
TJ = 25°C
Frequency total variation (1)
Over line and temperature
VIH_SYNC
High-level input voltage, SYNC
VOH_SYNC
High-level input voltage, SYNC
ISYNC = –400 μA, VCT = 2.6 V
VOL_SYNC
Low-level output voltage, SYNC
ISYNC = 100 μA, VCT = 2.6 V
SYNC output pulse width
LOADSYNC = 3.9 kΩ and 30 pF in parallel
VRT
Timing resistor voltage
VCT(peak)
Timing capacitor peak voltage
VCT(valley)
Timing capacitor valley voltage
(1)
473
500
527
2.5%
5%
kHz
2.05
2.1
2.4
V
4.1
4.5
5
V
0
0.5
1
V
85
135
ns
2.9
3
3.1
V
2.25
2.35
2.55
V
0
0.2
0.4
V
Specified by design
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF, no load on the outputs,
TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current Sense
ICS(bias)
20
μA
Peak current threshold
1.9
2
2.1
V
Overcurrent threshold
2.4
2.5
2.6
V
75
110
ns
Current sense bias current
Current sense to output delay
4
0 V < CS < 2.5 V, 0 V ADS < 2.5 V
0 V ≤ CS ≤ 2.3 V, DELAB = DELCD = REF
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF, no load on the outputs,
TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Soft Start/Shutdown
ISOURCE
Soft-start source current
SS/DISB = 3 V, CS = 1.9 V
–40
–35
–30
μA
ISINK
Soft-start sink current
SS/DISB = 3 V, CS = 2.6 V
325
350
375
μA
0.44
0.5
0.56
V
Soft-start/disable comparator threshold
Adaptive Delay Set (ADS)
ADS = CS = 0 V
0.45
0.5
0.55
ADS = 0 V, CS = 2 V
1.9
2
2.1
ADS = CS = 0 V
450
560
620
ns
ADS bias current
0 V < ADS < 2.5 V, 0 V < CS < 2.5 V
–20
20
μA
VOH
High-level output voltage (all outputs)
IOUT = –10 mA, VDD to output
250
420
mV
VOL
Low-level output voltage (all outputs)
IOUT = 10 mA
150
270
mV
tR
Rise time (2)
CLOAD = 100 pF
20
35
ns
tF
Fall time (2)
CLOAD = 100 pF
20
35
ns
DELAB/DELCD output voltage
tDELAY
Output delay (2)
(3)
V
Output
(2)
(3)
Specified by design
Output delay is measured between OUTA and OUTB or between OUTC and OUTD. Output delay is defined as shown in the following
figure, where:
tf(OUTA) = falling edge of OUTA signal
tr(OUTB) = rising edge of OUTB signal
tPERIOD
OUTA
OUTA
tDELAY = tf(OUTC) – tf(OUTA)
tDELAY = tf(OUTB) – tf(OUTA)
OUTB
OUTC
Same applies to OUTB and OUTD
Same applies to OUTC and OUTD
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF, no load on the outputs,
TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7
0.85
1.05
V
0
0.85%
1.5%
70
120
PWM Comparator
EAOUT to RAMP input offset voltage
RAMP = 0 V, DELAB = DELCD = REF
Minimum phase shift (4)
(OUTA to OUTC, OUTB to OUTD)
RAMP = 0 V, EAOUT = 650 mV
tDELAY
Delay (5)
(RAMP to OUTC, RAMP to OUTD)
0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB = DELCD = REF
IR(bias)
RAMP bias current
RAMP < 5 V, CT = 2.2 V
–5
IR(sink)
RAMP sink current
RAMP = 5 V, CT = 2.6 V
11
(4)
(5)
5
19
ns
μA
mA
Minimum phase shift is defined as:
t f (OUTC) – t f (OUTA)
t f (OUTC) – t f (OUTB)
F = 180 ×
or F = 180 ×
tPERIOD
tPERIOD
Space
Space
where:
tf(OUTA) = falling edge of OUTA signal
tf(OUTB) = falling edge of OUTB signal
tf(OUTC) = falling edge of OUTC signal
tf(OUTD) = falling edge of OUTD signal
tPERIOD = period of OUTA or OUTB signal
Space
Output delay is measured between OUTA and OUTB or between OUTC and OUTD. Output delay is defined as shown in the following
figure, where:
tf(OUTA) = falling edge of OUTA signal
tr(OUTB) = rising edge of OUTB signal
tPERIOD
OUTA
OUTA
tDELAY = tf(OUTC) – tf(OUTA)
tDELAY = tf(OUTB) – tf(OUTA)
OUTB
OUTC
Same applies to OUTB and OUTD
6
Same applies to OUTC and OUTD
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TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ADS
11
I
Adaptive delay set. Sets the ratio between the maximum and minimum programmed output delay dead time.
CS
12
I
Current-sense input for cycle-by-cycle current limiting and for overcurrent comparator
CT
7
I
Oscillator timing capacitor for programming the switching frequency. The oscillator charges CT via a
programmed current.
DELAB
9
I
Delay programming between complementary outputs. DELAB programs the dead time between switching of
output A and output B.
DELCD
10
I
Delay programming between complementary outputs. DELCD programs the dead time between switching of
output C and output D.
EAOUT
2
I/O
EAP
20
I
Noninverting input to the error amplifier. Keep below 3.6 V for proper operation.
EAN
1
I
Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
GND
5
–
Ground for all circuits except the output stages
OUTA
18
O
OUTB
17
O
OUTC
14
O
OUTD
13
O
PGND
16
–
Output-stage power ground
RAMP
3
I
Inverting input of the PWM comparator
REF
4
O
5-V ± 1.2% 5-mA voltage reference. For best performance, bypass with a 0.1-μF low-ESR low-ESL capacitor
to ground. Do not use more than 1 μF of total capacitance on this pin.
RT
8
I
Oscillator timing resistor for programming the switching frequency
SS/DISB
19
I
Soft start/disable. This pin combines two independent functions.
SYNC
6
I/O
VDD
15
I
Error amplifier output
The four outputs are 100-mA CMOS drivers and are optimized to drive FET driver circuits such as the
UCC27424 or gate-drive transformers.
Oscillator synchronization. This pin is bidirectional.
Power-supply input. VDD must be bypassed with a minimum of a 1-μF low-ESR low-ESL capacitor to ground.
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FUNCTIONAL BLOCK DIAGRAM
IRT
RT
8
CT
7
Q
8(IRT)
15
D S Q
OSC
Q
Q
D SQ
18
DELAY A
VDD
OUTA
R
RAMP
6
PWM
Comparator
3
2
D
EAP
Error
Amp
20
No Load
Comparator
+
+
EAN
S
DELAY C
+
Current Sense
Comparator
Q
OUTB
12
+
Overcurrent
Comparator
IRT
Q
S
Q
R
13
OUTD
16
PGND
11
ADS
4
REF
19
5
GND
0.5 V
+
11 V/9 V
Disable
Comparator
0.5 V
REF
Reference OK
Comparator
+
4V
HI = ON
10(IRT)
+
REF
RT
DELCD
UVLO Comparator
HI = ON
RT
10
Adaptive Delay
Set Amplifier
+
REF
OUTC
0.5 V/0.6 V
2.5 V
SS
17
14
DELAY D
R Q
1
2V
CS
DELAY B
DELAB
+
0.8 V
EAOUT
R Q
9
+
SYNC
VREF
8 × IRT
IRT
CT
CLOCK
2.5 V
S
Q
+
CT
R
SYNC
0.2 V
CLOCK
+
Figure 1. Oscillator Block Diagram
8
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REF
0.5 V
TO DELAY A
AND DELAY B
BLOCKS
75 kΩ
100 kΩ
CS
DELAB
100 kΩ
ADS
REF
75 kΩ
TO DELAY C
AND DELAY D
BLOCKS
DELCD
Figure 2. Adaptive Delay Setting Block Diagram
REF
Bussed Current
From ADS Circuit
3.5 V
DELAB/CD
From Pad
Delayed
Clock
Signal
2.5 V
Clock
Figure 3. Delay Block Diagram (One Delay Block Per Outlet)
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DETAILED PIN DESCRIPTIONS
Adaptive Delay Set (ADS)
This function sets the ratio between the maximum and minimum programmed output-delay dead time. When the
ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs
when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2 V (the peakcurrent threshold); ADS changes the output voltage on the delay pins DELAB and DELCD by Equation 1:
VDEL = [0.75 × (VCS – VADS)] + 0.5 V
(1)
(1)
where VCS and VADS are in volts. ADS must be limited to between 0 V and 2.5 V and must be less than or equal
to CS. DELAB and DELCD are clamped to a minimum of 0.5 V.
Current Sense (CS)
CS is the inverting input of the current-sense comparator and the noninverting input of the overcurrent
comparator and the ADS amplifier. The current-sense signal is used for cycle-by-cycle current limiting in peakcurrent mode control, and for overcurrent protection in all cases with a secondary threshold for output shutdown.
An output disable initiated by an overcurrent fault also results in a restart cycle, called soft stop, with full soft
start.
Oscillator Timing Capacitor (CT)
The oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak voltage of
2.35 V. The approximate oscillator period is calculated by Equation 2:
tOSC = [(5 × RT × CT)/48] + 120 ns
(2)
(2)
where CT is in farads, RT is in Ω, and tOSC is in seconds. CT can range from 100 pF to 880 pF.
NOTE
A large CT and a small RT combination results in extended fall times on the CT waveform.
The increased fall time increases the SYNC pulse duration, hence limiting the maximum
phase shift between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum
duty cycle of the converter (see Figure 1).
Delay Programming Between Complementary Outputs (DELAB, DELCD)
DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time
between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the
external bridge. The UCC2895N allows the user to select the delay, during which the resonant switching of the
external power stages takes place. Separate delays are provided for the two half bridges to accommodate
differences in resonant-capacitor charging currents. The delay in each stage is set according to Equation 3:
tDELAY = [(25 × 10–12 × RDEL)/VDEL] + 25 ns
(3)
(3)
where VDEL is in volts, RDEL is in ohms, and tDELAY is in seconds. DELAB and DELCD can source approximately
1 mA maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay
is defeated by tying DELAB and/or DELCD to REF. For optimum performance, keep stray capacitance on these
pins at less than 10 pF.
Error Amplifier (EAOUT, EAP, EAN)
EAOUT is connected internally to the noninverting input of the PWM comparator and the no-load comparator.
EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages
when EAOUT falls below 500 mV, and allows the outputs to turn on again when EAOUT rises above 600 mV.
EAP is the noninverting input and the EAN is the inverting input to the error amplifier.
10
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Output MOSFET Drivers (OUTA, OUTB, OUTC, OUTD)
The four outputs are 100-mA CMOS drivers and are optimized to drive MOSFET driver circuits. OUTA and
OUTB are fully complementary, assuming no programming delay. They operate near 50% duty cycle and onehalf the oscillator frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power
stage. OUTC and OUTD drive the other half-bridge circuit and have the same characteristics as OUTA and
OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB.
NOTE
Changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB
requires other than the nominal 50% duty ratio on OUTC and OUTD during those
transients.
Power Ground (PGND)
To keep output switching noise from critical analog circuits, the UCC2895-Q1 has two different ground
connections. PGND is the ground connection for the high-current output stages. Both GND and PGND must be
electrically tied together. Also, because PGND carries high current, board traces must be low-impedance.
Inverting Input of the PWM Comparator (RAMP)
This pin receives either the CT waveform in voltage control and average-current-mode control or the current
signal (plus slope compensation) in peak-current-mode control.
Voltage Reference (REF)
The 5 V ± 1.2% reference supplies power to internal circuitry, and can also supply up to 5 mA to external loads.
The reference is shut down during undervoltage lockout (UVLO) but is operational during all other disable
modes. For best performance, bypass with a 0.1-μF low-ESR low-ESL capacitor to GND. Do not use more than
1 μF of total capacitance on this pin to ensure the stability of the internal reference.
Oscillator Timing Resistor (RT)
The oscillator operates by charging an external timing capacitor (CT) with a fixed current programmed by RT. RT
current is calculated by Equation 4:
IRT(A) = 3 V / RT (Ω)
(4)
(4)
RT can range from 40 kΩ to 120 kΩ. Soft-start charging and discharging currents are also programmed by IRT
(see Figure 1).
Analog Ground (GND)
This pin is the ground for all internal circuits except the output stages.
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Soft Start/Disable (SS/DISB)
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the UVLO threshold. In the case of REF being pulled
below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal MOSFET switch.
If an overcurrent fault is sensed (CS = 2.5 V), a soft stop is initiated. In this mode, SS/DISB sinks a constant
current of 10 × IRT. The soft stop continues until SS/DISB falls below 0.5 V. When any of these faults is detected,
all outputs are forced to ground immediately.
NOTE
If SS/DISB is forced below 0.5 V, the pin starts to source current equal to IRT. The only
time the device switches into low IDD current mode is when the device is in UVLO.
Soft-Start Mode: After a fault or disable condition has passed, VDD is above the start threshold, or SS/DISB
falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start mode. The pin then sources current equal to
IRT. A user-selected resistor-and-capacitor combination on SS/DISB determines the soft-start time constant.
NOTE
SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin
voltage during both soft-start, soft-stop, and disable conditions.
Oscillator Synchronization (SYNC)
This pin is bidirectional (see Figure 1). When used as an output, SYNC can be used as a clock, which is the
same as the internal clock of the device. When used as an input, SYNC overrides the internal oscillator of the
device and acts as its clock signal. This bidirectional feature allows synchronization of multiple power supplies.
Also, the SYNC signal internally discharges the CT capacitor and any filter capacitors that are present on the
RAMP pin. The internal SYNC circuitry is level-sensitive, with an input-low threshold of 1.9 V and an input-high
threshold of 2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the SYNC
pulse duration.
Chip Supply (VDD)
This is the input pin to the chip. VDD must be bypassed with a minimum of 1-μF low-ESR low-ESL capacitor to
ground.
12
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APPLICATION INFORMATION
Programming DELAB, DELCD, and ADS
The UCC2895N allows the user to set the delay between switch commands within each leg of the full-bridge
power circuit according to Equation 5:
tDELAY = [(25 × 10–12 × RDEL)/VDEL] + 25 ns
(5)
From Equation 5, VDEL is determined in conjunction with the desire to use (or not use) the ADS feature from
Equation 6:
VDEL = [0.75 × (VCS – VADS)] + 0.5 V
(6)
Figure 4 illustrates the resistors needed to program the delay periods and the ADS function.
UCC2895
9
DELAB
10
DELCD
CS
12
ADS
11
RDELAB
RDELCD
Figure 4. Programming Adaptive Delay Set
The ADS feature allows the user to vary the delay times between switch commands within each of the two legs
of the converter. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a
resistive divider from CS through ADS to GND to set VADS as shown in Figure 1. From Equation 6 for VDEL, if
ADS is tied to GND then VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load
increases. In this condition, the maximum value of VDEL is 2 V.
If ADS is connected to a resistive divider between CS and GND, the term (VCS – VADS) becomes smaller,
reducing the level of VDEL. This decreases the amount of delay modulation. In the limit of ADS tied to CS,
VDEL = 0.5 V, and no delay modulation occurs. Figure 5 shows the delay time versus load for varying adaptivedelay-set feature voltages (VADS).
In the case of maximum delay modulation (ADS = GND), when the circuit goes from light load to heavy load, the
variation of VDEL is from 0.5 V to 2 V. This causes the delay times to vary by a 4:1 ratio as the load is changed.
The ability to program an adaptive delay is a desirable feature, because the optimum delay time is a function of
the current flowing in the primary winding of the transformer and can change by a factor of 10:1 or more as
circuit loading changes. Reference [5] describes the many interrelated factors for choosing the optimum delay
times for the most-efficient power conversion, and illustrates an external circuit to enable adaptive delay set
using the UC3879. Implementing this adaptive feature is simplified in the UCC2895-Q1 controller, giving the user
the ability to tailor the delay times to suit a particular application with a minimum of external parts.
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13
UCC2895-Q1
SLUS783C – MAY 2008 – REVISED AUGUST 2012
www.ti.com
A = VADS/VCS
RDELAY = 10 kW
A = 1.0
tdelay - Dela y Time - ns
500
400
A = 0.8
300
A = 0.6
200
A = 0.4
A = 0.2
A = 0.1
100
0
0.5
1.0
1.5
2.0
2.5
VCS - Current Sense Voltage - V
Figure 5. Delay Time Under Varying ADS Voltages
CLOCK
RAMP
and
COMP
PWM
Signal
OUTA
OUTB
OUTC
OUTD
Figure 6. Timing Diagram (No Output Delay Shown, COMP to RAMP Offset Not Included)
14
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SLUS783C – MAY 2008 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS
OUTPUT DELAY
vs
DELAY RESISTANCE
OSCILLATOR FREQUENCY
vs
TIMING CAPACITANCE
2000
1600
VCS = 0 V
1800
1400
1200
1000
800
600
VCS = 2 V
fsw - Switc hing Frequency - kHz
1600
400
1200
RT = 47 kW
1000
800
600
400
200
RT = 100 kW
200
RT = 82 kW
0
0
0
20
30
10
RDEL – Delay Resistor – kW
1000
CT – Timing Capacitance - pF
Figure 7.
Figure 8.
EAOUT TO RAMP OFFSET
vs
TEMPERATURE
AMPLIFIER GAIN AND PHASE MARGIN
vs
FREQUENCY
1.00
200
100
Gain
80
160
0.95
Gain - dB
VOFFSET - EA OUT to RAMP Offset - V
100
40
0.90
120
60
80
40
Phase
Margin
0.85
0.80
-55
40
20
0
-35
-15
5
25
45
65
TA - Temperature - °C
85
105
125
Phase Margin - Degrees
tDELAY – Output Delay - ns
RT = 62 kW
1400
1
10
100
10k
100k
1k
1M
fOSC - Oscillator Frequenc y - Hz
Figure 9.
0
10M
Figure 10.
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UCC2895-Q1
SLUS783C – MAY 2008 – REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
INPUT CURRENT
vs
OSCILLATOR FREQUENCY
9
INPUT CURRENT
vs
OSCILLATOR FREQUENCY
13
No Output Loading
0.1-nF Output Loads
12
VDD = 15 V
VDD = 15 V
11
7
IDD - Operating Current - mA
IDD - Operating Current - mA
8
VDD = 17 V
6
10
9
VDD = 17 V
8
7
VDD = 12 V
6
5
VDD = 10 V
5
VDD = 10 V
VDD = 12 V
4
0
400
800
4
1200
1600
0
400
800
1200
1600
fOSC - Oscillator Frequenc y - kHz
fOSC - Oscillator Frequenc y - kHz
Figure 11.
Figure 12.
REFERENCES
1. M. Dennis, A Comparison Between the BiCMOS UCC2895 Phase Shift Controller and the UC3875
(SLUA246)
2. L. Balogh, The Current-Doubler Rectifier: An Alternative Rectification Technique For Push-Pull and Bridge
Converters (SLUA121)
3. W. Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM
Controller (SLUA107)
4. L. Balogh, The New UC3879 Phase-Shifted PWM Controller Simplifies the Design of Zero Voltage Transition
Full-Bridge Converters (SLUA122)
5. L. Balogh, Design Review: 100 W, 400 kHz, dc-to-dc Converter with Current Doubler Synchronous
Rectification Achieves 92% Efficiency, Unitrode Power Supply Design Seminar Manual, SEM-1100, 1996,
Topic 2.
6. UC3875 Phase Shift Resonant Controller data sheet (SLUS229)
7. UC3879 Phase Shift Resonant Controller data sheet (SLUS230)
8. Configuring the UCC2895 for Direct Control Driven Synchronous Rectification (SLUU109)
9. S. Mappus, UCC2895 OUTC/OUTD Asymetric Duty Cycle Operation (SLUA275)
10. S. Mappus, Current Doubler Rectifier Offers Ripple Current Cancellation (SLUA323)
11. S. Mappus, Control Driven Synchronous Rectifiers In Phase Shifted Full Bridge Converters (SLUA287)
16
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UCC2895-Q1
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SLUS783C – MAY 2008 – REVISED AUGUST 2012
REVISION HISTORY
Changes from Revision B (July 2012) to Revision C
Page
•
Changed TJ from –40ºC to –55ºC ......................................................................................................................................... 2
•
Changed TJ from –40ºC to –55ºC ......................................................................................................................................... 3
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17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC2895QDWRQ1
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC2895Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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