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UCC29002, UCC29002-1, UCC39002
SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
UCC2900x, UCC39002 Advanced 8-Pin Load-Share Controller
1 Features
3 Description
•
The UCC39002 device is an advanced, highperformance, and low-cost load share controller that
provides all necessary functions to parallel multiple
independent power supplies or DC-to-DC modules.
Targeted for high-reliability applications in server,
workstation, telecom, and other distributed power
systems, the controller is suitable for N+1 redundant
systems or high current applications where off-theshelf power supplies must be paralleled.
1
•
•
•
•
•
•
•
•
•
High Accuracy, Better Than 1% Current Share
Error at Full Load
High-Side or Low-Side (GND Reference) CurrentSense Capability
Ultra-Low Offset Current Sense Amplifier
Single Wire Load Share Bus
Full Scale Adjustability
Intel® SSI Load Share Specification Compliant
Disconnect from Load Share Bus at Stand-By
Load Share Bus Protection Against Shorts to GND
or to the Supply Rail
8-Pin MSOP Package Minimizes Space
Lead-Free Assembly
2 Applications
•
•
•
•
Modules With Remote-Sense Capability
Modules With Remote-Sense Capability
Modules With Remote-Sense Capability
In Conjunction With the Internal Feedback E/A of
OEM Power Supply Units
The BiCMOS UCC39002 is based on the automatic
master or slave architecture of the UC3902 and
UC3907 load share controllers. The device provides
better than 1% current share error between modules
at full load by using a very low offset post-packagetrimmed current sense amplifier and a high-gain
negative feedback loop. And with the amplifier’s
common-mode range of 0 V to the supply rail, the
current sense resistor, RSHUNT, can be placed in
either the GND return path or in the positive output
rail of the power supply.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC29002
SOIC (8)
4.90 mm × 3.91 mm
UCC29002-1
VSSOP (8)
3.00 mm × 3.00 mm
UCC39002
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Low-Side Current-Sensing Application
V+
RADJ
S−
CSO
8
2
CS+
LS
7
3
VDD
EAO
6
4
GND
ADJ
5
LOAD
SYSTEM+−
POWER
SUPPLY
WITH
REMOTE
SENSE
CS−
SYSTEM+
UCC39002
1
LS BUS
S+
RSHUNT
V−
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC29002, UCC29002-1, UCC39002
SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
Overview ................................................................... 7
Functional Block Diagram ......................................... 7
Feature Description................................................... 7
Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information .......................................... 14
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (August 2007) to Revision I
•
2
Page
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
5 Pin Configuration and Functions
D or DGK Package
8-Pin SOIC or VSSOP
Top View
CS−
CS+
VDD
GND
1
8
2
7
3
6
4
5
P Package
8-Pin PDIP
Top View
CSO
LS
EAO
ADJ
CS−
CS+
VDD
GND
1
8
2
7
3
6
4
5
CSO
LS
EAO
ADJ
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ADJ
5
O
Adjust amplifier output. This is the buffered output of the error amplifier block to adjust output voltage of the
power supply being controlled. This pin must always be connected to a voltage equal to or greater than
VEAO + 1 V.
CS–
1
I
Current sense amplifier inverting input.
CS+
2
I
Current sense amplifier noninverting input.
CSO
8
O
Current sense amplifier output.
EAO
6
O
Output for load share error amplifier. (Transconductance error amplifier.)
GND
4
–
Ground. Reference ground and power ground for all device functions. Return the device to the low current
sense−path of the converter.
LS
7
I/O
VDD
3
I
Load share bus. Output of the load share bus driver amplifier.
Power supply providing bias to the device. Bypass with a good quality, low ESL 0.1-µF to 1-µF, maximum,
capacitor as close to the VDD pin and GND as possible.
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: UCC29002 UCC39002
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UCC29002, UCC29002-1, UCC39002
SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VDD
Supply voltage, current limited
−0.3
15
V
VDD
Supply voltage, voltage source
−0.3
13.5
V
VCS+, VCS−
Input voltage, current sense amplifier
–0.3
VDD + 0.3
V
VCSO
Current sense amplifier output voltage
−0.3
VDD
V
VLS
Load share bus voltage
−0.3
VDD
V
10
mA
Supply current (IDD + IZENER)
VEAO +1 V < VADJ ≤ VDD
VADJ
Adjust pin input voltage
IADJ
Adjust pin sink current
6
mA
TJ
Operating junction temperature range
−55
150
°C
Tstg
Storage temperature
−65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
4.575
13.5
V
Current sense amplifier output voltage
0
11.8
V
VLS
Load share bus voltage
0
VDD – 1.7
IADJ
Adjust pin sink current
VDD
Supply voltage, voltage source
VCSO
4.55
V
mA
6.4 Thermal Information
UCC2900x/UCC39002
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
P (PDIP)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
111.9
168.0
54.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.6
61.9
43.9
°C/W
RθJB
Junction-to-board thermal resistance
52.6
88.8
31.2
°C/W
ψJT
Junction-to-top characterization parameter
12.9
7.3
21.6
°C/W
ψJB
Junction-to-board characterization parameter
52.0
87.2
31.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Product Folder Links: UCC29002 UCC39002
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SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
6.5 Electrical Characteristics
VDD = 12 V, 0°C < 70°C for the UCC39002, –40°C < TA < 105°C for the UCC29002 and UCC29002-1, TA = TJ (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.5
3.5
mA
13.5
14.25
15
V
4.175
4.375
4.575
0.2
0.375
0.55
GENERAL
Supply current
LS with no load, ADJ = 5 V
VDD clamp voltage
IDD = 6 mA
UNDERVOLTAGE LOCKOUT
Start-up voltage (1)
Hysteresis
V
CURRENT SENSE AMPLIFIER
TA = 25 C, VIC = 0.5 V or 11.5 V, VCSO = 5 V
−100
100
µV
VIO
Input offset voltage
±10
µV/ C
AV
Gain
75
90
dB
CMRR
Common-mode rejection ratio
75
90
dB
IBIAS
Input bias current (CS+, CS−)
VOH
High-level output voltage (CSO)
0.1 V ≤ ([CS+] − [CS−]) ≤ 0.4 V, IOUT_CSO = 0 mA
VOL
Low-level output voltage (CSO)
−0.4 V ≤ ([CS+] − [CS−]) ≤ 0.1 V, IOUT_CSO = 0 mA
IOH
High-level output current (CSO)
VCSO = 10 V
IOL
Low-level output current (CSO)
VCSO = 1 V
GBW
Gain bandwidth product (2)
Overtemperature variation
−0.6
0.6
µA
10.7
11
11.8
V
0
0.1
0.15
−1
−1.5
1
1.5
mA
2
MHz
V
mA
LOAD SHARE DRIVER (LS)
VRANGE
Input voltage range
VOUT
Output voltage
VOL
Low-level output voltage
0
10
VCSO = 1 V
0.995
1
1.005
VCSO = 10 V
0.995
10
1.005
0.1
0.15
VCSO = 0 V, IOUT_LS = 0 mA
0
V
V
V
VDD −
1.7
V
−1
−1.5
V
(2)
VOH
High-level output voltage
IOUT
Output current
0.5 V ≤ VLS ≤ 10 V
ISC
Short-circuit current
VLS = 0 V, VCSO = 10 V
−10
−20
VSHTDN
Driver shutdown threshold
VCS− − VCS+
0.3
0.5
0.7
VCSO = 2 V, VEAO = 2 V, VLS = VDD, VADJ = 5 V
0
5
10
VCSO = 2 V, VEAO = 2 V, VLS = 0 V, VADJ = 5 V
0
5
10
3.5
3.65
3.8
mA
V
LOAD SHARE BUS PROTECTION
IADJ
Adjust amplifier current
µA
ERROR AMPLIFIER
VOH
High-level output voltage
IOUT_EAO = 0 mA
gM
Transconductance
IEAO = ± 50 µA
IOH
High-level output current
VLS − VCSO = 0.4 V, REAO = 2.2 kΩ
14
0.7
0.85
V
mS
1
mA
ADJ BUFFER
VIO
Input offset voltage (2)
VADJ = 1.5 V, VEAO = 0 V
ISINK
Sink current
VADJ = 5.0 V, VEAO = 0 V
TA = 25°C
ISINK
Sink current
0°C ≤ TA ≤ 70°C
−40°C ≤ TA ≤ 105°C
(1)
(2)
−60
VADJ = 5.0 V,
VEAO = 2.0 V,
LS = floating
mV
0
5
10
3.6
3.95
4.3
3.45
3.95
4.45
3.35
3.95
4.55
µA
mA
Enables the load share bus at start-up.
Ensured by design. Not production tested.
Copyright © 2001–2016, Texas Instruments Incorporated
Product Folder Links: UCC29002 UCC39002
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6.6 Typical Characteristics
Figure 1. Resultant Load Current Sharing Accuracy, as Measured Across Shunts from the Output of Each
Module
6
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SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
7 Detailed Description
7.1 Overview
The UCC39002 is an advanced, high-performance, low-cost load-share controller that provides all the necessary
functions to parallel multiple independent power supplies and modules. The UCC39002 can easily parallel
currently available and popular synchronous buck converters, such as those designed with the TPS40050
controller.
7.2 Functional Block Diagram
Current Sense
Amp
CS− 1
8 CSO
Disconnect Switch
+
+
CS+
2
Enable
and
Bias OK
VBIAS
VDD
7 LS
Load Share Bus
Receiver +
3
100 kΩ
Error Amp
+
gM
13.5 V
to
15 V
GND
Load Share
Bus Driver
6 EAO
3V
4
Fault
Protection
Start Up
and
Adjust
Logic
3V
5 ADJ
Adjust Amp
+
500Ω
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Differential Current Sense Amplifier (CS+, CS−, CSO)
The UCC39002 features a high-gain and high-precision amplifier to measure the voltage across a low-value
current sense resistor. Because the amplifier is fully uncommitted, the current sense gain is user programmable.
The extremely low input offset voltage of the UCC39002 current sense amplifier makes it suitable to measure
current information across a low value sense resistor. Furthermore, the input common mode range includes
ground and the positive supply rail of the UCC39002 (VDD). Accordingly, the current sense resistor can be placed
in the ground return path or in the positive output rail of the power supply VO as long as VO ≤ VDD. The current
sense amplifier is not unity gain stable and must have a minimum gain of three.
7.3.2 Load Share Bus Driver Amplifier (CSO)
This is a unity-gain buffer amplifier to provide separation between the load share bus voltage and the output of
the current sense amplifier. The circuit implements an ideal diode with virtually 0-V forward voltage drop by
placing the diode inside the feedback loop of the amplifier. The diode function is used to automatically establish
the role of the master module in the system. The UCC39002 which is assigned to be the master uses the load
share bus driver amplifier to copy its output current information on to the load share bus.
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Feature Description (continued)
All slave units, with lower output current levels by definition, have this ideal diode reversed biased (VCSO < VLS).
Consequently, the VCSO and VLS signals will be separated. That allows the error amplifier of the UCC39002 to
compare its respective module’s output current to the master module’s output current and make the necessary
corrections to achieve a balanced current distribution.
Since the bus is always driven by a single load share bus driver amplifier, the number of modules (n) are limited
by the output current capability of the amplifier according to Equation 1:
100 kW ´ IOUT,MIN
n=
VLS,FULL _ SCALE
where
•
•
•
100 kΩ is the input impedance of the LS pin as shown in the block diagram,
IOUT,MIN is given in the data sheet
and VLS,FULL_SCALE is the maximum voltage on the load share bus at full load.
(1)
NOTE
The number of parallel units can be increased by reducing the full scale bus voltage, that
is, by reducing the current sense gain.
7.3.3 Load Share Bus Receiver Amplifier (LS)
The load share bus receiver amplifier is a unity-gain buffer monitoring the load share bus voltage. Its primary
purpose is to ensure that the load share bus is not loaded by the internal impedances of the UCC39002. The LS
pin is already internally compensated and has an internal 15-kHz filter. Adding external capacitance, including
stray capacitance, must be avoided to maintain stability
7.3.4 Error Amplifier (EAO)
As pictured in the block diagram, the UCC39002 employs a transconductance also called gM type error amplifier.
The gM amplifier was chosen because it requires only one pin, the output to be accessible for compensation.
The purpose of the error amplifier is to compare the average, per module current level to the output current of
the respective module controlled by the UCC39002. It is accommodated by connecting the buffered VLS voltage
to its noninverting input and the VCSO signal to its inverting input. If the average per module current, represented
by the load share bus is higher than the module’s own output current, an error signal will be developed across
the compensation components connected between the EAO pin and ground. The error signal is than used by the
adjust amplifier to make the necessary output voltage adjustments to ensure equal output currents among the
parallel operated power supplies.
In case the UCC39002 assumes the role of the master load share controller in the system or it is used in
conjunction with a stand alone power module, the measured current signal on VCSO is approximately equal to the
VLS voltage. To avoid erroneous output voltage adjustment, the input of the error amplifier incorporates a typically
25-mV offset to ensure that the inverting input of the error amplifier is biased higher than the noninverting input.
Consequently, when the two signals are equal, there will be no adjustment made and the initial output voltage set
point is maintained.
7.3.5 Adjust Amplifier Output (ADJ)
A current proportional to the error voltage VEAO on pin 6 is sunk by the ADJ pin. This current flows through the
adjust resistor RADJ and changes the output voltage of the module controlled by the UCC39002. The amplitude of
the current is set by the 500-Ω internal resistor between ground and the emitter of the amplifier’s open collector
output transistor according to Figure 2. The adjust current value is given in Equation 2:
V
IADJ = EAO
500 W
(2)
At the master module VEAO is 0 V, thus the adjust current must be zero as well. This ensures that the output
voltage of the master module remains at its initial output voltage set point at all times.
8
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Feature Description (continued)
Furthermore, at insufficient bias level, during a fault or when the UCC39002 is disabled, the noninverting input of
the adjust amplifier is pulled to ground to prevent erroneous adjustment of the module’s output voltage by the
load share controller.
7.3.6 Enable Function (CS+, CS−)
The two inputs of the current sense amplifier are also used for implementing an ENABLE function. During normal
operation CS− = CS+ and the internal offset added between the CS− voltage and the inverting input of the
enable comparator ensures that the UCC39002 is always enabled. By forcing the CS− pin approximately 0.5 V
above the CS+ pin, the UCC39002 can be forced into a disable mode. While disabled, the UCC39002
disconnects itself from the load share bus and its adjust current is zero.
CS+ 2
+
ENABLE
+
0.5 V
CS− 1
Figure 2. Enable Comparator
7.3.7 Fault Protection
Accidentally, the load share bus might be shorted to ground or to the positive bias voltage of the UCC39002.
These events might result in erroneous output voltage adjustment. For that reason, the load share bus is
continuously monitored by a window comparator as shown in Figure 3.
VDD − 0.7 V
+
LS 7
FAULT
+
R
CSO 8
2R
Figure 3. Fault Protection Comparators
The FAULT signal is handled by the start-up and adjust logic which pulls the noninverting input of the adjust
amplifier low when the FAULT signal is asserted.
7.3.8 Start-Up and Adjust Logic
The start-up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under
these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make
the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states. Similarly, the
driver amplifier of UCC39002 is disabled during these conditions.
In the UCC39002 and UCC29002, during start-up, the load share driver amplifier is disabled by the disconnect
switch and the adjust amplifier is forced to sink the maximum current through the adjust resistor. This operating
mode ensures that the module controlled by the UCC39002 will be able to quickly engage in sharing the load
current since its output will be adjusted to a sufficiently high voltage immediately at turnon. Both the load share
driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of the
average per module current level represented by the LS bus voltage. The UCC29002 and UCC29001 does not
have this logic at start up. In this way, the UCC2900x does not adjust the output of the module to its maximum
adjustment range at turn on and engages load sharing at more moderate rate.
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Feature Description (continued)
In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver
and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the
CS+ and CS− pins or when the bias voltage is below the minimum operating voltage.
7.3.9 Bias and Bias OK Circuit (VDD)
The UCC39002 is built on a 15-V, high-performance BiCMOS process. Therefore, the maximum voltage across
the VDD and GND pins (pin 3 and 4 respectively) is limited to 15 V. The recommended maximum operating
voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the bias
voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor. The
current into the VDD pin must be limited to 10 mA as listed in Absolute Maximum Ratings.
The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such,
must be placed as close to the device pins (VDD and GND) as possible, using a good-quality, low-ESL capacitor,
including trace length. The device is optimized for a capacitor value of 0.1 µF to 1 µF.
VBIAS
(Internal Bias)
VDD 3
14.2 V
GND 4
4.375 V
+
Bias_OK
Figure 4. VDD Clamp and Bias Monitor
The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable
function with a 4.375-V threshold. While VDD < 4.375 V the load share control functions are disabled. While this
might be inconvenient for some low voltage applications it is necessary to ensure high accuracy. The load share
accuracy is dependent on working with relatively large signal amplitudes on the load share bus. If the internal
offsets, current sense error and ground potential difference between the UCC39002 controllers are comparable
in amplitude to the load share bus voltage, they can cause significant current distribution error in the system. The
maximum voltage on the load share bus is limited approximately 1.7 V below the bias voltage level (VDD) which
would result in an unacceptably low load share bus amplitude therefore poor accuracy at low VDD levels. To
circumvent this potential design problem, the UCC39002 does not operate below the above mentioned 4.375-V
bias voltage threshold. If the system does not have a suitable bias voltage available to power the UCC39002, TI
recommends using an inexpensive charge pump which can generate the bias voltage for all the UCC39002s in
the load share system.
The maximum VDD of the UCC39002 is 15 V. For higher-voltage applications, use the application solution as
recommended in Figure 5. A Zener clamp on the VDD pin is provided internally so the device can be powered
from higher voltage rails using a minimum number of external components.
The CSA inputs must be adjusted so as to not exceed their absolute maximum voltage ratings.
10
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SLUS495I – SEPTEMBER 2001 – REVISED MAY 2016
Feature Description (continued)
LOAD CURRENT DIRECTION
VOUT+
R ADJ
SNS+
RBIAS1
LOAD
POWER SUPPLY
OUTPUT
SYSTEM
GROUND
UCC39002
1
CS−
CSO
8
2
CS+
LS
7
3
VDD
EAO
6
LS BUS
TO OTHER
UCC39002
DEVICES
CCOMP
R BIAS2
C BIAS
4
GND
ADJ
5
RCOMP
POWER SUPPLY
OUTPUT
SNS−
RSHUNT
VOUT−
Copyright © 2016, Texas Instruments Incorporated
Figure 5. High Voltage Application
The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power
modules for load sharing.
7.3.10 Paralleling the Power Modules
• VOUT = nominal output voltage of the modules to be paralleled
• IOUT(max) = maximum output current of each module to be paralleled
• ΔVADJ = maximum output voltage adjustment range of the power modules to be paralleled
• N = number of modules
NOTE
The power modules to be paralleled must be equipped with true remote sense or access
to the feedback divider of the module’s error amplifier.
A typical high side application for a single module is shown in Figure 6 and is repeated for each module to be
paralleled.
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Feature Description (continued)
R SHUNT
0.005Ω
V+
P1
R15
274Ω
V−
C13 1 nF
TP11
R16 16.2 kΩ
POWER MODULE
TP12
R13
274Ω
U1
UCC39002
RSENSE
200Ω
1 CS− CSO 8
RADJUST
R18
1 kΩ
2 CS+
Q1
LS 7
C12
V+
TP13
REAO
475Ω
SB2
Load
V−
3 VDD EAO 6
R19
47 kΩ
C11
0.47 µF
R14
16.2 kΩ
S+
4 GND
CEAO
47µF
ADJ 5
S1
S−
Load Share Bus
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Figure 6. Typical High-Side Application for Single Power Module
In Figure 6, P1 represents the output voltage terminals of the module, S1 represents the remote sense terminals
of the module, and a signal on the SB2 terminal will enable the disconnect feature of the device. The load share
bus is the common bus between all of the paralleled load share controllers. VDD must be decoupled with a goodquality ceramic capacitor returned directly to GND.
7.3.11 Measuring the Loop of the Modules
Using the configuration in Figure 7, measure the unity-gain crossover frequency of the power modules to be
paralleled. A typical resultant bode plot is shown in Figure 8.
VIN
+
+
VOUT
+
DC−DC Module
Load
50 W
+
SENSE
XFRMR
Source
Out
Channel
A
Channel
B
Network Analyzer
Figure 7. Unity-Gain Crossover Frequency Measurement Connection Diagram
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Feature Description (continued)
40
30
20
Gain − dB
10
0
−10
UNITY GAIN
CROSSOVER
FREQUENCY
fCO = 40 Hz
−20
−30
−40
1
10
100
1000
f − Frequency − Hz
Figure 8. Power Module Bode Plot
7.4 Device Functional Modes
7.4.1 Fault
This condition occurs if the load share bus is shorted high or low. Under this condition the device responds by
pulling the inverting input of the adjust amplifier low. See Fault Protection for details.
7.4.2 Start-Up
During start up the load share driver amplifier is disabled and the adjust amplifier is forced to sink the maximum
current through the adjust resistor. See Start-Up and Adjust Logic for details.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC39002 is an advanced, high-performance load-share controller that provides all the necessary functions
to parallel multiple independent power supplies or DC-to-DC modules. This load-share circuit is based upon the
automatic master or slave architecture used in the UC3902 and the UC3907 load-share controllers providing
better than 1% current-share error between the modules at full load.
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8.2 Typical Application
RSHUNT
V+
RADJ
S+
UCC39002
POWER SUPPLY
WITH
REMOTE SENSE
1 CS−
CSO 8
2 CS+
LS 7
3 VDD
EAO 6
4 GND
ADJ 5
S−
V−
RSHUNT
V+
RADJ
S+
UCC39002
POWER SUPPLY
WITH
REMOTE SENSE
1 CS−
CSO 8
2 CS+
LS 7
LOAD
3 VDD
EAO 6
4 GND
ADJ 5
S−
V−
RSHUNT
V+
RADJ
S+
UCC39002
POWER SUPPLY
WITH
REMOTE SENSE
1 CS−
CSO 8
2 CS+
LS 7
3 VDD
EAO 6
4 GND
ADJ 5
S−
V−
Figure 9. Typical High-Side Current-Sensing Application
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Typical Application (continued)
8.2.1 Design Requirements
In order to properly configure and design with the UCC39002 it necessary to gather requirements for the
following system level performance metrics.
1. Required system level stability to include phase margin (φm), gain margin (gm), and bandwidth (fbw). Typical
values are φm = 45 °, gm = 10 dB, and fbw= fs/10 where fs is the switching frequency.
2. Required current sharing accuracy. Typically this is 1 %.
8.2.2 Detailed Design Procedure
The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power
modules for load sharing.
8.2.2.1 The Shunt Resistor
Selection of the shunt resistor is limited by its voltage drop at maximum module output current. This voltage drop
should be much less than the voltage adjustment range of the module shown in Equation 3:
IOUT(max) ´ RSHUNT
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