UCC2946TPWRQ1

UCC2946-Q1 www.ti.com ................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 MICROPROCESSOR SUPERVISOR WITH WATCHDOG TIMER FEATURES 1 • • • • • • • • Qualified for Automotive Applications Fully Programmable Reset Threshold Fully Programmable Reset Period Fully Programmable Watchdog Period 2% Accurate Reset Threshold Input Voltage Down to 2 V Input 18-µA Maximum Input Current Reset Valid Down to 1 V DESCRIPTION The UCC2946 is designed to provide accurate microprocessor supervision, including reset and watchdog functions. During power up, the device asserts a reset signal RES with VDD as low as 1 V. The reset signal remains asserted until the VDD voltage rises and remains above the reset threshold for the reset period. Both reset threshold and reset period are programmable by the user. The UCC2946 is also resistant to glitches on the VDD line. Once RES has been deasserted, any drops below the threshold voltage need to be of certain time duration and voltage magnitude to generate a reset signal. These values are shown in Figure 1. An I/O line of the microprocessor may be tied to the watchdog input (WDI) for watchdog functions. If the I/O line is not toggled within a set watchdog period, programmable by the user, WDO is asserted. The watchdog function is disabled during reset conditions. The UCC2946 is available in 8-pin TSSOP (PW) package to optimize board space. VDD 8 POWER TO CIRCUITRY 400 nA RP 4 + S Q 3 RES POWER ON RESET + R 1.235 V Q Q S Q R + RTH 2 WP 400 nA 6 + 8−BIT COUNTER A3 + 100 mV + WATCHDOG TIMING WDI 7 EDGE DETECT 1.235 V + S Q R Q 5 WDO A2 CLR A1 A0 CLK 1 GND UDG−02192 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2009, Texas Instruments Incorporated UCC2946-Q1 SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 ................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 105°C (1) TSSOP – PW ORDERABLE PART NUMBER Reel of 3000 UCC2946TPWRQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) PW PACKAGE (TOP VIEW) GND RTH RES RP 1 8 2 7 3 6 4 5 VDD WDI WP WDO TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION GND 1 — Ground reference for the device RES 3 O This pin is high only if the voltage on the RTH has risen above 1.235 V. Once RTH rises above the threshold, this pin remains low for the reset period. This pin asserts low and remains low if the RTH voltage dips below 1.235 V for an amount of time determined by Figure 1. RTH 2 I This input compares its voltage to an internal 1.25-V reference. By using external resistors, a user can program any desired reset threshold. RP 4 I This pin allows the user to program the reset period by adjusting an external capacitor. VDD 8 I Supply voltage for the device WDI 7 I This pin is the input to the watchdog timer. If this pin is not toggled or strobed within the watchdog period, WDO is asserted. WDO 5 O This pin is the watchdog output. This pin is asserted low if the WDI pin is not strobed or toggled within the watchdog period. WP 6 I This pin allows the user to program the watchdog period by adjusting an external capacitor. 2 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 UCC2946-Q1 www.ti.com ................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UCC2946 VIN Input voltage range 10 V IOUT WDO output current 20 mA TJ Junction temperature range –55°C to 150°C Tstg Storage temperature –65°C to 150°C (1) Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C ESD rating, HBM 1500 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal. ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C, 2.1 V ≤ VDD ≤ 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference VDD Operating voltage IDD Supply current VDD(min) Minimum operating voltage (1) 2.1 12 5.5 V 18 µA 1.1 V 1.26 V Reset Section Reset threshold voltage VDD rising 1.17 Threshold hysteresis ILEAK Input leakage current VOH High-level output voltage VOL Low-level output voltage 1.235 15 mV 5 ISOURCE = 2 mA VDD – 0.3 V ISINK = 2 mA 0.1 ISINK = 20 µA, VDD = 1 V 0.4 VDD-to-output delay time VDD = –1 mV/µs Reset period CRP = 64 nF 200 V µs 120 140 nA 320 ms Watchdog Section VIH High-level input voltage, WDI VIL Low-level input voltage, WDI Watchdog period 0.7 × VDD CRP = 64 nF Watchdog pulse width VOH High-level output voltage ISOURCE = 2 mA VOL Low-level output voltage ISINK = 2 mA (1) V 0.3 × VDD 0.96 1.60 2.56 V s 50 ns VDD – 0.3 V 0.1 V Minimum supply voltage where RES is considered valid. Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 3 UCC2946-Q1 SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 ................................................................................................................................................. www.ti.com APPLICATION INFORMATION The UCC2946 supervisory circuit provides accurate reset and watchdog functions for a variety of microprocessor applications. The reset circuit prevents the microprocessor from executing code during undervoltage conditions, typically during power-up and power-down. To prevent erratic operation in the presence of noise, voltage glitches where voltage amplitude and time duration are less than the values specified in Figure 1 are ignored. 200 OVERDRIVE VOLTAGE WITH RESPECT TO RESET THRESHOLD vs DELAY TO OUTPUT LOW ON RESB 180 VTH − Overdrive Voltage − mV 160 140 120 100 80 RT Senses Glitch, RES Goes Low for Reset Period 60 40 20 0 100 Glitches Ignored, RESB Remains High 110 120 130 140 150 TDELAY − Delay Time − µs 160 170 180 Figure 1. The watchdog circuit monitors the microprocessor’s activity, if the microprocessor does not toggle WDI during the programmable watchdog period WDO goes low, alerting the microprocessor’s interrupt of a fault. The WDO pin is typically connected to the non-maskable input of the microprocessor so that an error recovery routine can be executed. 4 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 UCC2946-Q1 www.ti.com ................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 Programming the Reset Voltage and Reset Period The UCC2946 allows the reset trip voltage to be programmed with two external resistors. In most applications, VDD is monitored by the reset circuit, however, the design allows voltages other than VDD to be monitored. Referring to Figure 2, the voltage below which reset is asserted is determined by Equation 1: ) R2Ǔ ǒR1 R2 V RESET + 1.235 (1) To keep quiescent currents low, resistor values in the MΩ range can be used for R1 and R2. A manual reset can be easily implemented by connecting a momentary push switch in parallel with R2. RES is ensured to be low with VDD voltages as low as 1 V. VDD 8 POWER TO CIRCUITRY 400 nA RP 4 + − 1.235 V + CRP RES R Q RTH RESET 3 + − VDD R1 S Q POWER ON RESET Q S 2 R2 Q R uP I/O 8−BIT COUNTER 400 nA WP 6 + CWP A3 + − A2 CLR A1 100 mV + 1.235 V WDI 7 S Q R Q WDO 5 NMI A0 CLK + − WATCHDOG TIMING EDGE DETECT GND 1 UDG−98002 Figure 2. Typical Application Diagram Once VDD rises above the programmed threshold, RES remains low for the reset period defined by Equation 2: TRP = 3.125 × CRP (2) Where TRP is time in milliseconds CRP is capacitance in nanofarads CRP is charged with a precision current source of 400 nA, a high-quality, low-leakage capacitor (such as an NPO ceramic) should be used to maintain timing tolerances. Figure 3 shows the voltage levels and timings associated with the reset circuit. Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 5 UCC2946-Q1 SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 ................................................................................................................................................. www.ti.com TRP RES TRP 5V 0V 5V VDD Monitored by RT 2.5 V Programmed Threshold 1V 0V t1 t2 t3 t4 t5 t6 t7 t1: VDD > 1 V, RES is ensured low. t2: VDD > programmed threshold, RES remains low for TRP. t3: TRP expires, RES pulls high. t4: Voltage glitch occurs, but is filtered at the RTH pin, RES remains high. t5: Voltage glitch occurs whose magnitude and duration is greater than the RTH filter, RES is asserted for TRP. t6: On completion of the TRP pulse the RTH voltage has returned and RES is pulled high. t7: VDD dips below threshold (minus hysteresis), RES is asserted. Figure 3. Reset Circuit Timings 6 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 UCC2946-Q1 www.ti.com ................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 Programming the Watchdog Period The watchdog period is programmed with CWP as shown in Equation 3: TWP = 25 × CWP (3) Where TWP is in milliseconds CWP is in nanofarads A high-quality, low-leakage capacitor should be used for CWP. The watchdog input WDI must be toggled with a high-to-low or low-to-high transition within the watchdog period to prevent WDO from assuming a logic level low. WDO maintains the low logic level until WDI is toggled or RES is asserted. If at any time RES is asserted, WDO assumes a high logic state and the watchdog period be reinitiated. Figure 4 shows the timings associated with the watchdog circuit. TRP VDD RESET 0V TWP VDD WDI 0V VDD WDO 0V t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t1: Microprocessor is reset. t2: WDI is toggled some time after reset, but before TWP expires. t3: WDI is toggled before TWP expires. t4: WDI is toggled before TWP expires. t5: WDI is not toggled before TWP expires and WDO asserts low, triggering the microprocessor to enter an error recovery routine. t6: The microprocessor’s error recovery routine is executed and WDI is toggled, reinitiating the watchdog timer. t7: WDI is toggled before TWP expires. t8: WDI is toggled before TWP expires. t9: RES is momentarily triggered, RES is asserted low for TRP t10: Microprocessor is reset, RES pulls high. t11: WDI is toggled some time after reset, but before TWP expires. t12: WDI is toggled before TWP expires. Figure 4. Watchdog Circuit Timing Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 7 UCC2946-Q1 SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 ................................................................................................................................................. www.ti.com Connecting WDO to RES To provide design flexibility, the reset and watchdog circuits in the UCC2946 have separate outputs. Each output independently drives high or low, depending on circuit conditions explained previously. In some applications, it may be desirable for either the RES or WDO to reset the microprocessor. This can be done by connecting WDO to RES. If the pins try to drive to different output levels, the low output level dominates. Additional current flows from VDD to GND during these states. If the application cannot support additional current (during fault conditions), RES and WDO can be connected to the inputs of an OR gate whose output is connected to the microprocessor’s reset pin. Layout Considerations A 0.1-µF capacitor connected from VDD to GND is recommended to decouple the UCC2946 from switching transients on the VDD supply rail. Because RP and WP are precision current sources, capacitors CRP and CWP should be connected to these pins with minimal trace length to reduce board capacitance. Care should be taken to route any traces with high voltage potential or high speed digital signals away from these capacitors. Resistors R1 and R2 generally have a high ohmic value; traces associated with these parts should be kept short to prevent any transient producing signals from coupling into the high-impedance RTH pin. 8 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 UCC2946-Q1 www.ti.com ................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS INPUT CURRENT vs INPUT VOLTAGE THRESHOLD RESISTANCE vs AMBIENT TEMPERATURE 12.0 1.26 1.25 11.5 1.24 11.0 IDD − Input Current − µA VRTH − Threshold Resistance − V VDD = 5 V 1.23 1.22 10.0 9.5 1.21 1.20 −55 10.5 9.0 −35 −15 5 25 45 65 85 105 125 2 TA − Ambient Temperature − °C Figure 5. 3 4 5 VDD − Input Voltage − V 6 Figure 6. Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2946-Q1 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC2946TPWRQ1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 2946T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of