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Design
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
SLUS161F – APRIL 1999 – REVISED MAY 2020
UCCx813-x Low-Power Economy BiCMOS Current-Mode PWM
1 Features
3 Description
•
•
•
•
•
•
The UCC3813-x device family of high-speed, lowpower integrated circuits contains all of the control
and drive components required for off-line and DC-toDC fixed-frequency current-mode switching power
supplies with minimal parts count.
1
•
•
•
•
100-µA typical starting supply current
500-µA typical operating supply current
Operation to 1 MHz
Internal soft start
Internal fault soft start
Internal leading-edge blanking of the currentsense signal
1-A totem-pole output
70-ns typical response from current-sense to gatedrive output
1.5% Tolerance Voltage Reference
Same Pinout as the UCC3802 device, UC3842
device, and UC3842A device families
These devices have the same pin configuration as
the UC384x device family, and also offer the added
features of internal full-cycle soft start and internal
leading-edge blanking of the current-sense input.
The UCC3813-x device family offers a variety of
package options, temperature-range options, choice
of maximum duty cycle, and choice of critical voltage
levels. Devices with lower reference voltage such as
the UCC3813-3 and UCC3813-5 fit best into battery
operated systems, while the higher reference and the
higher UVLO hysteresis of the UCC3813-2 device
and UCC3813-4 device make these ideal choices for
use in off-line power supplies.
2 Applications
•
•
•
•
•
Switch mode power supplies (SMPS)
DC-DC converters
Power modules
Industrial PSUs
Battery operated PSUs
The UCC2813-x device series is specified for
operation from –40°C to 85°C and the UCC3813-x
device series is specified for operation from 0°C to
70°C.
Device Information(1)
PART NUMBER
UCC2813-x,
UCC3813-x
PACKAGE
BODY SIZE (NOM)
PDIP (8)
6.35 mm × 9.81 mm
SOIC (8)
3.91 mm × 4.90 mm
TSSOP (8)
4.40 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
FB
COMP
CS
2
1
3
7 VCC
UCCx813-1
UCCx813-4
UCCx813-5
Only
Leading Edge
Blanking
1.5 V
Over Current
VCC
OK
REF/2
T Q
S Q
R
4V
Voltage
Reference
Oscillator
6 OUT
S Q
S Q
R
REF
OK
PWM
Latch
R
13.5 V
0.5 V
Full Cycle
Soft Start
Logic
Power
τ=4ms
1V
5 GND
8
4
REF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
SLUS161F – APRIL 1999 – REVISED MAY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 31
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August, 2016) to Revision F
Page
•
Added Notes under Abs Max Section. ................................................................................................................................... 4
•
Changed Power Supply section to reflect power up of the device....................................................................................... 31
Changes from Revision D (May 2013) to Revision E
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision C (August 2010) to Revision D
Page
•
Added temperature range table note to second part of ordering information table for clarity in new datasheet format ........ 3
•
Added TI's general Absolute Maximum Ratings table note to end of ABSOLUTE MAXIMUM RATINGS table.................... 4
•
Added Thermal Information Table. ......................................................................................................................................... 5
•
Added UCCX813-3 to Total variation test condition line containing UCCx813-5 in ELECTRICAL
CHARACTERISTICS table ..................................................................................................................................................... 5
•
Changed part numbers in Dead Time vs CT, RT = 100 k graph in APPLICATION INFORMATION ...................................... 7
•
Changed layout from Unitrode Products datasheet to TI datasheet ...................................................................................... 7
Changes from Revision B (April 2008) to Revision C
Page
•
Added Analog inputs RC and COMP in the Absolute Maximum Ratings table ..................................................................... 4
•
Added clarification to Analog Inputs min-max range in the Absolute Maximum Ratings table .............................................. 4
2
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Copyright © 1999–2020, Texas Instruments Incorporated
Product Folder Links: UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0
UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
www.ti.com
SLUS161F – APRIL 1999 – REVISED MAY 2020
5 Device Comparison Table
MAXIMUM DUTY
CYCLE
REFERENCE
VOLTAGE
TURNON
THRESHOLD
TURNOFF
THRESHOLD
UNIT
100%
5
7.2
6.9
V
UCCx813-1
50%
5
9.4
7.4
V
UCCx813-2
100%
5
12.5
8.3
V
UCCx813-3
100%
4
4.1
3.6
V
UCCx813-4
50%
5
12.5
8.3
V
UCCx813-5
50%
4
4.1
3.6
V
PART NUMBER (1)
UCCx813-0
(1)
The x in the part number refers to the operating temperature range difference between the UCC2813 devices and the UCC3813
devices.
6 Pin Configuration and Functions
N and D Packages
8-Pin PDIP and SOIC
Top View
PW Package
8-Pin TSSOP
Top View
COMP
1
8
REF
COMP
1
8
REF
FB
2
7
VCC
FB
2
7
VCC
CS
3
6
OUT
CS
3
6
OUT
RC
4
5
GND
RC
4
5
GND
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COMP
1
O
COMP is the output of the error amplifier and the input of the PWM comparator. Feedback loop
compensation is applied between this pin and the FB pin.
CS
3
I
CS is the input to the current-sense comparators: the PWM comparator and the overcurrent comparator.
FB
2
I
FB is the inverting input of the error amplifier.
GND
5
—
GND is the reference ground and power ground for all functions of this device.
OUT
6
O
OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET.
RC
4
I
RC is the oscillator timing programming pin. An external resistor and capacitor are applied to this input to
program the switching frequency and maximum duty-cycle.
REF
8
O
REF is the voltage reference for the error amplifier and many other functions, and is the bias source for logic
functions of this device.
VCC
7
I
VCC is the bias-power input for this device. In normal operation, VCC is connected to a voltage source
through a current-limiting resistor.
Copyright © 1999–2020, Texas Instruments Incorporated
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3
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
SLUS161F – APRIL 1999 – REVISED MAY 2020
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MAX
UNIT
VCC voltage (3)
MIN
12
V
VCC current
30
mA
OUT current
±1
A
OUT energy (capacitive load)
20
µJ
6.3 or
VVCC + 0.3 (4)
V
Analog inputs
FB, CS, RC, COMP
Power dissipation at TA < 25°C
–0.3
N package
1
D package
0.65
Lead temperature, soldering (10 s)
W
300
°C
Junction temperature
–55
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
(4)
All voltages are with respect to GND. All currents are positive into the specified terminal.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In normal operation Vcc is powered through a current limit resistor. The resistor must be sized so that the VCC voltage under all
operating conditions is below 12 V but above the turnoff threshold. Absolute maximum of 12 V applies when VCC is driven from a low
impedance source such that ICC does not exceed 30mA. Failure to limit VCC and ICC to these limits may result in permanent damage
of the device. This is further discussed in thePower Supply Recommendations
Whichever is smaller.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VVCC
VCC bias supply voltage from a low impedance source
11
V
IVCC
Supply bias current
25
mA
VOUT
Gate driver output voltage
IOUT
Average OUT pin current
IREF
REF pin output current
Voltage on analog pins
fOSC
(1)
4
–0.1
FB, CS, RC, COMP
–0.1
VVCC
V
20
mA
5
mA
6 or
VVCC (1)
Oscillator frequency
1
V
MHz
Whichever is smaller.
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UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
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SLUS161F – APRIL 1999 – REVISED MAY 2020
7.4 Thermal Information
UCCx813-x
THERMAL METRIC (1)
P (PDIP)
D (SOIC)
PW (TSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
50.9
107.5
153.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.3
49.3
38.4
°C/W
RθJB
Junction-to-board thermal resistance
28.1
48.7
83.8
°C/W
ψJT
Junction-to-top characterization parameter
17.6
6.6
2.2
°C/W
ψJB
Junction-to-board characterization parameter
28
48
82
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Unless otherwise stated, these specifications apply for –40°C ≤ TA ≤ 85°C for the UCC2813-x device; 0°C ≤ TA ≤ 70°C for the
UCC3813-x device, TJ = TA; VVCC = 10 V (1); RT = 100 kΩ from REF to RC; CT = 330 pF from RC to GND; 0.1-µF capacitor
from VCC to GND; 0.1-µF capacitor from VREF to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.925
5
5.075
3.94
4
4.06
10
30
UNIT
REFERENCE
Output voltage
Load regulation
Total variation
Output noise voltage
Long term stability
TJ = 25°C, I = 0.2 mA, UCCx813-[0,1,2,4]
TJ = 25°C, I = 0.2 mA, UCCx813-[3,5]
0.2 mA < I < 5 mA
UCCx813-[0,1,2,4]
(2)
UCCx813-[3,5] (2)
4.84
5
5.1
3.84
4
4.08
10 Hz ≤ f ≤ 10 kHz, TJ = 25°C (3)
TA = 125°C, 1000 hours
70
(3)
Output short circuit
mV
V
µV
5
–5
V
mV
–35
mA
OSCILLATOR
Oscillator frequency
Temperature stability
UCCx813-[0,1,2,4] (4)
40
46
52
UCCx813-[3,5] (4)
26
31
36
See note
(3)
Amplitude peak-to-peak
kHz
2.5%
2.25
Oscillator peak voltage
2.4
2.55
2.45
V
V
ERROR AMPLIFIER
Input voltage
VCOMP = 2.5 V; UCCx813-[0,1,2,4]
2.42
2.5
2.56
VCOMP = 2 V; UCCx813-[3,5]
1.92
2
2.05
Input bias current
–2
Open loop voltage gain
60
COMP sink current
VFB = 2.7 V, VCOMP = 1.1 V
COMP source current
VFB = 1.8 V, VCOMP = VREF – 1.2 V
Gain-bandwidth product
See note
2
80
0.4
–0.2
(3)
µA
dB
2.5
–0.5
V
–0.8
2
mA
mA
MHz
PWM
Maximum duty cycle
Minimum duty cycle
(1)
(2)
(3)
(4)
UCCx813-[0,2,3]
97%
99%
100%
UCCx813-[1,4,5]
48%
49%
50%
VCOMP = 0 V
0%
Adjust VCC above the start threshold before setting at 10 V.
Total variation includes temperature stability and load regulation.
Ensured by design. Not 100% tested in production.
Output frequency for the UCCx813-[0,2,3] device is the oscillator frequency. Output frequency for the UCCx813-[1,4,5] device is one-half
the oscillator frequency.
Copyright © 1999–2020, Texas Instruments Incorporated
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5
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
SLUS161F – APRIL 1999 – REVISED MAY 2020
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Electrical Characteristics (continued)
Unless otherwise stated, these specifications apply for –40°C ≤ TA ≤ 85°C for the UCC2813-x device; 0°C ≤ TA ≤ 70°C for the
UCC3813-x device, TJ = TA; VVCC = 10 V(1); RT = 100 kΩ from REF to RC; CT = 330 pF from RC to GND; 0.1-µF capacitor
from VCC to GND; 0.1-µF capacitor from VREF to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.1
1.65
1.8
0.9
1
UNIT
CURRENT SENSE
Gain
See note
Maximum input signal
(5)
VCOMP = 5 V
(6)
Input bias current
–200
CS blank time
V/V
1.1
V
200
nA
150
ns
50
100
1.32
1.55
1.7
V
0.45
0.9
1.35
V
I = 20 mA, all parts
0.1
0.4
I = 200 mA, all parts
0.35
0.9
I = 50 mA, VVCC = 5 V, UCCx813-[3,5]
0.15
0.4
0.7
1.2
0.15
0.4
1
1.9
I = –50 mA, VVCC = 5 V, UCCx813-[3,5]
0.4
0.9
Rise time
CL = 1 nF
41
70
ns
Fall time
CL = 1 nF
44
75
ns
Overcurrent threshold
COMP to CS offset
VCS = 0 V
OUTPUT
OUT low level
I = 20 mA, VCC = 0 V, all parts
I = –20 mA, all parts
VVCC –
OUT
OUT high Vsat
I = –200 mA, all parts
V
V
UNDERVOLTAGE LOCKOUT
Start threshold
Stop threshold
(7)
(7)
UCCx813-0
6.6
7.2
7.8
UCCx813-1
8.6
9.4
10.2
UCCx813-[2,4]
11.5
12.5
13.5
UCCx813-[3,5]
3.7
4.1
4.5
UCCx813-0
6.3
6.9
7.5
UCCx813-1
6.8
7.4
8
UCCx813-[2,4]
7.6
8.3
9
UCCx813-[3,5]
Start to stop hysteresis
3.2
3.6
4
UCCx813-0
0.12
0.3
0.48
UCCx813-1
1.6
2
2.4
UCCx813-[2,4]
3.5
4.2
5.1
UCCx813-[3,5]
0.2
0.5
0.8
V
V
V
SOFT START
COMP rise time
VFB = 1.8 V, Rise from 0.5 V to REF – 1 V
4
ms
Start-up current
VVCC < start threshold
0.1
0.23
mA
Operating supply current
VFB = 0 V, VCS = 0 V, VRC = 0 V
0.5
1.2
mA
12
13.5
15
V
0.5
1
OVERALL
VCC internal Zener voltage
(7)
ICC = 10 mA
VCC internal Zener voltage minus
UCCx813-[2,4]
start-threshold voltage (7)
A=
(5)
(6)
(7)
6
DVCOMP
DVCS
V
0 £ VCS £ 0.8 V
Gain is defined by:
.
Parameter measured at trip point of latch with FB at 0 V.
Start threshold, stop threshold, and Zener-shunt thresholds track one another.
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UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
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SLUS161F – APRIL 1999 – REVISED MAY 2020
7.6 Typical Characteristics
4.00
80
3.98
60
135
3.96
3.94
VREF (V)
Phase
90
Phase (º)
Gain (dB)
40
Gain
45
20
3.92
3.90
3.88
3.86
0
0
3.84
3.82
-20
10k
10k
100k
1M
10M
4
4.2
Frequency (Hz)
C001
5
5.2
VCC (V)
ILOAD = 0.5 mA
4.8
5.4
5.6
5.8
6
1000
10
Oscillator Freq. (kHz)
1000
Oscillator Freq. (kHz)
4.6
Figure 2. UCC3813-[3,5]: VREF vs VCC
Figure 1. Error Amplifier Gain and Phase Response
0p
F
100
20
0p
33
0p
F
F
100
10
0p
F
20
0p
F
33
0p
F
1n
F
10
10
1n
10
100
1000
F
10
RT (kΩ)
100
1000
RT (kΩ)
Figure 3. UCC3813-[0,1,2,4]: Oscillator Frequency vs
RT and CT
Figure 4. UCC3813-[3,5]: Oscillator Frequency vs RT and CT
100
50
99.5
F
p
00
=1
pF
30
48
pF
00
=3
96.5
=2
97
48.5
CT
F
p
00
pF
30
=3
pF
00
=2
CT
97.5
=1
98
49
CT
CT
98.5
CT
Maximum Duty Cycle (%)
49.5
99
CT
Maximum Duty Cycle (%)
4.4
47.5
96
47
95.5
46.5
95
10
100
1000
10
100
1000
Oscillator Frequency (kHz)
Oscillator Frequency (kHz)
Figure 5. UCC3813-[0,2,3]: Maximum Duty Cycle vs
Oscillator Frequency
Figure 6. UCC3813-[1,4,5]: Maximum Duty Cycle vs
Oscillator Frequency
Copyright © 1999–2020, Texas Instruments Incorporated
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7
UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5
UCC3813-0, UCC3813-1, UCC3813-2, UCC3813-3, UCC3813-4, UCC3813-5
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Typical Characteristics (continued)
16
8
14
7
12
C
VC
=
C
1nF
8V,
C=
8
VC
6
Loa
0V, No
C=1
4
2
0
0
100
200
300
400
500
600
700
800
C
VC
nF
=8
3
VCC =
2
No Load
0
=1
1
V,
4
d
VC
VCC = 8V,
VC
5
ICC (mA)
ICC (mA)
10
nF
1
V,
6
F
1n
V,
10
o Loa
10V, N
d
, No Load
VCC = 8V
1
0
0
900 1000
100
200
Oscillator Frequency (kHz)
300
400
500
600
700
800
900 1000
Oscillator Frequency (kHz)
Figure 7. UCC3813-0: ICC vs Oscillator Frequency
Figure 8. UCC3813-5: ICC vs Oscillator Frequency
500
1.1
Dead Time (ns)
400
350
UCCx813/5
300
250
200
UCCx813/1/2/4
150
100
COMP to CS Offset (Volts)
450
1.0
0.9
0.8
Slope = 1.8mV/°C
0.7
0.6
50
0
100
200
300
400
500
600
700
CT (pF)
RT = 100 kΩ
Figure 9. Dead Time vs CT
8
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800
900
1000
0
-55-50
-25
0
25
50
75
100
125
Temperature (°C)
VCS = 0 V
Figure 10. COMP To CS Offset vs Temperature
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8 Detailed Description
8.1 Overview
The UCCx813-x family of high-speed, low-power integrated circuits contain all of the control and drive functions
required for off-line and DC-to-DC fixed-frequency current-mode switched-mode power supplies having minimal
external parts count. The UCCx813-x family is a cost-reduced version of the UCCx80x family, with some
relaxation of certain parameter limits. See Differences Between the UCC3813 and UCC3800 PWM Families for
more information.
These devices have the same pin configuration as the UCx84x and UCx84xA families, and also offer the added
features of internal full-cycle soft start and internal leading-edge blanking of the current-sense input. The
UCCx813-x devices are pin-out compatible with the UCx84x and UCx84xA families, however they are not plug-in
compatible. In general, the UCCx813-x requires fewer external components and consumes less operating
current.
8.2 Functional Block Diagram
FB
COMP
CS
2
1
3
7 VCC
UCCx813-1
UCCx813-4
UCCx813-5
Only
Leading Edge
Blanking
1.5 V
Over Current
VCC
OK
REF/2
T Q
S Q
R
4V
Voltage
Reference
Oscillator
6 OUT
S Q
S Q
R
REF
OK
PWM
Latch
R
13.5 V
0.5 V
Full Cycle
Soft Start
Logic
Power
τ=4ms
1V
5 GND
8
4
REF
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8.3 Feature Description
The UCCx813-x family offers numerous advantages that allow the power supply design engineer to meet their
challenging requirements.
Features include:
• Bi-CMOS process
• Low starting supply current: typically 100 µA
• Low operating supply current: typically 500 µA
• Pinout compatible with UC3842 and UC3842A families
• 5-V operation (UCCx813-[3,5])
• Leading-edge blanking of current-sense signal
• On-chip soft start for start-up and fault recovery
• Internal full cycle restart delay
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9
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Feature Description (continued)
•
•
•
•
•
•
1.5% voltage reference
Up to 1-MHz oscillator
Low self-biasing output during UVLO
70-ns response from current sense to output
Very few external components required
Available in surface-mount and PDIP packages
8.3.1 Detailed Pin Descriptions
8.3.1.1 COMP
COMP is the output of the error amplifier and the input of the PWM comparator. Unlike earlier-generation
devices, the error amplifier in the UCCx813-x device family is a true low-output-impedance 2-MHz operational
amplifier. As such, the COMP terminal both sources and sinks current. However, the error amplifier is internally
current limited, so zero duty cycle may be commanded by externally forcing COMP to GND.
The UCCx813-x device family features built-in full cycle soft start at power up and after fault recovery, and no
external components are necessary. Soft start is implemented as a rising clamp on the COMP voltage,
increasing from 0 V to 5 V in 4 ms.
8.3.1.2 CS
CS is the input to the current-sense comparators. The UCCx813-x current sense is significantly different from its
predecessor. The UCCx813-x device family has two different current-sense comparators: the PWM comparator
and an overcurrent comparator. The overcurrent comparator is intended only for fault sensing, and exceeding the
overcurrent threshold causes a soft-start cycle. The earlier UC3842 family current-sense input connects to only
the PWM comparator.
The UCCx813-x device family contains digital current-sense filtering, which disconnects the CS terminal from the
current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This
digital filtering, also called leading-edge blanking, prevents false triggering due to leading edge noises which
means that in most applications, no analog filtering (external R-C filter) is required on CS. Compared to an
external RC filter technique, the leading-edge blanking provides a smaller effective CS-to-OUT delay. However,
the minimum non-zero on-time of the OUT signal is determined by the leading-edge-blanking time and the CS-toOUT propagation delay. The gain of the current sense amplifier is typically 1.65 V/V in the UCCx813-x family
versus typically 3 V/V in the UC3842 family. Connect CS directly to MOSFET source current sense resistor.
8.3.1.3 FB
FB is the inverting input of the error amplifier. For best stability, keep the FB lead length as short as possible and
FB stray capacitance as small as possible. At 2 MHz, the gain-bandwidth of the error amplifier is twice that of
earlier UC3842 family devices, and feedback design techniques are identical.
8.3.1.4 GND
GND is the signal reference ground and power ground for all functions on this part. TI recommends separating
the signal return paths and the high current gate driver path so that signals are not affected by the switching
current.
8.3.1.5 OUT
OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak
currents exceeding ±750 mA (up to ±1 A). OUT is actively held low when VCC is below the UVLO threshold. This
feature eliminates the need for a gate-to-source bleeder resistor associated with the MOSFET gate drive.
The high-current power driver consists of CMOS FET output devices, which can switch all of the way to GND
and all of the way to VCC. The output provides very smooth rising and falling waveforms, providing very low
impedances to overshoot and undershoot which means that in many cases, external Schottky clamp diodes may
not be necessary on the output. Finally, no external gate voltage clamp is necessary with the UCCx813-x as the
on-chip Zener diode automatically clamps the output to VCC.
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Feature Description (continued)
8.3.1.6 RC
RC is the oscillator timing pin. For fixed frequency operation, set the timing-capacitor charging current by
connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best
performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate
ground traces for the timing capacitor and all other functions.
The UCCx813-x’s oscillator allows for operation to 1 MHz versus 500 kHz with the UC3842 family. Both devices
make use of an external resistor to set the charging current for the capacitor, which determines the oscillator
frequency. For the UCCx813-[0,1,2,4], use Equation 1.
1.5
f =
R´C
where
•
•
•
ƒ is the oscillator frequency in hertz (Hz)
R is the timining resistance in ohms (Ω)
C is the timing capacitance in farads (F)
(1)
For the UCCx813-[3,5], use Equation 2.
1.0
f =
R´C
(2)
The recommended timing resistance is from 10 kΩ to 200 kΩ and timing capacitance is from 100 pF to 1000 pF.
Never use a timing resistor less than 10 kΩ.
The two equations are different due to different reference voltages. The peak-to-peak amplitude of the oscillator
waveform is 2.45 V versus 1.7 V in UC3842 family. For best performance, keep the timing capacitor lead to GND
as short as possible. TI recommends separate ground traces for the timing capacitor and all other pins. The
maximum duty cycle for the UCCx813-[0,2,3] is approximately 99%; the maximum duty cycle for the UCCx813[1,4,5] is approximately 49%. The duty cycle cannot be easily modified by adjusting RT and CT, unlike the
UC3842A family. The maximum duty cycle limit is set by the ratio of the external oscillator charging resistor RT
and the internal oscillator discharge transistor on-resistance, like the UC3842. However, maximum duty cycle
limits less than 90% (for the UCCx813-[0,2,3]) and less than 45% (for the UCCx813-[1,4,5]) can not reliably be
set in this manner. For better control of maximum duty cycle, consider using the UCCx807.
8.3.1.7 REF
REF is the voltage reference for the error amplifier and also for many other functions on the IC. REF is also used
as the logic power supply for high speed switching logic on the IC. The UCCx813-[0,1,2,4] have a 5-V reference
and the UCCx813-[3,5] have a 4-V reference. Both have ±1.5% accuracy at 25°C versus ±2% in the UC3842
family. The REF output short-circuit current is lower at 5 mA, compared to 30 mA in the UC3842 family.
For reference stability and to prevent noise problems with high speed switching transients, it is important to
bypass REF to GND with a ceramic capacitor as close to the pins as possible. A minimum of 0.1-µF ceramic is
required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference. An
electrolytic capacitor can also be used in addition to the ceramic capacitor.
When VCC is greater than 1 V and less than the UVLO on-threshold, REF is internally pulled to ground through
a 5-kΩ resistor which means that REF can be used as a logic output indicating power-system status.
8.3.1.8 VCC
VCC is the power input connection for this device. In normal operation, VCC is powered through a current
limiting resistor to a low-impedance source. To prevent noise problems, bypass VCC to GND with a 0.1-µF
ceramic capacitor in parallel as close to the VCC pin as possible. An electrolytic capacitor can also be used in
addition to the ceramic capacitor.
Although quiescent VCC current is very low, total supply current is higher, depending on the OUT current. Total
VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the switching
frequency f and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 3.
IOUT = Qg ´ f
(3)
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Feature Description (continued)
The UCCx813-x has a lower VCC (supply voltage) clamp of 13.5 V typical versus 30 V on the UC3842. For
applications that require a higher VCC voltage, a resistor must be placed in series with VCC to increase the
source impedance. The maximum value of this resistor is calculated with Equation 4.
Rmax=
VIN:min; -VVCC:max;
IVCC +Qg ×f
where
•
•
•
•
VIN(min) is the minimum voltage that is used to supply VCC
VVCC(max) is the maximum VCC clamp voltage of the controller
IVCC is the IC supply current without considering the gate driver current
Qg is the external power MOSFET gate charge, and f is the switching frequency
(4)
Additionally, the UCCx813-x has an on-chip Zener diode to limit VCC to 13.5 V, which also limits the maximum
OUT voltage. If the bias-supply source is always lower than 12 V, it may be connected directly to VCC. With
UVLO thresholds at 4.1 V and 3.6 V for the UCCx813-3 and UCCx813-5, respectively, 5-V PWM operation is
now possible.
8.3.2 Undervoltage Lockout (UVLO)
The UCCx813-[2,4] devices feature undervoltage lockout protection circuits for controlled operation during powerup and power-down sequences. Both the supply voltage (VVCC) and the reference voltage (VREF) are monitored
by the UVLO circuitry. During UVLO, an active-low, self-biasing totem-pole output structure is also incorporated
for enhanced power switch protection.
Undervoltage lockout thresholds for the UCCx813-[2,3,4,5] devices are different from the previous generation of
UCx84[2,3,4,5] PWM controllers. The thresholds are optimized for two groups of applications: off-line power
supplies and DC-DC converters. See Table 1 for the specific thresholds for each device.
Table 1. UVLO Level Comparison Table
DEVICE
VON (V)
VOFF (V)
UCCx813-0
7.2
6.9
UCCx813-1
9.4
7.4
UCCx813-[2,4]
12.5
8.3
UCCx813-[3,5]
4.1
3.6
The UCCx813-[2,4] feature typical UVLO thresholds of 12.5 V for turnon and 8.3 V for turnoff, providing 4.3 V of
hysteresis.
For low voltage inputs, which include battery and 5-V applications, the UCCx813-[3,5] turn on at 4.1 V and turn
off at 3.6 V with 0.5 V of hysteresis.
The UCCx813-[0,1] have UVLO thresholds optimized for automotive and battery applications.
During UVLO, the device draws approximately 100 µA of supply current. Once VCC crosses the turnon
threshold, the IC supply current increases typically to about 500 µA, over an order of magnitude lower than
bipolar counterparts. Figure 11 indicates the supply current behavior at the relative UVLO turnon and turnoff
thresholds, not including average OUT current.
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Figure 11. IC Supply Current at UVLO
8.3.3 Self-Biasing, Active Low Output
The self-biasing, active-low clamp circuit shown in Figure 12 eliminates the potential for problematic MOSFET
turnon. As the PWM output voltage rises while in UVLO, the P-channel device drives the larger N-channel switch
ON, which clamps the output voltage low. Power to this circuit is supplied by the externally rising gate voltage, so
full protection is available regardless of the device's supply voltage during undervoltage lockout.
2V
VCC = OPEN
VOUT
VCC = 2 V
VCC = 0 V
VCC = 1 V
1V
50 mA
100 mA
IOUT
Figure 12. Internal Circuit Holding OUT Low During
UVLO
Figure 13. OUT Voltage vs OUT Current During
UVLO
8.3.4 Reference Voltage
The traditional 5-V band-gap-derived reference voltage of the UC3842 family can be also found on the
UCCx813-[0,1,2,4] devices. However, the reference voltage of the UCCx813-[3,5] devices is 4 V. This change
was necessary to facilitate operation with input supply voltages below 5 V. Many of the reference voltage
specifications are similar to the UC3842 devices although the test conditions have been changed, indicative of
lower-current PWM applications. Similar to their bipolar counterparts, the BiCMOS devices internally pull the
reference voltage low during UVLO, which can be used as a logic status indication.
The 4-V reference voltage on the UCCx813-[3,5] is derived from the supply voltage (VVCC) and requires about
0.5 V of headroom to maintain regulation. Whenever VVCC is below approximately 4.5 V, the reference voltage
also drops outside of its specified range for normal operation. The relationship between VVCC and VREF during
this excursion is shown in Figure 14.
The noninverting input to the error amplifier is tied to one-half of the controller's reference voltage (VREF). This
input is 2 V on the UCCx813-[3,5] and 2.5 V on the higher reference voltage parts: the UCCx813-[0,1,2,4].
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4.0 V
UCC3813-x
3.9 V
REF
VREF
3.8 V
R
TO
3.7 V
E/A+
R
3.6 V
0.1 µF
BYPASS
3.5 V
3.6 V 3.8 V 4.0 V 4.2 V 4.4 V 4.6 V 4.8 V 5.0 V
VCC
Figure 14. UCC3813-3 REF Output vs VVCC
Figure 15. Required Reference Bypass Minimum
Capacitance
8.3.5 Oscillator
The UCCx813-x oscillator generates a sawtooth waveform on RC. The rise time is set by the time constant of RT
and CT. The fall time is set by CT and an internal transistor on-resistance of approximately 130 Ω. During the fall
time, the output is OFF and the maximum duty cycle is reduced below 50% or 100%, depending on the part
number. Larger values for the timing capacitor increase the discharge time and reduce the maximum duty cycle
and frequency slightly, as seen in Figure 5 and Figure 6 .
REF
8
0.2V
+
RT
R
+
RC
4
Q
S
2.65V
CT
Figure 16. Oscillator Equivalent Circuit
The oscillator section of the UCCx813-x BiCMOS family has few similarities to the UC3842 type — other than
single-pin programming. It does still use a resistor to the reference voltage and capacitor to ground to program
the oscillator frequency up to 1 MHz. Timing component values must be changed because a much lower
charging current is desirable for low-power operation. Several characteristics of the oscillator have been
optimized for high-speed, noise-immune operation. The oscillator peak-to-peak amplitude has been increased to
2.45 V typical versus 1.7 V on the UC3842 family. The lower oscillator threshold has been dropped to
approximately 0.2 V while the upper threshold remains fairly close to the original 2.8 V at approximately 2.65 V.
Discharge current of the timing capacitor has been increased to nearly 20-mA peak as opposed to roughly 8 mA.
This can be represented by approximately 130 Ω in series with the discharge switch to ground. The higher
current is necessary to achieve brief dead times and high duty cycles with high-frequency operation. Practical
applications can use these devices to a 1-MHz switching frequency.
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1000
800
2.65 V
600
400
ƒ (kHz)
VCT
0.2 V
0V
200
CT = 100 p
100
80
60
fCONV
CT = 180 p
CT = 270 p
CT = 390 p
CT = 470 p
40
20
0
20
40
60
80
100
120
RT (kW)
Figure 17. Oscillator Waveform at RC
Figure 18. Oscillator Frequency vs RT For Several
CT
8.3.6 Synchronization
Synchronization of these PWM controllers is best obtained by the universal technique shown in Figure 19. The
device oscillator is programmed to free-run at a frequency about 20% lower than that of the synchronizing
frequency. A brief positive pulse is applied across the 50-Ω resistor to force synchronization. Typically, a 1-V
amplitude pulse of 100-ns width is sufficient for most applications.
The controller can also be synchronized to a pulse-train applied directly to the oscillator RC pin. The device
internally pulls low at this node once the upper oscillator threshold is crossed. This 130-Ω impedance to ground
remains active until the voltage on RC is lowered below 0.2 V. External synchronization circuits must
accommodate these conditions.
REF
RT
RC
CT
SYNC
§ 50
Figure 19. Synchronizing the Oscillator
8.3.7 PWM Generator
Maximum duty cycle is higher for these devices than for their UC384[2,3,4,5] predecessors. This is primarily due
to the higher ratio of timing capacitor discharge-to-charge current, which can exceed one hundred-to-one in a
typical BiCMOS application. Attempts to program the oscillator maximum duty cycle much below the specified
range, by adjusting the timing component values of RT and CT, must be avoided. There are two reasons to
refrain from this design practice. First, the device's high discharge current would necessitate higher charging
current than necessary for programming, defeating the purpose of low power operation. Second, a low-value
timing resistor may prevent the capacitor from discharging to the lower threshold and initiating the next switching
cycle.
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8.3.8 Minimum Off-Time Adjustment (Dead-Time Control)
Dead time is the term used to describe the ensured OFF time of the PWM output during each oscillator cycle. It
is used to ensure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements,
and prevent saturation. The dead time of the UCCx813-x PWM family is determined by the internal 130-Ω
discharge impedance and the timing capacitor value. Larger capacitance values extend the dead time whereas
smaller values results in higher maximum duty cycles for the same operating frequency. A curve for dead time
versus timing capacitor values is provided in Figure 20. Further increasing the dead time is possible by adding a
low-value resistor between the RC pin and the timing components, as shown in Figure 21. The dead time
increases with increasing discharge resistor value to about 470 Ω as indicated from the curve in Figure 22.
Higher resistances must be avoided as they can decrease the dead time and reduce the oscillator peak-to-peak
amplitude. Sinking too much current (1 mA) by reducing RT will freeze the oscillator OFF by preventing discharge
to the lower comparator threshold voltage of 0.2 V. Adding this discharge control resistor has several impacts on
the oscillator programming. First, it introduces a DC offset to the capacitor during the discharge interval – but not
the charging interval of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude.
Because of the reduced peak-to-peak amplitude, the exact value of CT may require adjustment to obtain the
correct oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the timing
and discharge resistor values because these are readily available in finer numerical increments.
200
180
REF
160
RT
Td (ns)
140
RD
120
RC