UCC3884DG4

UCC2884 UCC3884 www.ti.com............................................................................................................................................. SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008 Frequency Foldback Current Mode PWM Controller FEATURES 1 • • • • • • • • • Frequency Foldback Reduces Operating Frequency Under Fault Conditions Accurate Programmable Volt-Second Clamp Programmable Maximum Duty Cycle Clamp Oscillator Synchronization Overcurrent Protection Shutdown With Full Soft Start Wide Gain Bandwidth Amplifier (GBW > 2.5 MHz) Current Mode Operation Precision 5-V Reference DESCRIPTION The UCC3884 is a high performance current mode PWM controller intended for single ended switch mode power supplies. The chip implements a frequency foldback scheme that decreases the oscillator frequency as the output voltage falls below a programmed value. This technique decreases the average output current sourced into a low impedance load which can occur during an output short circuit or overload condition. Excessive short circuit current is more prevalent in high frequency converters where the propagation delay and switch turn-off time forces a minimum attainable duty cycle. An accurate volt-second clamp limits the duty cycle during line or load transient conditions which could otherwise saturate the transformer. The volt-second clamp may also be used with an external overvoltage protection circuit to handle fault conditions such as current sense disconnect or current transformer saturation. The frequency foldback, volt-second clamp, cycle-by-cycle current limit, and overcurrent shutdown provide a rich set of protection features for use in peak current-mode pulse width modulators. OSCILLATOR SYNCHRONIZATION 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2008, Texas Instruments Incorporated UCC2884 UCC3884 SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008............................................................................................................................................. www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT Supply voltage 15 V Output sink current 1 Output source current All other pins 6 Storage temperature –65 TO 150 Junction temperature –40 TO 150 Lead temperature (soldering, 10 sec) (1) A 0.5 V °C 300 Currents are positive into, negative out of the specified terminal. ORDERING INFORMATION TJ (1) PACKAGED DEVICES (1) SOP (D) PDIP(N) -40°C to 85°C UCC2884D (16) UCC2884N (16) 0°C to 70°C UCC3884D (16) UCC3884N (16) Both the D and N packages are available taped and reeled (indicated by the TR suffix on the device type e.g., UCC2884DTR) CONNECTION DIAGRAMS N or D Package (Top View) 2 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 UCC2884 UCC3884 www.ti.com............................................................................................................................................. SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008 Block Diagram Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 Submit Documentation Feedback 3 UCC2884 UCC3884 SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply for TA = -40°C to 85°C for the UCC2884, and 0°C to 70°C for the UCC3884, CT = 220 pF, RON = 53 kΩ, ROFF = 38 kΩ, VOUT = VREF, VVS = 0 V, CSS = 2.5 nF, VDD = 11 V, Output no load, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.86 V 5-V Reference VREF IREF = 0 mA 5 5.14 Line regulation VDD = 10 V to 12 V 1 10 Load regulation 0 < IREF < 5 mA 1 20 Short circuit VREF = 0 V 15 45 mV mA Oscillator Accuracy VOUT = VREF 360 400 440 Foldback frequency VOUT = 0.75 V 200 230 260 5 5.2 0.0 0.4 CLKSYNC output high 4.8 CLKSYNC output low CLKSYNC sink current CLKSYNC = 1 V CLKSYNC source current CLKSYNC = 3 V CLKSYNC input threshold CLKSYNC from 5 V to 0 V (edge detect) 1.2 2.2 kHz V mA –0.2 0.1 3.0 3.5 V 1 µA 2.43 2.5 2.57 50 90 dB MHz 2.5 Error Amplifier IB Total bias current; regulating level FB voltage FB = COMP –1 AVO (1) GBW F = 100 kHz Output source current FB = 2.3 V, COMP = 2.5 V Output sink current FB = 2.7 V, VCOMP = 1 V VOL IO = 100 µA VOL IO = –100 µA Minimum duty cycle FB = 3 V, CS = 0 V Maximum duty cycle FB = 0 V, CS = 0 V 2.5 5 –0.6 –1.2 0.250 1.5 V mA 0.3 0.9 2.7 3.1 3.5 75% 78% 81% V PWM 0% Current Sense Input bias current (CS) 3.0 CS shutdown threshold 1.235 CS shutdown hysteresis 1.3 1.365 20 CS over current threshold µA V mV 0.95 1 1.05 –10 –20 –30 10 20 30 V Current/FAULT Soft start charge current Soft start discharge current VOL (1) 4 0 50 Soft start complete threshold 3.6 4 4.4 Soft start restart threshold 0.4 0.5 0.6 µA mV V Specified by design. Not 100% tested in production. Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 UCC2884 UCC3884 www.ti.com............................................................................................................................................. SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, these specifications apply for TA = -40°C to 85°C for the UCC2884, and 0°C to 70°C for the UCC3884, CT = 220 pF, RON = 53 kΩ, ROFF = 38 kΩ, VOUT = VREF, VVS = 0 V, CSS = 2.5 nF, VDD = 11 V, Output no load, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX VVS = 1.4 V, TA = 40°C to 85°C 50% 60% 70% VVS = 1.4 V, TA = 0°C to 70°C 52% 57% 67% VVS = 3.6 V, TA = –40°C to 85°C 20.5% 22.0% 25.5% VVS = 3.6 V, TA = 0°C to 70°C 20.5% 22.0% 23.5% UNIT Volt Second Clamp Duty cycle IB VVS = 3.7 V –1 1 µA Output Stage Output low saturation Output low saturation IOUT = 100 mA 0.5 0.9 IOUT = –50 mA 0.5 0.9 IOUT = 200 mA (2) 1.9 UVLO output low saturation IOUT = 20 mA, VDD = 0 V 0.7 1.2 Rise time CL = 1 nF 50 70 Fall time CL = 1 nF 30 50 V ns Undervoltage Lockout Turn-on threshold voltage 8.4 8.9 9.4 Hysteresis 200 600 1000 9.5 10 10.5 V mV Startup Regulator Regulated VDD voltage VDD override threshold 10.7 V Overall VDD range (2) 14.5 IDD (run) f = 400 kHz 2 IDD startup current VDD = 5.4 V 100 VDD clamp IDD = 10 mA 12 5 13.5 V 10 mA 250 µA 15 V Specified by design. Not 100% tested in production. Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 Submit Documentation Feedback 5 UCC2884 UCC3884 SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008............................................................................................................................................. www.ti.com PIN DESCRIPTIONS CLKSYNC: An edge triggered active low TTL signal to this pin synchronizes the oscillator to an external clock. When VOUT decreases below 3.0 V, the frequency foldback circuit is activated and the controller becomes unsynchronized. When VOUT exceeds 3.0 V, the controller resynchronizes to the external clock. COMP: The output of the voltage error amplifier used for compensation. The output is clamped to 3.0 V minimum. CS: Current sense input. This pin accepts a voltage proportional to converter inductor current. The voltage CS is compared to the output of the compensated error amplifier to control the on-time of the switch. Voltage mode control can be realized by driving this pin with fixed sawtooth ramp. Voltage feedforward is achieved by making the peak of this ramp proportional to the input voltage. CSS: A capacitor, CSS, to ground programs the soft-start time for the power-up sequence. This function is also used when an overcurrent fault occurs. As CSS is charged, the PWM comparator uses the lowest of either the voltage at CSS or the error amplifier output voltage to determine the duty cycle. The duty cycle, therefore, slowly increases during the soft-start cycle. The faults that cause CSS to discharge and shutdown the controller are the logical OR of VREF below 4.4 V or VDD below 8.8 V. If a fault is still present when CSS is discharged below 0.5 V, the supply remains off until the fault is cleared. The soft-start time is determined by: tSS = 3.5 ´ CSS I SS where ISS is 20 µA. A current limit terminates the present cycle. It does not generate a soft start cycle. CT: A capacitor, CT to ground, is charged and discharged creating the oscillator waveform. This waveform varies between 1.5 V and 3.5 V. The operating frequency is determined by: f = 4 .4 R ö æR CT ´ ç ON + OFF ÷ 3 .5 ø è 1 .5 The ratio of the time duration of the positive sloped portion of the CT voltage waveform to the period gives the maximum duty cycle. FB: The inverting input of the voltage amplifier used to sense the output voltage. The non-inverting input of the error amplifier is internally connected to 2.5 V. GND: The ground pin internally used for all the amplifiers and as the return for all resistor and capacitor connections to the UCC3884. GT: Used to drive an external depletion-mode MOSFET for the housekeeping power supply. The MOSFET is turned off when the bootstrap winding voltage exceeds 10 V. There is 300 mV of hysteresis around the 10-V, turn-off voltage to prevent oscillation. See Typical Application. IOFF: A resistor, ROFF, to ground, programs the discharge current of the timing capacitor CT. This is a variable discharge current which determines the negative slope of the oscillator voltage waveform at CT. The discharge time is dependent on the voltage at the VOUT pin. The discharge current is given by: I OFF = VOUT ROFF The VOUT pin is internally clamped to 3.5 V maximum. 6 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 UCC2884 UCC3884 www.ti.com............................................................................................................................................. SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008 ION: A resistor, RON, to ground programs the charge current of the timing capacitor, CT, which generates the positive slope of the oscillator waveform. The charge time is constant and corresponds to the maximum output on-time at OUT. The charge current equation is: I ON = 1.5V RON When required the linear positive slope of the CT voltage could be buffered and used to provide slope compensation into the CS pin. OUT: The output of the controller. The peak source current is 0.5 A and the peak sink current is 1.0 A. The faults listed under the CSS description turn off this output. PGND: The power ground pin is used as the return for the output transistor drive stage. VDD: The input voltage of the chip. A low ESR and ESL ceramic capacitor from this pin to GND should be used to bypass internal switching transients. VOUT: This pin accomplishes frequency foldback by controlling the discharge current for the oscillator CT capacitor. A dc voltage proportional to the output voltage is connected to this pin. To startup with zero output voltage the user should tie a resistor between VREF and VOUT. The value depends on the lowest desired operating frequency. When VOUT decreases below 3.5 V the frequency decreases by reducing the discharge current IOFF. When VOUT increases, the frequency increases by increasing the discharge current. The maximum operating frequency occurs when VOUT = 3.5 V. The CT charge time is constant to assure a maximum output duty cycle. This pin must be above 3.0 V to allow synchronization to occur. VREF: This pin is the output of the 5-V regulated reference. Bypass this pin with a low ESR and ESL ceramic capacitor (e.g., 0.47 µF). VVS: Provides a programmable duty cycle clamp which is dependent upon the input voltage. A resistor divider network reduces the input voltage supplied to VVS. The device determines the reciprocal of the voltage at VVS and scales the result. The voltage is then compared to the oscillator waveform to clamp the duty cycle. The purpose of this clamp is to reduce the likelihood of saturating the isolation transformer during unusual line or load conditions. Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 Submit Documentation Feedback 7 UCC2884 UCC3884 SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008............................................................................................................................................. www.ti.com APPLICATION INFORMATION Theory of Operation The UCC3884 current-mode PWM controller contains a programmable oscillator which includes the ability to synchronize multiple PWMs. The positive and negative sloped portions of the oscillator waveform (measured at CT), have time intervals that are set by external resistors at ION and IOFF. The operating frequency is inversely proportional to the timing capacitor. The negative sloped portion of the oscillator waveform is extended in time as the measured output voltage decreases providing protection during output faults. The power supply output voltage and the voltage from VREF are fed back to VOUT. When the output voltage decreases, the voltage at VOUT also decreases. As VOUT decreases below 3.5 V, the operating frequency decreases. This reduction in frequency allows the duty cycle to decrease below what the CS to OUT delay would otherwise permit. This is referred to as frequency foldback. An output short circuit or overload causes the converter to enter the frequency foldback mode. Synchronization to other controllers can only occur during normal operation, that is, when VOUT is greater than 3.0 V. GT is provided to turn off an external depletion-mode MOSFET after startup when the bootstrap winding exceeds 10 V. This depletion-mode MOSFET is used in the housekeeping section of the converter to simplify startup biasing circuitry. The amplifier that drives this MOSFET has 300 mV of hysteresis to avoid oscillation during power up. An accurate programmable volt-second technique clamps the duty cycle. The duty cycle limit is inversely proportional to input voltage and a resistor divider network is used to program the proportionality constant. At a given input voltage and constant load, under closed loop control, the operating duty cycle is a fixed value. The volt-second clamp duty cycle may then be set somewhat higher than this operating duty cycle. For other input voltages, the volt-second clamp still exceeds the steady state operating duty cycle. This allows normal closed loop operation of the converter. It is during a load transient (a fault such as a momentary short circuit) as the error amplifier increases the duty cycle, that when the volt-second clamp accurately limits the maximum volt-seconds. This ensures that the transformer does not saturate during a fault which can fail the power supply. After the fault is removed the converter resumes closed loop control. CSS is provided which allows the UCC3884 to be disabled with an external transistor. The increasing pulse width at OUT during soft start should be programmed to be less than the pulse width of the duty cycle limit that the frequency foldback circuitry creates. The frequency foldback circuit will be in effect during soft start since the output voltage fed back to VOUT is less than 3.5 V. Designing the circuit in this fashion allows a proper startup sequence. The current sense feedback pin has an overcurrent protection feature which forces a soft start cycle only if the device is not currently in a soft-start cycle. A 1-V bias at the PWM comparator’s non-inverting input and a reset dominant PWM latch permit zero duty cycle operation. The error amplifier has a wide gain-bandwidth product and its non-inverting input is internally set to 2.5 VDC. 8 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 UCC2884 UCC3884 www.ti.com............................................................................................................................................. SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008 Oscillator The oscillator has charge and discharge currents programmed with resistors to ground from ION and IOFF respectively, as seen on the Oscillator Block Diagram.(Figure 1). This generates a linear sawtooth waveform on CT. Frequency foldback is accomplished by the level shifted output voltage controlling the VOUT voltage which decreases the discharge current and the frequency. Synchronization is accomplished by coupling the fastest oscillator CLKSYNC signal as shown on the Oscillator Synchronization Diagram (Figure 2). The fastest (master) CLKSYNC pin couples a negative pulse into the slower (slave) CLKSYNC pins forcing the slaves’ CT pins to quickly discharge as shown on the Oscillator Waveform diagram (Figure 3). VREF 1.5V ION 11 – + CLK CT 3.5V 10 VREF VOUT 13 IOFF 12 S Q R Q 1.5V 6 CLKSYNC + – 3.0V 14 3.5V SYNCEN 8.8X 3V SYNCEN Figure 1. UCC3884 Oscillator Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 Submit Documentation Feedback 9 UCC2884 UCC3884 SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008............................................................................................................................................. www.ti.com Synchronization Techniques The following explains two synchronization techniques: 1. Initially Undefined Master If the user does not care which unit is the master, then the oscillator frequencies are designed as accurate as necessary and one unit becomes the master and synchronize the remaining units. The user never knows exactly which unit will be the master upon power up. 2. User-Defined Master If the user does care which unit is the master, a unit should be identified as the master, and the frequency and maximum duty cycle clamp should be programmed accordingly. The ROFF resistor which programs the slave units oscillator discharge ramp should be between 50% and 100% of the ROFF resistor which programs the master. This ensures that if a slave unit tries to synchronize the master, the master frequency will still be faster than the slave frequency and the master synchronizes all the remaining units. Figure 2. Oscillator Waveforms 10 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 UCC2884 UCC3884 www.ti.com............................................................................................................................................. SLUS160C – AUGUST 1999 – REVISED NOVEMBER 2008 Figure 3. Typical Application Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): UCC2884 UCC3884 Submit Documentation Feedback 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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