UCC388PW

     . ."      - SLUS377B - JULY 1999 - REVISED MAY 2000
Precision Positive Linear Voltage Regulator
0.2 V Dropout at 200 mA
Ensured Reverse Input/Output Voltage






SOIC DP PACKAGES (TOP VIEW) VOUT GND GND VSENSE Isolation with Low Leakage Adjustable Output Voltage (Down to 1.25 V) Load Independent Low Quiescent Current (10 A typical) Load Regulation of 5 mV from 0 mA to 200 mA Logic Shutdown Capability Shutdown Quiescent Current Below 2 A Short Circuit Protection - Duty Cycle Limiting Remote Load Voltage Sense for Accurate Load Regulation 1 8 2 7 3 6 4 5 VIN GND GND OFFB TSSOP PW PACKAGES (TOP VIEW) VIN N/C N/C VOUT 1 8 2 7 3 6 4 5 OFFB N/C VSENSE GND description The UCC386/7/8 positive linear pass regulator series is tailored for low-dropout applications where extremely low quiescent power is required. Fabricated with BiCMOS technology ideally suited for low input to output differential applications, the UCC386/7/8 will pass 200 mA while requiring only 200 mV of input voltage headroom. Quiescent current is typically less than 10 µA. To prevent reverse current conduction, on-chip circuitry limits the minimum forward voltage to 50 mV typical. Once the forward voltage limit is reached, the input-output differential voltage is maintained as the input voltage drops until undervoltage lockout disables the regulator. block diagram and application circuit SWITCH CONTROL VOUT LOAD VIN 1 8 + + – GND GND 2 7 + 1.25 V RS1 GND 3 R1 VSENSE R1 R2 UCC386 1.025 m 625 k UCC387 1.875 m 625 k UCC388 0 OPEN R2 OVERCURRENT, HICCUP CONTROL & THERMAL SHUTDOWN GND 6 4 OFFB 5 RS2 UCC388 ONLY FROM OPEN DRAIN SHUTDOWN COMMAND UDG-98087 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated    #$&"( $# ' )&&#( ' $ %)! ( $# ( &$)(' $#$&" ($ '%  ( $#' %& ( (&"' $ +' #'(&)"#(' '(#& *&&#(, &$)( $# %&$'' # $' #$( #''& !, #!) ('( # $ !! %&"(&' POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1               SLUS377B - JULY 1999 - REVISED MAY 2000 description (continued) The UCC386 has an on-chip resistor network for preset to regulate at 3.3 V, while the UCC387 has a fixed 5-V output. The UCC388 requires an external resistor network that can be programmed for output voltages down to 1.25 V. The output voltage is regulated to 1.5% at room temperature and better than 2.5% over the entire operating temperature range. Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by limiting the duty cycle of the load to 12.5% typical. This drastically reduces the power dissipation during short circuit such that heat sinking, if at all required, must only accommodate normal operation. Internal power dissipation is further controlled with thermal overload protection circuitry. Thermal shutdown occurs if the junction temperature exceeds 140°C. The chip remains in the off state until the temperature drops to 115°C. Pulling OFFB low commands a low-power shutdown mode, which requires less than 2-µA quiescent current. These devices are available in the 8-pin TSSOP (PW) and 8-pin SOIC (DP) surface-mount power packages. For other packaging options consult the factory. AVAILABLE OPTIONS OUTPUT VOLTAGE (V) TA 0°C to 70°C PACKAGE DEVICES MIN TYP MAX SOIC-8 (DP) TSSOP-8 (PW) 3.22 3.30 3.38 UCC386DP UCC386PW 4.785 5.000 5.125 UCC387DP UCC387PW UCC388DP UCC388PW ADJ † All package types are available taped and reeled. Add TR suffix to device type (e.g. UCC386DPTR) to order quantities of 3000 devices per reel. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V OFFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VIN 0.3 V Storage Temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND. electrical characteristics, TA = TJ = 0 C to 70 C, VIN = VOUT+1.5 V, IOUT = 0 mA, COUT = 0.1 F (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 3.25 3.3 3.35 V 3.22 3.3 3.38 13 25 5 10 mV 500 µVRMS mV UCC386 Fixed 3.3 V Output Output voltage TA = 25°C Over temperature Line regulation VIN = 3.45 V to 8.5 V, IOUT = 10 mA Load regulation IOUT = 1 mA to 200 mA TJ = 25°C, BW = 10 Hz to 10 kHz 200 VOUT = 3.20 V 200 VOUT = 3.20 V 50 Output noise voltage Dropout voltage, voltage VIN-VOUT VIN VOUT 2 IOUT = 200 mA, IOUT = 50 mA, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V mV mV               SLUS377B - JULY 1999 - REVISED MAY 2000 electrical characteristics, TA = TJ = 0 C to 70 C, VIN = VOUT+1.5 V, IOUT = 0 mA, COUT = 0.1 F (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 260 550 850 mA 225 375 525 mA 12.5 14 % 900 1250 µs 10 20 µA 5 µA 0.5 V UCC386 Fixed 3.3 V Output (continued) Peak current limit VOUT = 0V Overcurrent threshold Current limit duty cycle VOUT = 0 V Overcurrent timeout, TON VOUT = 0 V Quiescent current OFFB = VIN Shutdown quiescent current VIN ≤ 8.5 V, Shutdown threshold (OFF) VIN = 8.5 V 0 See Note 1 VIN 0.5 V Shutdown threshold (ON) Reverse leakage current 550 OFFB ≤ 0.5 V 0 V < VIN < VOUT, VOUT < 3.35 V, at VIN 0 V < VIN < VOUT, VOUT < 3.35 V, at VOUT 2 Bias current at VSENSE pin V 10 µA 10 µA µA 2 UCC387 Fixed 5 V Output Output voltage TA = 25°C Over full temperature range Line regulation VIN = 5.5 V to 8.5 V, IOUT = 10 mA Load regulation IOUT = 1 mA to 200 mA TJ = 25°C, BW = 10 Hz to 10 kHz 200 IOUT = 200 mA, IOUT = 50 mA, VOUT = 4.75 V 200 Dropout voltage, voltage VIN-VOUT VIN VOUT VOUT = 4.75 V 50 Peak current limit VOUT = 0 V Output noise voltage 4.925 5 5.075 4.785 5 5.125 13 25 5 10 mV 500 µVRMS mV 260 Overcurrent threshold 225 Current limit duty cycle VOUT = 0 V Overcurrent timeout, TON VOUT = 0 V Quiescent current OFFB = VIN Shutdown quiescent current VIN ≤ 8.5 V, Shutdown threshold (OFF) VIN = 8.5 V 0 See Note 1 VIN 0.5 V Shutdown threshold (ON) Reverse leakage current 550 OFFB ≤ 0.5 V V V mV mV 550 850 mA 375 525 mA 12.5 14 % 900 1250 µs 10 20 µA 2 5 µA 0.5 V V 0 V < VIN < VOUT, VOUT < 3.35 V, at VIN 10 µA 0 V < VIN < VOUT, VOUT < 3.35 V, at VOUT 10 µA Bias current at VSENSE pin µA 2 UCC388 Adjustable Output Output voltage TA = 25°C Over full temperature range Line regulation VIN = 2.5V to 8.5 V, Load regulation IOUT = 1 mA to 200 mA TJ = 25°C, Output noise voltage Dropout voltage, voltage VIN-VOUT VIN VOUT IOUT = 200 mA, IOUT = 50 mA, Peak current limit VOUT = 0 V 1.23 1.25 1.27 1.22 1.25 1.28 10 40 mV 5 10 mV 500 µVRMS mV IOUT = 10 mA, VOUT = 1.25 V BW = 10 Hz to 10 kHz 200 VOUT = 3.20 V 200 VOUT = 3.20 V Overcurrent threshold 50 V V mV 260 550 850 mA 225 375 525 mA NOTE 1: An internal 100-nA pullup is provided for this function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3               SLUS377B - JULY 1999 - REVISED MAY 2000 electrical characteristics, TA = TJ = 0 C to 70 C, VIN = VOUT+1.5 V, IOUT = 0 mA, COUT = 0.1 F (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS UCC388 Adjustable Output (continued) Current limit duty cycle VOUT = 0 V Overcurrent timeout, TON VOUT = 0 V Quiescent current OFFB = VIN Shutdown quiescent current VIN ≤ 8.5 V, Shutdown threshold (OFF) VIN = 8.5 V 0 Shutdown threshold (ON) See Note 1 VIN 0.5 V Reverse leakage current 550 OFFB ≤ 0.5 V 0 V < VIN < VOUT, VOUT < 3.35 V, at VIN 0 V < VIN < VOUT, VOUT < 3.35 V, at VOUT Bias current at VSENSE pin 12.5 14 % 900 1250 µs 10 20 µA 5 µA 0.5 V 2 V 10 µA 10 µA 50 Minimum operating voltage nA 2.5 V NOTE 1: An internal 100-nA pullup is provided for this function. pin descriptions GND: Chip Ground. All voltages are measured with respect to this pin. This is the low-noise ground reference for input regulation. The output decoupling capacitor should be tied between VOUT and GND. OFFB: Shutdown, active low. This pin must be externally pulled to GND to turn off the IC. Pulling this pin high turns on the IC. This pin is internally pulled to VIN by 100-nA current source. VIN: Positive supply input for the regulator. Bypass this pin to GND with at least 0.1 µF of low ESR, ESL capacitance if the source is located further than 1 inch from the device. VOUT: Output of the regulator. The regulator does not require a minimum output capacitance for stability, however a small capacitor is recommended to improve transient response. Choose the appropriate size capacitor for the application with respect to the required transient loading. For example, if the load is very dynamic, a large capacitor will smooth out the response to load steps. VSENSE: Externally programmable voltage sense node. For the UCC388, connect resistor divider network between VOUT, VSENSE and GND to provide custom regulation level. For the UCC386 and UCC387, connect this pin to VOUT as close to the load as possible. APPLICATION INFORMATION load independent current consumption This series of LDOs is based on CMOS circuitry and uses a high-side P-channel pass element. Consequently, the current consumed by the LDO is extremely low at 10 µA under normal operating conditions and does not vary with load. The shutdown mode (OFFB = GND) consumes only 2 µA, making this series an excellent choice for battery applications. reverse voltage standoff These LDOs are designed to operate with the voltage at the output greater than the voltage at the input. This can be an advantage where a circuit needs to be powered from two separate power sources that must be kept isolated, such as selecting between one of two or more batteries. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265               SLUS377B - JULY 1999 - REVISED MAY 2000 APPLICATION INFORMATION overcurrent protection The UCC386/7/8 uses a fixed, absolute, current limit in conjunction with a timed overcurrent function that significantly reduces power dissipation in the event of a shorted load (see Figure 1). In this diagram, a 100-mA load is applied to the output of the LDO. At some point, a fault is applied. When the current level exceeds the overcurrent threshold of about 300 mA, a timer is started. If the current does not fall below the overcurrent threshold before the timer times out, about 5.6 ms, the LDO declares an overcurrent condition exists and turns off its output for about 5.6 ms. Note that the output current is internally limited to 600 mA. After the output has been off for 5.6 ms, it is turned on for about 800 µs and again limited to 600 mA. If the current does not fall below the overcurrent threshold before the 800-µs timer expires, the output is again turned off for 5.6 ms. This process repeats itself until the fault condition is removed from the output of the LDO. The average current supplied to the faulted load by the LDO is approximately 112 mA. This is well below the maximum rated current of 200 mA of the LDO. Therefore, for most applications that have adequate thermal dissipation for the LDO to operate at full rated load, the thermal dissipation will also be adequate in a faulted condition. 800 µ s 5.6 ms 5.6 ms 600 mA 300 mA 100 mA 0 FAULT APPLIED FAULT REMOVED UDG-98088 Figure 1. Current Waveform During a Fault thermal shutdown The LDOs have a thermal shutdown circuit that will turn the LDO output off before the die temperature reaches damaging levels. When the die cools, the LDO will again function. The thermal shutdown circuit has a turn-off threshold of nominally 140°C, and a turn-on threshold of 115°C. These temperatures insure that the LDO will not be damaged due to excessive power dissipation. maximum load recovery The LDO will start a load that has a large capacitance and a dc current component. One of the consequences of the LDOs fault behavior is a maximum output capacitor value and load current that the LDO can restart after an overcurrent condition has been declared. Figure 2 shows the maximum load that the LDO can re-start from a faulted condition with a given output filter capacitor. Note that the LDO can start a much higher load than it can restart after a fault. If the LDO is hiccuping into a load that it cannot re-start, either momentarily disconnecting the load or a power cycle allows the LDO to start the load. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5               SLUS377B - JULY 1999 - REVISED MAY 2000 APPLICATION INFORMATION maximum load recovery (continued) CRITICAL LOAD CURRENT vs OUTPUT CAPACITANCE 200 CL - Load Current - mA 160 120 UCC386 80 40 UCC387 0 20 60 100 140 180 CO - Output Capacitance - F Figure 2. using OFFB The OFFB pin is used to turn the output of the LDO on or off from some external source. There are two things to note when using this pin. The first is that after taking OFFB high (on), the LDO will require up to about 2 ms to start and stabilize. The second item is that OFFB is designed to be driven from an open-drain-type output. Internally, this pin is pulled high by a weak 100-nA current source, and will normally be at the input supply voltage, so the driving circuitry must be able to withstand the voltage applied to the input of the regulator. Also, depending upon load, if the OFFB pin is driven (overriding the internal pull-up) high with a fast edge signal, there may be a brief pulse on the output, followed by no output, with the regulator coming on and stabilizing about 2 ms after the OFFB pin was driven high. This output pulse is never more than the normal output voltage of the regulator and is about 200 µs in length. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265               SLUS377B - JULY 1999 - REVISED MAY 2000 APPLICATION INFORMATION output capacitance and transient response The transient response of the regulator is heavily influenced by the capacitor on the output. In general, larger capacitors produce less voltage variation during load changes, but take longer to stabilize (quit wiggling). Note that no output capacitor is required for a stable output. However, if the load exhibits sharp changes in current requirements, and temporary deviations from the nominal output voltage must be minimized, some output filter capacitor will be needed. UCC388 output voltage programming Referring to the applications diagram on the front page of the data sheet, the output voltage is given by: V O   1.25 R 
R S1 S2 R S2 Note that for the UCC388, the internal resistor R2 is open. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) UCC386PW OBSOLETE TSSOP PW 8 TBD Call TI Call TI UCC386PWTR OBSOLETE TSSOP PW 8 TBD Call TI Call TI UCC387DP OBSOLETE SOIC D 8 TBD Call TI Call TI UCC387DPTR OBSOLETE SOIC D 8 TBD Call TI Call TI UCC387PW OBSOLETE TSSOP PW 8 TBD Call TI Call TI UCC387PWTR OBSOLETE TSSOP PW 8 TBD Call TI Call TI UCC388DP OBSOLETE SOIC D 8 TBD Call TI Call TI UCC388DPTR OBSOLETE SOIC D 8 TBD Call TI Call TI UCC388PW OBSOLETE TSSOP PW 8 TBD Call TI Call TI UCC388PWTR OBSOLETE TSSOP PW 8 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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