User’s Guide
UCC39002 Advanced Load-Share
Controller User’s Guide, HPA027A
User’s Guide
1
EVM IMPORTANT NOTICE
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
2
DYNAMIC WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the maximum input voltage ranges specified.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
If there are questions concerning the input range, please contact a TI field representative prior to connecting
the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM
output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 50°C. The EVM
is designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
3
SLUU166A - December 2003 − Revised February 2004
UCC39002 Advanced Load-Share Controller User’s Guide,
HPA027A
System Power
Lisa Dinwoodie
ABSTRACT
The UCC39002 is an advanced, high-performance load-share controller that provides all the
necessary functions to parallel multiple independent power supplies or dc-to-dc modules. This
load-share circuit is based upon the automatic master/slave architecture utilized in the UC3902 and
the UC3907 load-share controllers providing better than 1% current-share error between the modules
at full load.
1
2
3
4
5
6
7
8
9
10
11
12
1
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Introduction
The UCC39002 load-share controller allows accurate current sharing between paralleled power modules. The
evaluation module provides an optimum layout to parallel up to three modules on a board in which most of the
reference designators are unpopulated. This user’s guide will facilitate component selection for the modules to
be current shared. Component values are dependent upon the specific power modules and must be calculated
for each load-share system.
2
Caution
Dependent upon the power modules being paralleled, there may be high voltages present on this EVM. Some
components under maximum power may be hot. Precautions should be taken. The maximum load current for
this evaluation board is recommended to be 10 A from each module being paralleled. Due to the absolute
maximum voltage ratings of the current sense amplifier inputs and the adjust pin input, this evaluation module
is limited to use with converters whose output voltages do not exceed 15 V.
4
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
3
Applications
This user’s guide will enable the user to select components to successfully parallel power modules that have
the following features:
D Remote sense
D Output voltages greater than 1 V, but less than 15 V
D An output stage that sources output current only, allowing for paralleling of converters and ensuring one
converter does not sink current from another converter.
D Available minimum 5-V bus for controller bias voltage, or use of the output voltage of the modules for bias
when the output of the modules is between 5 V and 15 V.
4
Features
D
D
D
D
D
D
D
D
D
D
5
High accuracy, better than 1% current-share error at full load
High-side current sensing
Ultra-low offset current sense amplifier
Single wire load-share bus
Intel SSI load-share specification compliant
Disconnect from load-share bus at stand-by
Load-share bus protection against shorts to GND or to the supply rail
8-pin MSOP package option minimizes board space
External or internal bias selection
External shutdown switch for each module
Schematic
A schematic of a typical load-share design, where the outputs of three modules are being shared, is shown in
Figure 1. Note that one load-share controller is required for each module and the circuits are identical when three
identical modules are used. Terminals J1 and J2 are connected to the +VOUT and −VOUT, respectively, of the
first power module. Terminals J3, J4, J5, and J6 correspond to the other two modules positive and negative
output pins. Terminal J7 connects the positive output bus to the load and J8 connects the negative output to the
load.
The UCC39002 load share controllers require a minimum bias voltage of 4.575 V to ensure enabling the load
share bus. Note the maximum bias voltage for this design is 15 V. This enables the under voltage lockout/bias
ok internal circuitry of the UCC39002 without exceeding the absolute maximum voltage rating of the current
sense amplifier inputs and the adust pin. Modules that have an output voltage of less than 5 V will require
external biasing for the load share controllers: jumpers JP1 through JP3 should be shorted to the EXT. position
and an external 5-V supply can be used as bias at the terminal block labeled EXTERNAL BIAS. Otherwise, the
controllers should be biased from the modules’ output bus voltage by shorting these jumpers to the INT. position.
Note that the voltage on the current sense input pins and the adjust pin must be equal to or less than the bias
voltage on VDD.
Terminal blocks TB1 through TB3 connect to the sense lines from each module. For remote sensing, JP4 and
JP5 are left open and remote sense leads from the load are connected to the terminal block labeled REMOTE
SENSE. For local voltage sensing, simply jumper JP4 and JP5. This connects the sense lines from the modules
to the load terminals on the evaluation board through dedicated, low noise, low current traces.
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
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SLUU166A - December 2003 − Revised February 2004
The available evaluation boards come pre−populated with the load share controllers, VDD decoupling
capacitors, and components for external controller shut down. This circuitry is shown in Figure 1 as U1, C5, Q1,
R1, and R4 for the first module, U2, C7, Q2, R2, R5 for the second, and U3, C9, Q3, R3, and R6 for the third.
By applying a 2-V signal onto the SD terminal of any of the three modules, the 2N7002 transistor is turned on,
shorting CS+ to ground, resulting in that module’s disconnect feature to be enabled. With the disconnect feature
enabled, the UCC39002 disconnects itself from the load share bus and its adjust current is zero.
Figure 1. UCC39002 Load-Share Schematic
6
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
6
Design Procedure
The following is a step-by-step design procedure on how to determine the appropriate components to parallel
power modules for load sharing. The user’s guide is stated for the first module and the circuit is repeated for
each of the remaining two modules.
In order to accurately current share between power modules, specific parameters must be known:
D VOUT = nominal output voltage of the modules to be paralleled
D IOUT(max) = maximum output current of each module to be paralleled
D ∆VADJ(max) = maximum voltage adjustment range of the power module to be paralleled
D N = number of modules to be paralleled
D VDD = bias voltage for the UCC39002 controllers
D The transfer function of the power modules between their positive voltage sense and power output
terminals.
6.1
Measuring the Module’s Unity Gain Crossover Frequency
Power modules usually have a very low bandwidth to ensure proper operation with a variety of loads. The
transfer function is determined using a network analyzer and injecting a small signal across a 20-Ω to 50-Ω
resistor placed between the positive sense terminal and the positive voltage output terminal as shown in
Figure 2. The resultant bode plot will show the dc gain and the unity gain crossover frequency of the module.
Expect the module’s crossover frequency to be within the range from 10 Hz to 30 kHz. The desired crossover
frequency for the load-share loop is set well before the crossover frequency of the modules. This is
accomplished by adding a zero to the compensation of the transconductance error amplifier as described in the
error amplifier section. The unity gain crossover frequency is unique to the specific module and must be
measured for each module type.
+Vout
DC−DC
V IN
LOAD
−Vout
Module
+Sense
−Sense
50Ω
XFRMR
Source Channel
A
Out
Channel
B
NETWORK
ANALYZER
Figure 2. Measuring the Unity Gain Crossover Frequency
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
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SLUU166A - December 2003 − Revised February 2004
GAIN AND PHASE
vs
FREQUENCY
100
0
Gain − dB
50
−100
0
Phase
−50
100
Phase − Degrees
−50
Gain
−150
−200
1k
10k
Frequency − Hz
100k
Figure 3
Figure 3 shows an example of the gain and phase frequency response measurement of a power module.
6.2
Choosing the Sense Resistor
The primary concern in the selection of the sense resistor, RSENSE, is to ensure that the sum of the voltage drops
across the resistor and the parasitic wire impedances, at maximum module output current, is significantly less
than the output voltage adjustment range of the modules, otherwise there would be no room for output voltage
adjustment.
I OUT(max)
R SENSE tt DV ADJ(max)
(1)
Other limitations for the sense resistor are the desired minimum power dissipation and available component
ratings. The board provided has space for two 1-W 2512 resistors in parallel to be used for current sensing, as
shown by R10 and R11 in Figure 1.
6.3
Setting the Gain of the Current Sense Amplifier
The gain of the current-sense amplifier (CSA) is configured by adding compensation components between the
inverting input to the amplifier, CS−, and the current sense amplifier output, CSO, of the load-share device. The
maximum voltage at the CSO pin, VCSO(max), is limited by the saturation voltage of the internal current sense
amplifier and must be at least two volts less than VDD.
V CSO(max) t VDD * 2 V
(2)
Referring to Figure 1, the CSA gain, ACSA, is equal to:
ǒ Ǔ
V CSO
A CSA + R22 +
R19
R SENSE I OUT(max)
8
ǒ
Ǔ
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
(3)
SLUU166A - December 2003 − Revised February 2004
A high-frequency pole, fPOLE configured with C4, should be added for noise filtering.
C4 +
2
1
R 22
p
f POLE
(4)
The total impedance at CS− must be mirrored at the non-inverting input, CS+, of the differential amplifier, as
shown by R7, R16, and C1 in Figure 1.
The CSA output voltage, VCSO, serves as the input to the internal unity gain LS bus driver. The module with the
highest output voltage will forward bias the internal diode located at the output of the LS bus driver and determine
the voltage on the load-share bus on the LS pin, VLS, making this module the master. This load-share bus acts
as a communication port between the paralleled modules. The LS pin is bi-directional. By forward biasing the
internal diode, the master sets the LS bus voltage based upon the voltage across its current sense resistor.
Because the internal diode is reverse biased on the other modules, referred to as the slaves, the LS voltage
is used as the non-inverting input to the internal LS bus receiver. The master transmits the voltage signal to the
slave modules so they can compare their voltages across their own current sense resistors with that of the
master module. The slave modules represent a load on the bias current, IVDD, of the master module due to the
internal 100-kΩ resistor at the LS pin. This increase in supply current for the master module is equal to:
ǒ
DI VDD + N
Ǔ
V LS
100 kW
(5)
where N is equal to the number of paralleled modules.
6.4
Determining RADJUST
The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor,
R25 in Figure 1, between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop
across RADJUST due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be
maintained at approximately 1 V above the voltage at the EAO pin. This is necessary in order to keep the
transistor at the output of the internal adjust amplifier from saturating. To fulfill this requirement, RADJUST can
be calculated using the following equation:
R ADJUST w
ƪDVADJ(max) * ǒIOUT(max) RSENSEǓƫ 500 W
ƪVOUT * ǒDVADJ(max) * ǒIOUT(max) RSENSEǓǓ * 1 Vƫ
(6)
Also needed for consideration is the actual adjust pin current. The maximum sink current for the ADJ pin,
IADJ(max), is 6 mA as determined by the internal 500-Ω emitter resistor and 3-V clamp. The value of adjust
resistor, RADJUST, is based upon the maximum adjustment range of the module, ∆VADJ(max). This adjust resistor
is determined using the following formula:
R ADJUST w
ƪDVADJ(max) * ǒIOUT(max)
Ǔƫ
R SENSE
I ADJ(max)
(7)
By selecting a resistor that meets both of these minimum requirements, the ADJ pin will be at least 1 V greater
than the EAO voltage and the adjust pin sink current will not exceed its 6 mA maximum.
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
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SLUU166A - December 2003 − Revised February 2004
6.5
Error Amplifier Compensation
The total load-share loop must be configured for a unity gain crossover frequency well before the crossover
frequency of the module, fCOmodule, as measured in Figure 2 and shown in Figure 3. This is accomplished by
placing a zero in the error amplifier compensation at least one decade before the module’s crossover frequency.
Compensation of the transconductance error amplifier is done by placing the compensation resistor, REAO
shown as R30 in Figure 1, and capacitor, CEAO shown as C12 in Figure 1, between EAO and GND. The values
of these components are determined by the following loop gain equation:
C EAO +
ǒ
2
GM
p f ZERO
Ǔ
A CSA
AV
A ADJ
A PWR(fco)
(8)
Where:
1. Gm is the transconductance of the error amplifier, typically 14 mS,
2. fzero is equal to the desired frequency in Hz of the zero to be added to the load-share loop, maximum zero
f CO(module)
frequency will be equal to
,
10
3. ACSA equals R22/R19,
4. AV is the voltage gain, equal to
R SENSE
,
R LOAD
5. AADJ is the gain associated with the adjust amplifier, equal to
R ADJUST
,
500 W
6. APWR(fCO) is the measured gain of the power module at the desired inserted zero frequency, read from
Figure 3 and converted from dB to V/V.
The calculated capacitor value will most likely be very large due to the low frequency of the zero. The actual
available capacitor used will undoubtedly be of a lower value and this must be taken into consideration when
determining the compensation resistor. Once the CEAO capacitor is determined, REAO is selected to achieve
the desired loop response:
R EAO +
10
ǒ2
1
p
C EAO(actual value used)
f ZERO
Ǔ
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
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7
List of Materials
REFERENCE
QTY
DESCRIPTION
MANUFACTURER
PART NUMBER
C1, C2, C3, C4, C6,
C8
6
Capacitor, ceramic, X5R or better, CSA compensation,
0805
TBD
TBD
C10, C11, C12
3
Capacitor, ceramic, X5R or better, EA compensation,
1210
TBD
TBD
C5, C7, C9
3
Capacitor, ceramic, 0.47 µF, 25 V, X7R, ±10%, 0805
TDK Corporation
C2012X7R1E474K
Q1, Q2, Q3
3
MOSFET, N-channel, 60 V, 115 mA, 1.2 Ω, SOT23
Vishay−Liteon
2N7002DICT
R1, R2, R3
3
Resistor, chip, 47 kΩ, 1/10 W, ±5%, 0805
Panasonic − ECG
ERJ−6GEYJ473V
R4, R5, R6,
3
Resistor, chip, 1 kΩ, 1/10 W, ±5%, 0805
Panasonic − ECG
ERJ−6GEYJ102V
R7, R8, R9, R19,
R20, R21
6
Resistor, chip, 1/10 W or better, ±5% or better, CSA compensation, 0805
TBD
TBD
R10, R11, R12, R13,
R14, R15
6
Resistor, chip, 1 W, ±5% or better, current sense, 2512
TBD
TBD
R16, R17, R18, R22,
R23, R24
6
Resistor, chip, 1/10 W or better, ±5% or better, CSA compensation, 0805
TBD
TBD
R25, R26, R27
3
Resistor, chip, 1/10 W or better, ±5% or better, voltage
adjustment, 0805
TBD
TBD
R28, R29, R30
3
Resistor, chip, 1/10 W or better, ±5% or better, EA compensation, 0805
TBD
TBD
TB1, TB2, TB3, TB4,
TB5
5
Terminal block, 2 pin, 15 A, 5.1 mm, 0.40 x 0.35
OST
ED1609
U1, U2, U3 **
3
IC, Advanced Load Share Controller, SO8
Texas Instruments
UCC39002D
JP1, JP2, JP3
3
Header, 3 pin, 100-mil spacing, 36-pin strip, 0.100 x 3”
Sullins
PTC36SAAN
JP4, JP5
2
Header, 2 pin, 100-mil spacing, 36-pin strip, 0.100 x 2”
Sullins
PTC36SAAN
J1, J2, J3, J4, J5, J6,
J7, J8
8
Lug, solderless, #10−12 AWG, copper/tin, uninsulated,
0.375 x1.00
AMP
33457
N/A
5
Shunt for JP1, JP2, JP3, JP4, JP5, 0.100”
Sullins
STC02SYAN
N/A
8
Input and output lugs for V+ and V− pads, 0.765”
Solis
8−33457−1
N/A
8
Screw, roundhead, phillips, #8−32 1/4”, 0.35”
Std
Std
N/A
8
Star washer, #8, 0.36”
Std
Std
N/A
8
Nut, medium #8, 0.245”
Std
Std
NOTES: 1.
2.
3.
4.
These assemblies are ESD sensitive, ESD precautions shall be observed.
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
These assemblies must comply with workmanship standards IPC−A−610 Class 2.
Ref designators marked with an asterisk (’**’) cannot be substituted. All other components can be substituted with equivalent MFG’s
components.
5. Install lugs with appropriate hardware per Figure 4,below. Ensure the lug is seated on the square pad for good contact.
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
11
SLUU166A - December 2003 − Revised February 2004
Figure 4. Lug Assembly Detail
8
Board Layout
Figure 5. Top View
12
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
Figure 6. Top Layer Route
Figure 7. Bottom Layer Route
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
13
SLUU166A - December 2003 − Revised February 2004
9
Connection Diagram
INPUT POWER SOURCE
VOUT+
+VIN
−VIN
POWER
MODULE 3
VOUT−
S−
S+
+VIN
−VIN
VOUT−
POWER
MODULE 2
VOUT+
VOUT−
S−
S+
A
+VIN
−VIN
POWER
MODULE 1
VOUT+
A
VOUT−
S−
S+
VOUT+
A
A
LOAD
Figure 8. Connection Diagram for Load Share EVM when Paralleling Three Modules
14
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
Table 1. Connection Chart for Various Operating Conditions
OPERATING CONDITIONS
JUMPER POSITION
COMMENTS
JP1
Power module output voltage
greater than 1V but less than 5V
JP2
EXT.
External minimum bias voltage of 4.575V for the Loads Share Controller required at the EXTERNAL BIAS terminal block
INT.
Load Share Controller bias from the output bus voltage of each of the modules
OPEN
Connect leads from the REMOTE SENSE terminal block directly to the load for
voltage sensing at the point of load
JP3
JP1
Power module output voltage between 5V and 15V
JP2
JP3
JP4
Remote sensing
JP5
JP4
Local sensing
10
JP5
SHORTED
Voltage sensing at the J7/J8 connectors for local sensing on the EVM board
Conclusion
This user’s guide will help the user determine the appropriate components to populate the available evaluation
board in order to current share power modules using the UCC39002 advanced load-share controller. load-share
accuracies of better than 1% at full load will be realized. At light load, internal offset voltages and small signal
measurement error have a more pronounced effect, which will contribute to a larger current distribution error.
11
References
Balogh, Laszlo, The UC3902 load-Share Controller and It’s Performance in Distributed Power, TI Literature No.
SLUA128A
Dinwoodie, Lisa, 48-VIN , 12-VOUT Loadshare System Using the UCC39002 With Three DC/DC Modules, TI
Literature No. SLUA270A
Advanced 8-Pin Load-Share Controller, TI Literature No. SLUS495B
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
15
SLUU166A - December 2003 − Revised February 2004
12
Appendix
Example
NOTE:The following calculations are given as an example. Actual circuit values will vary depending
upon the specific modules used
This design uses the UCC39002 to parallel three Texas Instrument PT4484 modules whose output voltages are
nominally 5 V, the maximum output current of each module is 20 A, and a maximum output voltage adjustment
range of 2% of the output voltage.
Known Variables
N is equal to the number of paralleled units:
N+3
VOUT is equal to the nominal output voltage of the modules:
V OUT + 5 V
IOUT(max) is equal to the maximum output current of each module:
I OUT(max) + 20 A
∆VOUTADJ(max) is equal to the maximum output voltage adjustment range of the module by the Sense pins, which
is 2% of the output voltage for these modules:
DV OUTADJ(max) + 0.02 V OUT
DV OUTADJ(max) + 0.1 V
Because the output voltage of the modules is equal to 5 V, the load share controller can be biased directly from
this output bus by shorting the JP1, JP2, and JP3 connectors to the INT. positions:
V DD + 5 V
16
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
Measuring the Module’s Unity Gain Crossover Frequency
The unity gain crossover frequency of the module was measured at maximum load exactly as shown in Figure
8. The measured results are displayed in Figure 9. Measurement shows the module has a dc gain of
approximately 65 dB, a zero at approximately 1100 Hz, one pole at 10 kHz, and a double pole at approximately
200 Hz, and the crossover frequency of the module, fCOMOD, was measured to be 25.6 kHz:
f COMOD + 25.6 kHz
+Vout
DC−DC
Module
V IN
LOAD
−Vout
+Sense
−Sense
50W
XFRMR
Source Channel Channel
Out
A
B
NETWORK
ANALYZER
Figure 9. Connection Diagram for Measuring the Unity Gain Crossover Frequency of a Power Module
GAIN
vs
FREQUENCY
80
70
60
Gain − dB
50
40
30
20
10
0
−10
100
1000
10000
100000
Frequency − Hz
Figure 10. Gain-Frequency Response (PT4484 at Maximum Load)
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
17
SLUU166A - December 2003 − Revised February 2004
The results of this gain-frequency measurement are approximated in the following equation and plotted in
Figure 10:
G MOD(f) +
65
10 20
1 ) s(f)
ƪ1 ) s(f) ǒ2
1
p 10000 Hz
ǒ2
1
p 1100 Hz
Ǔ
Ǔƫ ƪ1 ) s(f) ǒ2
1
p 200 Hz
Ǔƫ
2
where:
f + 100 Hz, 200 Hz, 50 kHz
s(f) + j
2
p
f
logǒŤG MOD(f)ŤǓ
G MODULE(f) + 20
Q MODULE(f) + argǒG MOD(f)Ǔ
180
p
GAIN
vs
FREQUENCY
100
Gain − dB
50
0
−50
100
1000
10000
100000
Frequency − Hz
Figure 11. Gain-Frequency Mathematical Approximation of the PT4484 Module
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UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
PHASE
vs
FREQUENCY
0
Phase − Degrees
−50
−100
−150
−200
100
1000
10000
100000
Frequency − Hz
Figure 12. Phase-Frequency Mathematical Approximation of the PT4484 Module
Choosing the Sense Resistor
Because the current sense resistor is in series with the sense lines of the module, the voltage drop across the
sense resistor, VRSENSE, must be subtracted from the maximum voltage adjustment range of the module.
VRSENSE must be much less than ∆VADJ otherwise there would be no headroom for the load share controller
to adjust the output voltage of the module. The following equation should be true:
R SENSE
I OUT(max) t DV ADJ
The evaluation module can accommodate two 1-W resistors in parallel for each load share controller circuit. In
order to allow for de-rating, the maximum combined power dissipation is limited to 1 W for the combination.
PRSENSE(max) is equal to the desired maximum power dissipation of the sense resistors:
P RSENSE(max) + 1 W
RSENSE(max) is equal to the maximum value of the current sense resistor for the given allowable power
dissipation:
R SENSE(max) +
P RSENSE(max)
I OUT(max)
2
R SENSE(max) + 2.5 mW
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
19
SLUU166A - December 2003 − Revised February 2004
RSENSE is equal to the actual resistor value used based upon availability of standard values, two 0.002-Ω
resistors are used in parallel:
R SENSE + 1 mW
PRSENSE is equal to the calculated power dissipation of the actual resistor used and VRsense is equal to its
resultant voltage drop:
P RSENSE + R SENSE
I OUT(max)
2
P RSENSE + 0.4 W
V RSENSE + I OUT(max)
R SENSE
V RSENSE + 0.02 V
Confirm that VRSENSE is much less than ∆VADJ.
Setting the Gain of the Current Sense Amplifier
VCSO(max) is equal to the absolute maximum voltage of the CSO pin and, to avoid saturating the internal
amplifier, is limited to:
V CSO(max) + V DD * 2 V
ACSA(max) is equal to the absolute maximum allowable current sense gain before saturation:
A CSA(max) +
V CSO(max)
R SENSE
I OUT(max)
A CSA(max) + 150
ACSA is equal to the actual current sense amplifier gain chosen for this design:
A CSA + 100
VCSO is equal to the resultant output voltage of the current sense amplifier (CSA) and approximate voltage of
the load share (LS) bus:
V CSO + A CSA
R SENSE
I OUT(max)
V CSO + 2 V
ACSA is equal to the current sense amplifier gain set by RCSA1 (R22) and RCSA2 (R19):
R CSA(1) + 100 kW
R CSA(2) + 1 kW
A CSA +
R CSA(1)
R CSA(2)
A CSA + 100
20
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
fPOLE is equal to the added high frequency pole for noise roll off:
f POLE + 50 kHz
C CSA +
2
p
1
R CSA(1)
f POLE
C CSA + 31.831 pF
CCSA is equal to the actual capacitor value selected for this pole:
C CSA + 33 pF
The resultant actual pole frequency:
f POLE +
2
p
1
R CSA(1)
C CSA
f POLE + 48.229 kHz
Note that these CSA compensation components must be on both input terminals of the differential amplifier.
RLS is equal to the internal resistance of the LS pin, which is seen as a load to the master module and will cause
a subsequent increase in supply current and power dissipation of the master module:
R LS + 100 KW
I MASTERINCREASE(max) + N
ǒ
Ǔ
V CSO(max)
R LS
I MASTERINCREASE(max) + 0.09 mA
P MASTERINCREASE + V DD
I MASTERINCREASE(max)
P MASTERINCREASE + 0.45 mW
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
21
SLUU166A - December 2003 − Revised February 2004
Determining RADJ
IADJ(max) is equal to the maximum current that the internal adjust amplifier can sink:
I ADJ(max) + 3 V
500 W
I ADJ(max) + 6 mA
A resistor, RADJ, is placed between the power module’s Sense+ terminal and the load. The load share
controller’s adjust amplifier will sink current through this resistor proportional to the error amplifier output voltage,
setting up an artificial sense voltage at the module and resulting in the module adjusting its output voltage, and
current, accordingly until the error amplifier output turns off the adjust amplifier. The value of RADJ can be
calculated first by assuming the maximum voltage drop across it can be no greater than the maximum output
voltage adjustment range of the module by the Sense pins, ∆VOUTADJ(max), minus the voltage drop across the
sense resistor:
R ADJ +
DV OUTADJ(max) * I OUT(max)
R SENSE
I ADJ(max)
R ADJ + 13.3 W
This sets up a voltage at the ADJ pin, VADJ, equal to:
V ADJ + V OUT * R ADJ
I ADJ
I ADJ + 6 mA
V ADJ + 4.92 V
VADJ is not only equal to the voltage at the ADJ pin but it must also be greater than or equal to the error amplifier
output voltage, VEAO, by at least 1 V in order to keep the internal transistor from saturating:
V ADJ w V EAO ) 1 V
VEAO is clamped to a maximum of 3 V and will be equal to the voltage drop across the internal 500-Ω resistor
due to the current sunk by the adjust amplifier at ADJ:
V EAO + I ADJ
500 W
With VEAO clamped to a maximum of 3 V, and VADJ approximately equal to the output voltage (minus a small
voltage drop across the sense resistor), designs with output voltages of 4 V or greater, such as this one, will
easily meet the 1 V greater than VEAO requirement for VADJ. However, paralleling modules whose output voltage
is greater than 1 V but less than 4 V may risk saturating the internal adjust amplifier transistor if the RADJ does
not also meet the following requirement:
R ADJ w
ǒDVOUTADJ(max) * IOUT(max) RSENSEǓ 500 W
ƪVOUT * ǒDVOUTADJ(max) * IOUT(max) RSENSEǓ * 1 Vƫ
R ADJ w 10.2 W
As pointed out above, this design has an output voltage of 5 V so ADJ pin is approximately equal to 4.92 V which
naturally exceeds the maximum voltage on the EAO pin, equal to 3 V, by greater than 1 V by using an adjust
resistor that is greater than 10.2 Ω. Utilizing the full range of available adjust amplifier sink current of 6 mA,
without exceeding it, requires using an adjust resistor equal to 13.3 Ω, as calculated earlier.
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UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
SLUU166A - December 2003 − Revised February 2004
Error Amplifier Compensation
System stability requires the load share circuit’s unity gain crossover frequency to be well before the unity gain
crossover frequency of the power module, as measured in the first step of this design. In order to compensate
the error amplifier so that the load share controller’s crossover frequency does not interfere with the power
module, a zero is added to the error amplifier at least one decade before the module’s crossover frequency. In
this design, because the module’s crossover frequency is relatively high, at 25.6 kHz, the zero can be easily
placed two decades before this. fzero is equal to the desired frequency of the error amplifier compensation zero:
f ZERO +
f COMOD
100
f ZERO + 256 Hz
The absolute value of the gain of the power module is calculated at this zero frequency from the equation used
to plot Figure 3, or it can be estimated from the original gain frequency measurement, note this value is unit less,
not in dB:
ŤGMODǒfZEROǓŤ + 691.784
AV is equal to the voltage gain:
AV +
R SENSE
R LOAD
RLOAD is equal to:
R LOAD +
V OUT
I OUT(max)
10 *3
AV + 4
AADJ is equal to the adjust amplifier gain:
A ADJ +
R ADJ
500 W
A ADJ + 0.027
GM is equal to the transconductance of the internal error amplifier:
G M + 0.014 S
S+ 1
W
Combine all of the gains to determine the appropriate capacitor for compensation, CEAO:
C EAO +
2
GM
p f ZERO
A CSA
AV
A ADJ Ť G MOD ǒf ZEROǓ Ť
C EAO + 64.065 mF
Actual capacitor value used:
C EAO + 68 mF
REAO is equal to the series resistor used in the error amplifier compensation:
R EAO +
2
p
1
f ZERO
C EAO
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
23
SLUU166A - December 2003 − Revised February 2004
R EAO + 10 W
Actual resistor value used:
R EAO + 10 W
A bode plot of the load share open loop gain frequency response and comparing it to the original gain frequency
response of the individual module is shown in Figure12:
ǒ
G ERRORAMP(f) + G M
1
s(f)
C EAO
) R EAO
Ǔ
G LSOPENLOOP(f) +
20
logǒŤG CSA(f)ŤǓ ) 20
logǒŤA VŤǓ ) 20
logǒŤA ADJŤǓ ) 20
G TOTAL(f) + G LSOPENLOOP(f) ) G MODULE(f)
GAIN
vs
FREQUENCY
80
60
GMODULE (f)
40
Gain − dB
20
0
GTOTAL (f)
−20
−40
GLSOPENLOOP (f)
−60
−80
100
1000
10000
100000
Frequency − Hz
Figure 13. Load Share Open Loop Gain Frequency Response
24
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
logǒŤG ERRORAMP(f)ŤǓ
SLUU166A - December 2003 − Revised February 2004
Figure 14. Schematic of Three Paralleled PT4484 Modules
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
25
SLUU166A - December 2003 − Revised February 2004
LOAD SHARE ERROR RESULT FOR THE
PT4484 MODULES
10
8
Current Sharing Error − %
6
4
Module 3
2
0
Module 2
−2
Module 1
−4
−6
−8
−10
20
30
40
50
60
Total System Output Current − A
Figure 15. Resultant Load Current Sharing Accuracy, as Measured Across Shunts from the Output of
Each Module.
26
UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A
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