UCC3919PW


 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005        FEATURES D Precision Fault Threshold D Charge Pump for Low RDS(on) High Side D D D D D D D D D DESCRIPTION The UCC3919 family of hot swap power managers provide complete power management, hot swap, and fault handling capability. The UCC3919 features a duty ratio current limiting technique, which provides peak load capability while limiting the average power dissipation of the external pass transistor during fault conditions. The UCC3919 has two reset modes, selected with the TTL/CMOS compatible L/R pin. In one mode, when a fault occurs the IC repeatedly tries to reset itself at a user defined rate, with user defined maximum output current and pass transistor power dissipation. In the other mode the output latches off and stays off until either the L/R pin is reset or the shutdown pin is toggled. The on board charge pump circuit provides the necessary gate voltage for an external N-channel power FET. Drive Differential Sense Inputs Programmable Average Power Limiting Programmable Linear Current Control Programmable Fault Time Fault Output Indicator Manual and Automatic Reset Modes Shutdown Control With Programmable Softstart Undervoltage Lockout Electronic Circuit Breaker Function TYPICAL APPLICATION DIAGRAM RS VDD CSN GATE CSP LINEAR CURRENT AMP IMAX FROM SUPPLY 3 V TO 8 V + TO LOAD IBIAS TIMER CT CAP GND UDG−01068  
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 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 AVAILABLE OPTIONS PACKAGE DEVICES TJ D PACKAGE N PACKAGE PW PACKAGE 0°C to 70°C UCC3919D UCC3919N UCC3919PW −40°C to 85°C UCC2919D UCC2919N UCC2919PW N PACKAGE TOP VIEW IMAX IBIAS N/C CAP L/R SD FLT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 D AND PW PACKAGES (TOP VIEW) CSP VDD CSN GND GATE PL CT 1 2 3 4 5 6 7 8 IMAX IBIAS N/C CAP L/R SD N/C FLT 16 15 14 13 12 11 10 9 CSP VDD CSN GND GATE PL N/C CT functional block diagram VDD 13 CSP 14 LINEAR CURRENT AMPLIFIER + OVERCURRENT COMPARATOR CSN 12 − + 4 DRIVER 10 GATE CAP + VDD − 50mV CHARGE PUMP UVLO 200mV + IMAX OVERLOAD COMPARATOR − VDD 1 1.5v UVLO + + VDD 36µA IBIAS 2 1X 1X UVBIAS SET DOMINANT S Q R Q FLT SD PL 9 CT − 0.5V + S Q R Q 8 − GND 11 S Q R Q 270K RESET DOMINANT 1.2µA SD 5 6 LR SD NOTE: Pins shown for 14-pin package. 2 FLT 7 + 1.5V UVBIAS www.ti.com FLT 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 absolute maximum ratings over operating free-air temperature (unless otherwise noted)†} VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 10 V Pin voltage (all pins except CAP and GATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Pin voltage (CAP and GATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 18 V PL current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA to –10 mA IBIAS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 3 mA Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Lead temperature (soldering, 10sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package. electrical characteristics, VDD = 5 V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the UCC2919, all voltages are with respect to GND, TA = TJ, (unless otherwise specified) input supply PARAMETER Supply current Shutdown current TEST CONDITIONS MIN TYP MAX UNITS VDD = 3 V 0.5 1 mA VDD = 8 V 1 1.5 mA SD = 0.2 V 1 7 µA undervoltage lockout PARAMETER TEST CONDITIONS Minimum voltage to start Minimum voltage after start Hysteresis MIN TYP MAX UNITS 2.35 2.75 3 V 1.9 2.25 2.5 V 0.25 0.5 0.75 V IBIAS PARAMETER A < IOUT < 15 µA) A) Output voltage, (0 µA TEST CONDITIONS MIN TYP MAX UNITS 25°C, referred to CSP 1.47 1.5 1.53 V Over temperature range, referred to CSP 1.44 1.5 1.56 V 1 2 Maximum output current www.ti.com mA 3 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 electrical characteristics, VDD = 5 V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the UCC2919, all voltages are with respect to GND, TA = TJ, (unless otherwise specified) current sense PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 3 V ≤ VDD ≤ 8 V –55 –50 –45 mV referred to CSP, 3 V ≤ VDD ≤ 8 V –120 –100 –80 mV referred to CSP, 3 V ≤ VDD ≤ 8 V –440 –400 –360 mV referred to CSP, 3 V ≤ VDD ≤ 8 V –360 –300 –240 mV Referred to VDD, 3 V ≤ VDD ≤ 8 V, See Note 1 –1.5 0.2 V Referred to VDD, 3 V ≤ VDD ≤ 8 V, See Note 1 0 0.2 V Over current comparator offset Referred to CSP, Linear current amplifier offset VIMAX = 100 mV, VIMAX = 400 mV, Overload comparator offset VIMAX = 100 mV, CSN input common mode voltage range CSP input common mode voltage range Input bias current CSN 1 5 µA Input bias current CSP 100 200 µA current fault timer PARAMETER TEST CONDITIONS MIN TYP MAX UNITS –56 –35 –16 µA CT discharge current VCT = 1 V VCT = 1 V 0.5 1.2 1.9 µA On time duty cycle in fault IPL = 0 CT charge current 1.5 3 6 % CT fault threshold 1.0 1.5 1.7 V CT reset threshold 0.25 0.5 0.75 V IMAX PARAMETER Input bias current TEST CONDITIONS VIMAX = 100 mV, referred to CSP MIN –1 TYP 0 MAX 1 UNITS µA power limiting PARAMETER TEST CONDITIONS Voltage on PL IPL = –250 µA, IPL = –1.5 mA, On time duty cycle in fault IPL = –250 µA IPL = –1.5 mA TYP MAX UNITS referred to VDD –1.0 –1.4 –1.9 referred to VDD –0.5 –1.8 –2.2 V 0.25 0.5 1 % 0.05 0.1 0.2 % NOTES: 1. Ensured by design. Not 100% production tested. 4 MIN www.ti.com V 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 electrical characteristics, VDD = 5 V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the UCC2919, all voltages are with respect to GND, TA = TJ, (unless otherwise specified) SD and L/R inputs PARAMETER TEST CONDITIONS MIN TYP Input voltage low MAX 0.8 Input voltage high 2 L/R input current SD internal pulldown impedance UNITS V V 1 3 6 µA 100 270 500 kΩ FLT output PARAMETER TEST CONDITIONS Output leakage current VDD = 5 V Output low voltage IOUT = 10 mA MIN TYP MAX UNITS 10 µA 1 V FET gate driver and charge pump PARAMETER Peak output current Peak sink current TEST CONDITIONS VCAP = 15 V, VGATE = 5 V VGATE = 10 V MIN –3 –1 MAX UNITS –0.25 mA 20 Fault delay Maximum output voltage TYP mA 100 300 ns VDD = 3 V, average IOUT = 1 µA 8 10 12 V VDD = 8 V, average IOUT = 1 µA 12 14 16 V 6.5 8.8 10.1 V 6.5 9.9 11.5 V 50 100 150 kΩ Charge pump UVLO minimum voltage to start VDD = 3 V Charge pump source impedance VDD = 5 V, VDD = 8 V average IOUT = 1 µA pin descriptions CAP A capacitor is placed from this pin to ground to filter the output of the on board charge pump. A 0.01-µF to 0.1-µF capacitor will work in most applications. Refer to TI literature number SLUA339 application note, Sizing the UCC3919 Charge−Pump Capacitor, to determine the exact capacitance. CSN The negative current sense input signal. CSP The positive current sense input signal. Input to the duty cycle timer. CT Input to the duty cycle timer. A capacitor is connected from this pin to ground, setting the off time and maximum on time of the over-current protection circuit. FLT Fault indicator. This open drain output will pull low under any fault condition where the output driver is disabled. This output is disabled when the IC is in low current standby mode. www.ti.com 5 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 pin descriptions (continued) GATE The output of the linear current amplifier. This pin drives the gate of an external N-channel MOSFET pass transistor. The linear current amplifier control loop is internally compensated, and ensured stable for output load (gate) capacitance between 100 pF and 0.01 µF. In applications where the GATE voltage (or charge pump voltage) exceeds the maximum gate-to-source voltage ratings (VGS) for the external N-channel MOSFET, a Zener clamp may be added to the gate of the MOSFET. No additional series resistance is required since the internal charge pump has a finite output impedance of 100-kΩ typical. GND The ground reference for the device. IBIAS Output of the on board bias generator internally regulated to 1.5 V below CSP. A resistor divider between this pin and CSP can be used to generate the IMAX voltage. The bias circuit is internally compensated, and requires no bypass capacitance. If an external bypass is required due to a noisy environment, the circuit will be stable with up to 0.001 µF of capacitance. The bypass must be to CSP, since the bias voltage is generated with respect to CSP. Resistor R2 (Figure 5) should be greater than 50 kΩ to minimize the effect of the finite input impedance of the IBIAS pin on the IMAX threshold. IMAX Used to program the maximum allowable sourcing current. The voltage on this pin is with respect to CSP. If the voltage across the shunt resistor exceeds this voltage the linear current amplifier lowers the voltage at GATE to limit the output current to this level. If the voltage across the shunt resistor goes more than 200 mV beyond this voltage, the gate drive pin GATE is immediately driven low and kept low for one full off time interval. L/R Latch/Reset. This pin sets the reset mode. If L/R is low and a fault occurs the device will begin duty ratio current limiting. If L/R is high and a fault occurs, GATE will go low and stay low until L/R is set low. This pin is internally pulled low by a 3-µA nominal pulldown. PL Power Limit. This pin is used to control average power dissipation in the external MOSFET. If a resistor is connected from this pin to the source of the external MOSFET, the current in the resistor will be roughly proportional to the voltage across the FET. As the voltage across the FET increases, this current is added to the fault timer charge current, reducing the on time duty cycle from its nominal value of 3% and limiting the average power dissipation in the FET. SD Shutdown pin. If this pin is taken low, GATE will go low, and the IC will go into a low current standby mode and CT will be discharged. This TTL compatible input must be driven high to turn on. VDD The power connection for the device. 6 www.ti.com 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION The UCC3919 monitors the voltage drop across a high side sense resistor and compares it against three different voltage thresholds. These are discussed below. Figure 1 shows the UCC3919 waveforms under fault conditions. fault threshold The first threshold is fixed at 50 mV. If the current is high enough such that the voltage on CSN is 50 mV below CSP, the timing capacitor CT begins to charge at about 35 µA if the PL pin is open. (Power limiting will be discussed later). If this threshold is exceeded long enough for CT to charge to 1.5 V, a fault is declared and the external MOSFET will be turned off. It will either be latched off (until the power to the circuit is cycled, the L/R pin is taken low, or the SD pin is toggled), or will retry after a fixed off time (when CT has discharged to 0.5 V), depending on whether the L/R pin is set high or low by the user. The equation for this current threshold is simply: I FAULT + 0.05 R SENSE (1) The first time a fault occurs, CT is at ground, and must charge to 1.5 V. Therefore: t FAULT +t ON(sec) + C t(mF) 1.5 35 (2) In the retry mode, the timing capacitor will already be charged to 0.5 V at the end of the off time, so all subsequent cycles will have a shorter ton time, given by: t FAULT ^t ON(sec) + C (mF) T 35 (3) Note that these equations for tON are without the power limiting feature (RPL pin open). The effects of power limiting on tON will be discussed later. The off time in the retry mode is set by CT and an internal 1.2-µA sink current. It is the time it takes CT to discharge from 1.5 V to 0.5 V. The equation for the off time is therefore: t OFF(sec) + C mF T 1.2 (4) shutdown characteristics When the SD pin is set to TTL high (above 2 V) the UCC3919 is ensured to be enabled. When SD is set to a low TTL (below 0.8 V) the UCC3919 is ensured to be disabled, but may not be in ultra low current sleep mode. When SD is set to 0.2 V or less, the UCC3919 is ensured to be disabled and in ultra low current sleep mode. See Figure 1. At cold temperatures, (below 0°C), the UCC2919 shutdown supply current delays gradually over time and may take >1 minute to drop below the 7-µA shutdown current limit. However, the gate output is driven low immediately when the SD pin is pulled low and does not exhibit a temperature dependency. www.ti.com 7 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION SUPPLY CURRENT vs SD PIN VOLTAGE ICC − Supply Current − µA 10,000 1000 100 10 1 0.1 0.01 0.0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 VSD − SD Pin Voltage − V Figure 1 IMAX threshold The second threshold is programmed by the voltage on IMAX (measured with respect to the CSP pin). This controls the maximum current, IMAX, that the UCC3919 will allow to flow into the load during the MOSFET on time. A resistive divider connected between IBIAS and CSP generates the programming voltage. When the drop across the sense resistor reaches this voltage, a linear amplifier reduces the voltage on GATE to control the external MOSFET in a constant current mode. During this time CT is charging, as described above. If this condition lasts long enough for CT to charge to 1.5 V, a fault will be declared and the MOSFET will be turned off. The IMAX current is calculated as follows: I V *V IMAX + CSP MAX R SENSE (5) Note that if the voltage on the IMAX pin is programmed to be less than 50 mV below CSP, then the UC3919 will control the MOSFET in a constant current mode all the time. No fault will be declared and the MOSFET will remain on because IMAX is less than IFAULT. 8 www.ti.com 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION overload threshold There is a third threshold which, if exceeded, will declare a fault and shutdown the external MOSFET immediately, without waiting for CT to charge. This overload threshold is 200 mV greater than the IMAX threshold (again, this is with respect to CSP). This feature protects the circuit in the event that the external MOSFET is on, with a load current below IMAX, and a short is quickly applied across the output. This allows hot-swapping in cases where the UCC3919 is already powered up (on the backplane) and capacitors are added across the output bus. In this case, the load current could rise too quickly for the linear amplifier to reduce the voltage on GATE and limit the current to IMAX. If the overload threshold is reached, the MOSFET will be turned off quickly and a fault declared. A latch is set so that CT can be charged, ensuring that the MOSFET will remain off for the same period as defined above before retrying. The overload current is: I V *V ) 0.2 IMAX 0.2 + CSP +I ) MAX R OVERLOAD R SENSE SENSE (6) Note that IOVERLOAD may be much greater than IMAX, depending on the value of RSENSE. power limiting A power limiting feature is included which allows the power dissipated in the external MOSFET to be held relatively constant during a short, for different values of input voltage. This is accomplished by connecting a resistor from the output (source of the external MOSFET) to PL. When the output voltage drops due to a short or overload, an internal bias current is generated which is equal to: I PL ^ ǒVIN * VOUT * VPLǓ R (7) PL This current is used to help charge the timing capacitor in the event that the load current exceeds IFAULT. (A simplified schematic of the circuit internal to the UCC3919 is shown in Figure 2.) The result is that the on time of the MOSFET during current limit is reduced as the input voltage is increased. This reduces the effective duty cycle, holding the average power dissipated constant. VDD VDD UCC3919 POWER LIMIT 1X 1X SD TO GATE CT FLT RPL PL IPL TO LOAD UDG−98124 Figure 2. Power Limiting Circuit www.ti.com 9 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION It can be seen that power limiting will only occur when IPL is > 0 (it cannot be negative). For power limiting to begin to occur, the voltage drop across the MOSFET must be greater than VDD−VPL or 1.4 V(typ). V IN *V OUT w 1.4 V (8) The on time using RPL is defined as: t ON + C I PL T ) 35 DV 10 −6 where DV + 1 V , (9) The graph in Figure 4 illustrates the effect of RPL on the average MOSFET power dissipation into a short. The equation for the average power dissipation during a short is: P P I + MAX DISS I V PL IN ) 35 10 −6 1.2 10 −6 , or (10) I V t IN ON + MAX DISS t )t ON OFF If PL is left unconnected, the power limiting feature will not be exercised. In the retry mode, the duty cycle during a fault will be nominally 3%, independent of input voltage. The average power dissipation in the external MOSFET with a shorted output will be proportional to input voltage, as shown by the equation: P DISS +I MAX V 0.033 IN (11) calculating CT(min) for a given load capacitance without power limiting To ensure recovery from an overload when operating in the retry mode, there is a maximum total output capacitance which can be charged for a given tON (fault time) before causing a fault. For a worst case situation of a constant current load below the fault threshold, CT(min) for a given output load capacitance (without power limiting) can be calculated from: C T(min) V + IN 35 10 −6 OUT I *I MAX LOAD C (12) A larger load capacitance or a smaller CT will cause a fault when recovering from an overload, causing the circuit to get stuck in a continuous hiccup mode. To handle larger capacitive loads, increase the value of CT. The equation can be easily re-written, if desired, to solve for COUT(max) for a given value of CT. For a resistive load of value RL and an output cap COUT, CT(min) can be smaller than in the constant current case, and can be estimated from: −C C T(min) + OUT R ǒ ȏn 1 * L 28 V I IN MAX R Ǔ L 10 3 (13) Note that in the latch mode (or when first turning on in the retry mode), since the timing capacitor is not recovering from a previous fault, it is charging from 0 V rather than 0.5 V. This allows up to 50% more load capacitance without causing a fault. 10 www.ti.com 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION estimating CT(min) when using power limiting If power limiting is used, the calculation of CT(min) for a given COUT becomes considerably more complex, especially with a resistive load. This is because the CT charge current becomes a function of VOUT, which is changing with time. The amount of capacitance that can be charged (without causing a fault) when using power limiting will be significantly reduced for the same value CT, due to the shorter tON time. The charge current contribution from the power limiting circuit is defined as: I PL ^ ǒVIN * VOUT * VPLǓ R (14) PL UDG−97073 t0: Normal condition − Output current is nominal, output voltage is at positive rail, VCC. t1: Fault control reached − Output current rises above the programmed fault value, CT begins to charge with 35 µA + IPL. t2: Maximum current reached − Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t3: Fault occurs − CT has charged to 1.5 V, fault output goes low, the FET turns off allowing no output current to flow, VOUT discharges to GND. t4: Retry − CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT increases. t3 to t5: Illustrates < 3% duty cycle depending upon RPL selected. t6 = t4 t7: Fault released, normal condition − return to normal operation of the circuit breaker Figure 3. www.ti.com 11 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION constant current load For a constant current load in parallel with a load capacitor, the load capacitor will charge linearly. During that time: I PL(avg) ^ ǒVIN * VPLǓ 2 R V PL 2 (15) IN Modifying equation (12) yields: V C T(min) IN C OUT ^ ȱǒV *V Ǔ2 ȧ2 INRPL PLVIN ) 35 Ȳ I MAX *I ȳ ȧ ȴ 10 −6 LOAD (16) MOSFET AVERAGE SHORT CIRCUIT POWER DISSIPATION vs INPUT VOLTAGE 0.30 For IMAX = 7 A RPL = 24.9 k 0.25 Power Dissipation − W RPL = 20.0 k 0.20 RPL = 15.0 k 0.15 RPL = 10.0 k 0.10 0.05 0 1 2 3 4 VIN − Input Voltage − V Figure 4 12 www.ti.com 5 6 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION parallel R-C load Determining CT(min) for a parallel R-C load is more complex. First, the expression for the output voltage as a function of time is: V OUT(t) +I MAX ȡ − TSTART ȣ R 1 * e R LOAD C OUTȧ LOADȧ Ȣ Ȥ Solving for TSTART when VOUT = VIN yields: T START +*R C LOAD OUT ǒ ǒ ȏn 1 * V I MAX IN R (17) ǓǓ LOAD (18) Assuming that the device is operating in the retry mode, where CT is charging from 0.5 V to just below 1.5 V in time (t), CT is defined as: I dt +I C + CT T CT dV I CT ǒ PL ) 35 + I dt, where (19) Ǔ 10 −6 Substituting equation (15) into (19) yields: ȡ ǒV * V Ǔ2 IN PL ) 35 C + T(min) ȧ2 R V PL IN Ȣ ȣ ȧ Ȥ 10 −6 dt (20) This yields the following expression for CT(min) for a resistive load with power limiting. By substituting the value calculated for TSTART in equation (18) for dt, CT(min) is determined. ȱ ǒV * V Ǔ2 IN PL C + ) 35 T(min) ȧ2 R V PL IN Ȳ ȳ ȧ ȴ 10 −6 T START www.ti.com (21) 13 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION example The example in Figure 5 shows the UCC3919 in a typical application. A low value sense resistor and N-channel MOSFET minimize losses. With the values shown for R1, R2, and RS, the overcurrent fault will be 5-A nominal. Linear current limiting (IMAX) will occur at 7.14 A and the overload comparator will trip at 27 A. The calculations are shown below. I I I FAULT MAX + 0.05 + 0.05 + 5 A 0.01 R S V *V IMAX + 1.5 R1 + CSP + 7.14 A (R1 ) R2) R R S S OVERLOAD T OFF(sec) +I + MAX ) 0.2 + 7.14 A ) 0.2 + 27.14 A 0.01 R S C mF T + 0.01 + 8.33 ms 1.2 1.2 With the value shown for RPL: I t PL(typ) ON P (22) (output shorted) + (shorted) + ǒ V (23) (24) (25) Ǔ *V IN PL R PL ǒ Ǔ + 5 * 1.6 + 340 mA 10 k (26) C I PL −6 T + 0.01 10 + 27 ms 375 mA ) 35 10 −6 I V t IN ON + 7.14 5 27 ms + 0.12 W (shorted) + MAX DISS t )t 27 ms ) 8.33 10 −3 ON OFF (27) (28) For a worst case 1 Ω resistive load: COUT(max) ≅ 47 µF. For a worst case 5 A constant current load: COUT(max) ≅ 27 µF. With L/R grounded, the part will operate in the retry or hiccup mode. The values shown for CT and RPL will yield a nominal duty cycle of 0.32% and an off time of 8.3 ms. With a shorted output, the average steady state power dissipation in Q1 will be less than 100 mW over the full input voltage range. If power limiting is disabled by opening RPL, then: t FAULT P +t ON(sec) + C mF T 35 1 + 287 ms I V t IN ON + 7.14 5 287 10 −6 + 1.2 W (withV + 5 V) (shorted) + MAX IN DISS t )t 287 10 −6 ) 8.33 10 −3 ON OFF For a worst case 1-Ω resistive load: COUT(max) ≅ 220 µF. For a worst case 5 A constant current load: COUT(max) ≅ 120 µF. 14 www.ti.com (29) (30) 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 APPLICATION INFORMATION C IN V IN 10k Ω C SS R1 4.99k 1 BS584 Note 1 IMAX R2 100k 2 IBIAS 3 N/C 4 CAP 5 L/R CSP 14 VDD 13 CSN 12 GND 11 GATE 10 PL 9 RS 0.01 Ω 0.01 µ F 6 R PL 10k V OUT SD CT 0.01 µ F 7 FLT CT C OUT R LOAD 8 NOTES: 1. Optional FET speeds discharge of CSS during fault or shutdown UDG−98137 Figure 5. Application Circuit THERMAL INFORMATION steady state conditions In normal operation, with a steady state load current below IFAULT, the power dissipation in the external MOSFET will be: P DISS +R I DS(on) 2 LOAD (31) The junction temperature of the MOSFET can be calculated from: ǒ T +T ) P J A DISS q Ǔ JA (32) Where TA is the ambient temperature and θJA is the MOSFET’s thermal resistance from junction to ambient. If the device is on a heatsink, then the following equation applies: q JA +q JC )q CS )q SA (33) Where θJC is the MOSFET’s thermal resistance from junction to case, θCS is the thermal resistance from case to sink, and θSA is the thermal resistance of the heatsink to ambient. The calculated TJ must be lower than the MOSFET’s maximum junction temperature rating, therefore: T q JA ¦ *T J(max) A P DISS (34) www.ti.com 15 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 THERMAL INFORMATION transient thermal impedance During a fault condition in the retry mode, the average MOSFET power dissipation will generally be quite low due to the low duty cycle, as defined by: P I V t IN ON (with output shorted) + MAX DISS(avg) t )t ON OFF (35) (In the latch mode, tOFF will be the time between a fault and the time the device is reset.) However, the pulse power in the MOSFET during tON, with the output shorted, is: P DISS(pulse) +I V MAX IN (with output shorted) (36) In choosing tON for a given VIN, IMAX, and duty cycle it is important to consult the manufacturer’s transient thermal impedance curves for the MOSFET to make sure the device is within its safe operating area. These curves provide the user with the effective thermal impedance of the device for a given time duration pulse and duty cycle. Note that some of the impedance curves are normalized to one, in which case the transient impedance values must be multiplied by the dc (steady state) thermal resistance, θJC. For duty cycles not shown in the manufacturer’s curves, the transient thermal impedance for any duty cycle and tON time (given a square pulse) can be estimated from [1]: q JC(trans) ǒ + D q JC Ǔ ) (1 * D) q SP (37) t where D is the duty cycle: t ON . )t ON OFF and θSP is the single pulse thermal impedance given in the transient thermal impedance curves for the time duration of interest (tON). Note that these are absolute numbers, not normalized. If the given single pulse impedance is normalized, it must first be multiplied by θJC before using in the equation above. This effective transient thermal impedance, when multiplied by the pulse power, will give the transient temperature rise of the die. To keep the junction temperature below the maximum rating, the following must be true: *T J(max) C P DISS(pulse) T q JC(trans) + (38) If necessary, the junction temperature rise can be reduced by reducing ton (using a smaller value for CT), or by reducing the duty cycle using the power limiting feature already discussed. Note that in either case, the amount of load capacitance, COUT, that can be charged before causing a fault, will also be reduced. 16 www.ti.com 

 SLUS374C − JULY 1999 − REVISED NOVEMBER 2005 THERMAL INFORMATION safety recommendations Although the UCC3919 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. for this reason, if the UCC3919 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3919 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. references 1. International Rectifier, HEXFET Power MOSFET Designer’s Manual, Application Note 949B, Current Ratings, Safe Operating Area, and High Frequency Switching Performance of Power HEXFETs, pp.1553−1565, September 1993. www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 30-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) UCC2919D OBSOLETE SOIC D 16 TBD Call TI Call TI -40 to 85 UCC2919D UCC2919DG4 OBSOLETE SOIC D 16 TBD Call TI Call TI -40 to 85 UCC2919D UCC2919DTR OBSOLETE SOIC D 16 TBD Call TI Call TI -40 to 85 UCC2919D UCC2919DTRG4 OBSOLETE SOIC D 16 TBD Call TI Call TI -40 to 85 UCC2919D UCC2919N OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 85 UCC2919PW OBSOLETE TSSOP PW 16 TBD Call TI Call TI -40 to 85 2919 UCC2919PWG4 OBSOLETE TSSOP PW 16 TBD Call TI Call TI -40 to 85 2919 UCC3919D OBSOLETE SOIC D 16 TBD Call TI Call TI 0 to 70 UCC3919D UCC3919DTR OBSOLETE SOIC D 16 TBD Call TI Call TI 0 to 70 UCC3919D UCC3919N OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 UCC3919PW OBSOLETE TSSOP PW 16 TBD Call TI Call TI 0 to 70 3919 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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