UCC3921DG4

UCC1921 UCC2921 UCC3921 Latchable Negative Floating Hot Swap Power Manager FEATURES DESCRIPTION • Precision Fault Threshold The UCC3921 family of negative floating hot swap power managers provides complete power management, hot swap, and fault handling capability. The IC is referenced to the negative input voltage and is powered through an external resistor connected to ground, which is essentially a current drive as opposed to the traditional voltage drive. The onboard 10V shunt regulator protects the IC from excess voltage and serves as a reference for programming the maximum allowable output sourcing current during a fault. All control and housekeeping functions are integrated and externally programmable. These include the fault current level, maximum output sourcing current, maximum fault time, selection of Retry or Latched mode, soft start time, and average power limiting. In the event of a constant fault, the internal timer will limit the on time from less than 0.1% to a maximum of 3% duty cycle. The duty cycle modulation depends on the current into PL, which is a function of the voltage across the FET, thus limiting average power dissipation in the FET. The fault level is fixed at 50mV across the current sense amplifier to minimize total • Programmable: Average Power Limiting, Linear Current Control, Overcurrent Limit and Fault Time • Fault Output Indication Signal • Automatic Retry Mode or Latched Operation Mode • Shutdown Control • Undervoltage Lockout • 250µs Glitch Filter on the SDFLTCH pin • 8-Pin DIL and SOIC (continued) BLOCK DIAGRAM UDG-99052 3/98 UCC1921 UCC2921 UCC3921 DESCRIPTION (continued) CT charges to 2.5V, the output device is turned off and performs a retry some time later (provided that the selected mode of operation is Automatic Retry Mode). When the output current reaches the maximum sourcing current level, the output acts as a current source, limiting the output current to the set value defined by IMAX. dropout. The fault current level is set with an external current sense resistor, while the maximum allowable sourcing current is programmed with a voltage divider from VDD to generate a fixed voltage on IMAX. The current level, when the output acts as a current source, is equal to VIMAX/RSENSE. If desired, a controlled current start up can be programmed with a capacitor on IMAX. Other features of the UCC3921 include undervoltage lockout, 8-pin Small Outline (SOIC) and Dual-In-Line (DIL) packages, and a Latched Operation Mode option, in which the output is latched off once CT charges to 2.5V and stays off until either SDFLTCH is toggled (for greater than 1ms) or the IC is powered down and then back up. When the output current is below the fault level, the output device is switched on. When the output current exceeds the fault level, but is less than the maximum sourcing level programmed by IMAX, the output remains switched on, and the fault timer starts charging CT. Once CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS IVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA SDFLTCH Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA PL Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA IMAX Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-8 , SOIC-8 (Top View) N or J, D Packages All voltages are with respect to VSS (the most negative voltage). Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = 0°C to 70°C for the UCC3921 and –40°C to 85°C for the UCC2921, and –55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1nF (the minimum allowable value), there is no resistor connected between the SDFLTCH and VSS pins. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ISOURCE = 2mA 9 1 2 mA 9.5 10.0 V ISOURCE = 10mA 9.15 9.6 10.15 V 6 7 8 V 47.5 50 53.5 mV 46 50 53.5 mV 50 500 nA VDD Section IDD Regulator Voltage UVLO Off Voltage Fault Timing Section Overcurrent Threshold TJ = 25°C Over Operating Temperature Overcurrent Input Bias CT Charge Current VCT = 1V, IPL = 0 –50 –36 –22 µA Overload Condition, VSENSE - VIMAX = 300mV –1.7 –1.2 –0.7 mA CT Discharge Current VCT = 1V, IPL = 0 0.6 1 1.5 µA CT Fault Threshold 2.2 2.45 2.6 V CT Reset Threshold 0.41 0.49 0.57 V 1.7 2.7 3.7 % Output Duty Cycle Fault Condition, IPL = 0 2 UCC1921 UCC2921 UCC3921 ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = 0°C to 70°C for the UCC3921 and –40°C to 85°C for the UCC2921, and –55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1nF (the minimum allowable value), there is no resistor connected between the SDFLTCH and VSS pins. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS IOUT = 0mA 8.5 10 V IOUT = –1mA 6 8 V Output Section Output High Voltage Output Low Voltage IOUT = 0mA, VSENSE – VIMAX = 100mV 0 10 mV IOUT = 2mA, VSENSE – VIMAX = 100mV 200 600 mV Linear Amplifier Section Sense Control Voltage VIMAX = 100mV 85 100 115 mV VIMAX = 400mV 370 400 430 mV 50 500 nA 4.35 4.85 5.35 V Input Bias Power Limiting Section VSENSE Regulator Voltage IPL = 64µA Duty Cycle Control IPL = 64µA 0.6 1.2 1.7 % IPL = 1mA 0.045 0.1 0.17 % 300 500 ns mV Overload Section Delay to Output Note 1 Output Sink Current VSENSE – VIMAX = 300mV 40 100 Threshold Relative to IMAX 140 200 260 mA 3 5 VDD+1 V VSDFLTCH = 5V 50 110 250 µA 250 500 1000 µs 6 9.5 5 8.5 Shutdown/Fault/Latch Section Shutdown Threshold Input Current Filter Delay Time (Delay to Output) Fault Output High ISDFLTCH = –100µA Fault Output Low Output Duty Cycle Fault Condition, IPL = 0 1.7 V V 0 10 2.7 3.7 % 0 % ISDFLTCH = –100µA, Fault Condition, IPL = 0 mV Note 1: Guaranteed by design. Not 100% tested in production. PIN DESCRIPTIONS voltage on IMAX over the current sense resistor. If desired, a controlled current start up can be programmed with a capacitor on IMAX, and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an RC network. CT: A capacitor is connected to this pin in order to set the fault time. The fault time must be longer than the time to charge external load capacitance. The fault time is defined as: TFAULT = 2 • CT ICH OUT: This pin provides gate output drive to the MOSFET pass element. where ICH = 36µA + IPL, and IPL is the current into the power limit pin. Once the maximum fault time is reached the output will shutdown for a time given by: PL: This feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected from this pin to the drain of the NMOS pass element. When the voltage across the NMOS exceeds 5V, current will flow into the PL pin which adds to the fault timer charge current, reducing the duty cycle from the 3% level. When IPL>>36µA, then the average MOSFET power dissipation is given by: TSD = 2 • 10 6 • CT IMAX: This pin programs the maximum allowable sourcing current. Since VDD is a regulated voltage, a voltage divider can be derived from VDD to generate the program level for IMAX. The current level at which the output appears as a current source is equal to the PMOSFET avg = IMAX • 1 • 10 −6 • R PL 3 UCC1921 UCC2921 UCC3921 PIN DESCRIPTIONS (continued) SENSE: Input voltage from the current sense resistor. When there is greater than 50mV across this pin with respect to VSS, then a fault is sensed, and CT starts to charge. If an 5k < RLATCH < 250kΩ resistor is placed from this pin to VSS, then the latched operating mode will be invoked. Upon the occurrence of a fault, under the latched mode of operation, once the CT capacitor charges up to 2.5V the NMOS pass element latches off. A retry will not periodically occur. To reset the latched off device, either SDFLTCH is toggled high for a duration greater than 1ms or the IC is powered down and then up. SDFLTCH: This pin provides fault output indication, shutdown control, and operating mode selection. Interface into and out of this pin is usually performed through level shift transistors. When open, and under a non-fault condition, this pin pulls to a low state with respect to VSS. When a fault is detected by the fault timer, or undervoltage lockout, this pin will drive to a high state with respect fo VSS, indicating the NMOS pass element is OFF. When > 250µA is sourced into this pin for > 1ms, it drives high causing the output to disable the NMOS pass device. VDD: Current driven with a resistor to a voltage approximately 10V more positive than VSS. Typically a resistor is connected to ground. The 10V shunt regulator clamps VDD approximately 10V above VSS, and is also used as an output reference to program the maximum allowable sourcing current. VSS: Ground reference for the IC and the most negative voltage available. APPLICATION INFORMATION UDG-96275-1 Figure 1. Fault Timing Circuitry for the UCC3921, Including Power Limit Overload 4 UCC1921 UCC2921 UCC3921 APPLICATION INFORMATION (continued) Figure 1 shows the detailed circuitry for the fault timing function of the UCC3921. For the time being, we will discuss a typical fault mode, therefore, the overload comparator, and current source I3 does not work into the operation. Once the voltage across the current sense resistor, RS, exceeds 50mV, a fault has occurred. This causes the timing capacitor to charge with a combination of 36µA plus the current from the power limiting amplifier. The PL amplifier is designed to only source current into the CT pin and to begin sourcing current once the voltage across the output FET exceeds 5V. The current IPL is related to the voltage across the FET with the following expression: V − 5V I PL = FET RPL where VFET is the voltage across the NMOS pass device. Later it will be shown how this feature will limit average power dissipation in the pass device. Note that under a condition where the output current is more than the fault level, but less than the max level, VOUT ≈ VSS (input voltage), IPL = 0, the CT charging current is 36µA. UDG-96276 t5 = t3: Illustrates 3% duty cycle. t0: Safe condition. Output current is nominal, output voltage is at the negative rail, VSS. t6 = t4: Retry. CT has discharged to 0.5V, but fault is still exceeded, CT begins charging again, FET is on, VOUT pulled down towards VSS. t1: Fault control reached. Output current rises above the programmed fault value, CT begins to charge at ~36µA. t7: Output short circuit. If VOUT is short circuited to ground, CT charges at a higher rate depending upon the values for VSS and RPL. t2: Maximum current reached. Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t8: Fault occurs. Output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted. t3: Fault occurs. CT has charged to 2.5V, fault output goes high, the FET turns off allowing no output current to flow, VOUT floats up to ground. t9 = t4: Output short circuit released, still in fault mode. t4: Retry. CT has discharged to 0.5V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT pulled down towards VSS. t10 = t0: Fault released, safe condition. Return to normal operation of the hot swap power manager. Figure 2. Retry Operation Mode 5 UCC1921 UCC2921 UCC3921 APPLICATION INFORMATION (cont.) UDG-96277 t0: Safe condition. Output current is nominal, output voltage is at the negative rail, VSS. is still exceeded, CT begins charging again, FET is on, VOUT pulled down towards VSS. t1: Fault control reached. Output current rises above the programmed fault value, CT begins to charge at ~36µA. t8 = t3: Fault occurs. CT has charged to 2.5V, fault output goes high as indicated by the SDFLTCH voltage, the FET turns off allowing no output current to flow, VOUT floats up to ground, and since there is an 82kΩ resistor from SDFLTCH to VSS, the internal latchset signal goes high. t2: Maximum current reached. Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t9: Output is latched off. Even though CT has discharged to 0.5V, there will not be a retry since the latchset signal was allowed to remain high. t3: Fault occurs. CT has charged to 2.5V, fault output goes high as indicated by the SDFLTCH voltage. The FET turns off allowing no output current to flow, VOUT floats up to ground, and since there is an 82kΩ resistor from the SDFLTCH pin to VSS, the internal latchset signal goes high. t10: Output remains latched off. CT has discharged all the way to 0V. t4: Since the user does not want the chip to LATCH off during this cycle, he toggles SDFLTCH high for greater than 1ms {t6 - t4 > 1ms}. t11: The output has been latched off for quite some time. The user now wishes to reset the latched off output, thus toggling SDFLTCH high for greater than 1ms {t13 - t11}. t5: The latchset signal is reset. t12 = t5: The latchset signal is reset. t6: Forcing of SDFLTCH is released after having been applied for > 1ms. t13: Forcing of SDFLTCH is released after having been applied for > 1ms. The fault had also been released during the time the output was latched off, safe condition, return to normal operation of the hot swap power manager. t7: Retry (since the latchset signal has been reset to its’ low state) - CT has discharged to 0.5V, but fault current Figure 3. Latched Operation Mode: RLATCH = 82k 6 UCC1921 UCC2921 UCC3921 APPLICATION INFORMATION (continued) output FET failure or to build redundancy into the system. During a fault, CT will charge at a rate determined by the internal charging current and the external timing capacitor. Once CT charges to 2.5V, the fault comparator switches and sets the fault latch. Setting of the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with the 1µA current source, I2, until 0.5V is reached. Once the voltage at CT reaches 0.5V, the fault latch resets, which re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the fault comparator will close the charging switch causing the cycle to repeat. Under a constant fault, the duty cycle is given by: Duty Cycle = Determining External Component Values To set RVDD (see Fig. 4) the following must be achieved: VIN min 10V > + 2mA RVDD R1 + R 2 1µA I PL + 36 µA Average power dissipation in the pass element is given by: PFETAVG = VFET • I MAX • 1µA I PL + 36 µA UDG-96278 Figure 4. Where VFET>>5V IPL can be approximated as: VFET RPL In order to estimate the minimum timing capacitor, CT, several things must be taken into account. For example, given the schematic in Figure 4 as a possible (and at this point, a standard) application, certain external component values must be known in order to estimate CTMIN. Now, given the values of COUT, Load, RSENSE, VSS, and the resistors determining the voltage on the IMAX pin, the user can calculate the approximate startup time of the node VOUT. This startup time must be faster than the time it takes for CT to charge to 2.5V (relative to VSS), and is the basis for estimating the minimum value of CT. In order to determine the value of the sense resistor, RSENSE, assuming the user has determined the fault current, RSENSE can be calculated by: and where IPL>>36µA, the duty cycle can be approximated as : 1µA • RPL VFET Therefore, the maximum average power dissipation in the MOSFET can be approximated by: PFET AVG = VFET • I MAX • = IMAX • 1µA • RPL 1µA • RPL VFET Notice that in the approximation, VFET cancels, thereby limiting the average power dissipation in the NMOS pass element. RSENSE = 50mV I FAULT Next, the variable IMAX must be calculated. IMAX is the maximum current that the UCC3921 will allow through the transistor, M1, and it can be shown that during startup with an output capacitor the power MOSFET, M1, can be modeled as a constant current source of value IMAX where Overload Comparator The linear amplifier in the UCC3921 ensures that the output NMOS does not pass more than IMAX (which is VIMAX/RSENSE). In the event the output current exceeds the programmed IMAX by 0.2V/RSENSE, which can only occur if the output FET is not responding to a command from the IC, CT will begin charging with I3, 1mA, and continue to charge to approximately 8V. This allows a constant fault to show up on the SDFLTCH pin, and also since the voltage on CT will continue charging past 2.5V in an overload fault mode, it can be used for detection of I MAX = VIMAX where VIMAX = voltage on pin IMAX. RSENSE Given this information, calculation of the startup time is now possible via the following: 7 UCC1921 UCC2921 UCC3921 APPLICATION INFORMATION (continued) Resistive Load: Current Source Load: TSTART = CT min = 3 • TSTART • ( 36 µA • R PL + VSS − 5V − I MAX • ROUT ) 5 • RPL COUT • VSS I MAX − I LOAD Resistive Load: TSTART = +  I MAX • ROUT COUT • ROUT • n   I MAX • ROUT − VSS  l     Level Shift Circuitry to Interface with SDFLTCH Some type of circuit is needed to interface with the UCC3921 via SDFLTCH, such as opto-couplers or level shift circuitry. Figure 6 depicts one implementation of level shift circuitry that could be used, showing component values selected for a typical –48V telecommunications application. There are three communication conditions which could occur; two of which are Hot Swap Power Manager (HSPM) state output indications, and the third being an External Shutdown. Once TSTART is calculated, the power limit feature of the UCC3921 must be addressed and component values derived. Assuming the user chooses to limit the maximum 25 R PL===∞ ∞∞ 22.5 IMAX = 4A 20 1) When open, and under a non-fault condition, SDFLTCH is pulled to a low state. In Figure 6, the Nchannel level shift transistor is off, and the FAULT OUT signal is pulled to LOCAL VDD through R3. This indicates that the HSPM is not faulted. 17.5 15 R PL = 10M 12.5 R PL = 5M 10 2) When a fault is detected by the fault timer or undervoltage lockout, this pin will drive to a high state, indicating that the external power FET is off. In Figure 6, the N-channel level shift transistor will conduct, and the FAULT OUT signal will be pulled to a Schottky Diode voltage drop below LOCAL GND. This indicates that the HSPM is faulted. The Schottky Diode is necessary to ensure that the FAULT OUT signal does not traverse too far below LOCAL GND, making fault detection difficult. 7.5 R PL = 2M 5 R PL = 1M 2.5 0 R PL = 500k R PL = 200k 0 25 50 3 • ROUT • VSS • COUT 5 • RPL 75 100 125 150 175 200 VFET Figure 5. Plot Average Power vs FET Voltage for Increasing Values of RPL allowable average power that will be associated with the hot swap power manager, the power limiting resistor, RPL, can be easily determined by the following: RPL = PFET avg 1µA • I MAX where a minimum RPL exists defined by RPL min = VSS (Refer to Figure 5). 5 mA Finally, after computing the aforementioned variables, the minimum timing capacitor can be derived as such: Current Source Load: UDG-96279 CT min = 3 • TSTART • ( 72 µA • R PL + VSS − 10V ) 10 • RPL Figure 6. Possible Level Shift Circuitry to Interface to the UCC3921, showing component values selected for a typical telecom application. 8 UCC1921 UCC2921 UCC3921 APPLICATION INFORMATION (continued) limited to 10mA or less: ISDFLTCHMAX < 10mA. If a 5k < RLATCH < 250kΩ resistor is tied between SDFLTCH & VSS, as optionally shown in Figure 6, then the latched operating mode (described earlier) will be invoked upon the occurrence of a fault. SAFETY RECOMMENDATIONS Although the UCC3921 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3921 is intended for use in safety critical applications where  UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the external power FET. The UCC3921 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. 3) To externally shutdown the HSPM, the SHUTDOWN signal (typically held at LOCAL VDD) must be pulled to LOCAL GND. Assuming SHUTDOWN is tied to LOCAL GND, the P-channel level shift transistor will conduct, driving SDFLTCH high (to roughly VDD plus a diode). By sourcing > 250µA into SDFLTCH for > 1ms the output to the external power FET will be disabled. The current sourced into SDFLTCH must be Ω UDG-98053 Figure 7. Typical Telecommuications Application (The “Negative Magnitude-Side” of the Supply is Switched in) 9 UCC1921 UCC2921 UCC3921 APPLICATION INFORMATION (continued) Ω UDG-98054 Figure 8. Floating Positive Application The “Ground-side” of the Supply is Switched In UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 10 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) UCC2921D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2921 UCC2921DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2921 UCC2921DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2921 UCC3921D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3921 UCC3921DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3921 UCC3921DTR/81143 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR UCC3921 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of